CN214586331U

CN214586331U - Display module and display device

Info

Publication number: CN214586331U
Application number: CN202022758417.8U
Authority: CN
Inventors: 姜晓婷; 戴珂; 杨海鹏; 张春旭; 程敏; 芮洲
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-11-02
Anticipated expiration: 2030-11-25

Abstract

The utility model provides a display module assembly and display device belongs to and shows technical field. The utility model discloses a display module, which comprises a display panel and a light control panel which are arranged in a laminated way; the light control panel is provided with a light adjusting area and a peripheral area surrounding the light adjusting area; the light control panel includes: the liquid crystal display panel comprises a first substrate, a second substrate and a first liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the first liquid crystal layer is arranged between the first substrate and the second substrate; wherein the first substrate includes: the signal transmission line is arranged on one side, close to the first liquid crystal layer, of the first substrate and is positioned in the peripheral area; the second substrate includes: the first black matrix layer is arranged on one side, close to the first liquid crystal layer, of the second substrate and is positioned in the light adjusting area and the peripheral area; the first black matrix layer is provided with a groove positioned in the peripheral area, and the orthographic projection of at least part of the groove on the first substrate is positioned on one side, close to the dimming area, of the orthographic projection of the signal transmission line on the first substrate.

Description

Display module and display device

Technical Field

The utility model belongs to the technical field of show, concretely relates to display module assembly and display device.

Background

With the continuous development of display technologies by users, the industry can adopt various technologies to improve the contrast of a display picture, and a dual-box area brightness adjustment technology is one of the technologies. At present, a display device adopting a dual-box area brightness adjustment technology generally comprises a light control panel and a display panel, wherein the light control panel is in black-and-white display to control the display brightness of different areas, and the display panel is in normal display. By adopting the double-box area brightness adjusting technology, the contrast of the display picture can be improved to more than 100000 from the original 1000, so that the contrast of the display picture can be obviously improved, the display effect is improved, and the use experience of a user is improved.

SUMMERY OF THE UTILITY MODEL

The utility model discloses aim at solving one of the technical problem that exists among the prior art at least, provide a display module assembly and display device.

In a first aspect, a display module according to an embodiment of the present disclosure includes a display panel and a light control panel stacked in a stack; the light control panel is provided with a light adjusting area and a peripheral area surrounding the light adjusting area; the light control panel includes: the liquid crystal display panel comprises a first substrate, a second substrate and a first liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the first liquid crystal layer is arranged between the first substrate and the second substrate; wherein the content of the first and second substances,

the first substrate includes:

a first substrate having a first surface and a second surface,

the signal transmission line is arranged on one side, close to the first liquid crystal layer, of the first substrate and is positioned in the peripheral area;

the second substrate includes:

a second substrate, which is a substrate,

the first black matrix layer is arranged on one side, close to the first liquid crystal layer, of the second substrate and is positioned in the dimming area and the peripheral area; wherein the content of the first and second substances,

the first black matrix layer is provided with a groove positioned in the peripheral area, and the orthographic projection of at least part of the groove on the first substrate is positioned on one side, close to the dimming area, of the orthographic projection of the signal transmission line on the first substrate.

Wherein the slot includes a continuous pattern surrounding the dimming area.

Wherein the number of the slots is at least one, the signal transmission line is arranged around the dimming area,

the dimming area comprises a first side and a second side which are oppositely arranged along a first direction, and a third side and a fourth side which are oppositely arranged along a second direction;

each of the slots comprises a first slot part and a second slot part which are oppositely arranged along a first direction, and a third slot part and a fourth slot part which are oppositely arranged along a second direction;

the distance from the first groove part of the notch closest to the light adjusting area to the first side edge of the light adjusting area is equal to the distance from the second groove part of the notch to the second side edge of the light adjusting area, and the distance is d 1;

the slot closest to the dimming area has a first slot part with a closest distance to the signal transmission line equal to a closest distance between a second slot part with a distance d 2;

the distance from the third groove part of the notch closest to the light adjusting area to the third side edge of the light adjusting area is equal to the distance from the fourth groove part of the notch to the fourth side edge of the light adjusting area, and the distance is d 3;

the slot closest to the dimming area has the nearest distance from the third slot part to the signal transmission line equal to the nearest distance from the fourth slot part to the signal transmission line, and the distance is d 4;

d1:d2＝kd3:d4，0.8＜k＜1.2。

wherein the range of d1: d2 is 4: 1-6: 1.

The first substrate further comprises a signal connecting line arranged on the first substrate; the signal connecting line comprises a first sub-signal line and a second sub-signal line which are electrically connected and are positioned at different layers; the connection position of the first sub signal line and the second sub signal line is positioned in the peripheral area; the slot is formed with a protrusion at a connection position corresponding to the first sub-signal line and the second sub-signal line, so that the slot and an orthographic projection of the connection position of the first sub-signal line and the second sub-signal line on the first substrate do not overlap.

Wherein the first sub-signal line includes a first common electrode line, and the second sub-signal line includes a first common voltage introduction line; one end of the first public voltage lead-in wire is connected with the first public electrode wire, and the other end of the first public voltage lead-in wire is connected with the first public electrode;

an orthographic projection of the protruding part on the first substrate is overlapped with an orthographic projection of the first common electrode line on the first substrate.

Wherein the signal transmission line includes a first common electrode line.

Wherein the first substrate further comprises:

a plurality of dimming cells and a plurality of redundant dimming cells, wherein the dimming cells and the redundant dimming cells are arranged on one side of the first substrate close to the first liquid crystal layer, the dimming cells are positioned in the dimming area, and the redundant dimming cells are positioned in the peripheral area; each of the plurality of dimming cells and the plurality of redundant dimming cells includes a first thin film transistor, a dimming electrode, and a first common electrode disposed on the first substrate;

the dimming electrode of the redundant dimming unit is electrically connected with the first common electrode.

Wherein there is an overlap between the orthographic projection of the slot on the first substrate and the orthographic projection of the redundant dimming unit on the first substrate.

Wherein the plurality of dimming cells and the plurality of redundant dimming cells are arranged side by side along a second direction to form a plurality of first dimming cell groups, and the dimming cell and the redundant dimming cell in each of the plurality of first dimming cell groups are arranged along a first direction; the plurality of dimming cells and the plurality of redundant dimming cells are arranged side by side along a first direction to form a plurality of second dimming cell groups, and the dimming cells and the redundant dimming cells in each of the plurality of second dimming cell groups are arranged along a second direction; the gates of the first thin film transistors of the dimming units and the redundant dimming units in the same first dimming unit group are connected with the same first grid line; each dimming unit and the redundant dimming unit in the same second dimming unit group are provided with data voltages through two first data lines, and the source electrodes of the adjacent first thin film transistors are connected with different first data lines;

the first substrate further includes:

the first transparent conducting layer is arranged on one side, close to the first liquid crystal layer, of the first substrate and comprises the dimming electrode; the light adjustment electrode includes a plurality of first openings arranged side by side in the second direction, each of the plurality of first openings extending in the first direction;

the first metal conducting layer is arranged on one side, close to the first liquid crystal layer, of the first substrate and comprises a plurality of first grid lines, grid electrodes of the first thin film transistors and a common electrode line, the first grid lines are arranged side by side along a second direction, each first grid line extends along a first direction, and orthographic projections of the first grid lines and the grid electrodes of the first thin film transistors on the first substrate fall in orthographic projections of the first opening parts on the first substrate;

the first grid insulating layer is arranged on one side, away from the first substrate, of the first metal conducting layer;

the active semiconductor layer is arranged on one side, away from the first metal conducting layer, of the first grid insulating layer; the active semiconductor layer includes an active layer of each of the first thin film transistors;

the second metal conducting layer is arranged on one side, away from the first grid electrode insulating layer, of the active semiconductor layer and comprises a plurality of first data lines arranged side by side along a first direction, and a source electrode and a drain electrode of each first thin film transistor, and the source electrode and the drain electrode of each first thin film transistor are respectively connected with the active layer; each of the plurality of first data lines extends in a second direction;

the first interlayer insulating layer is arranged on one side, away from the first interlayer insulating layer, of the second metal conducting layer, and the first substrate further comprises a first connecting through hole, a second connecting through hole and a third connecting through hole, wherein the first connecting through hole penetrates through the first interlayer insulating layer and the first grid insulating layer;

the second transparent conducting layer is arranged on one side, away from the second metal conducting layer, of the first interlayer insulating layer and comprises first common electrodes of all the dimming units and all the redundant dimming units and first connecting electrodes; the first connection electrode electrically connects the drain electrode of the first thin film transistor and the dimming electrode through the first connection via and the third connection via; the first common electrode is electrically connected with the first common electrode line through the second connecting via hole.

The first black matrix layer comprises a first light shielding part positioned in the light adjusting area and a second light shielding part positioned in the peripheral area;

the first light shielding portion includes a plurality of sub light shielding portions arranged side by side in the second direction, each of the plurality of sub light shielding portions extending in the first direction; and the orthographic projection of one sub-shading part on the first substrate covers the orthographic projection of one first grid line on the first substrate.

Wherein the light adjustment electrode further includes a plurality of second opening portions arranged side by side in the first direction, each of the plurality of second opening portions extending in the second direction; and the orthographic projection of the first data line on the first substrate is in the orthographic projection of the second opening part on the first substrate.

The second transparent conducting layer further comprises a plurality of third openings which are formed on the light modulation electrodes and are arranged side by side along the second direction; each of the plurality of third opening portions extends along a first direction, one third opening portion is arranged corresponding to one first gate line portion, and orthographic projections of the third opening portions and the first gate line portion on the first substrate are at least partially overlapped.

The first transparent conducting layer further comprises a plurality of first connecting parts arranged at intervals, and the first connecting parts are electrically connected with the dimming electrodes in the redundant dimming units and directly overlapped with the first common electrode wires.

The first substrate further comprises a gate driving circuit arranged on the first substrate and positioned in the peripheral area, and a plurality of gate signal leading-in lines, detection signal lines and compensation signal lines connected with the gate driving circuit; one of the gate signal lead-in lines is connected to one of the first gate lines; the detection signal line is connected with one first grid line;

the first metal conductive layer further comprises the detection signal line and the compensation signal line;

the second metal conductive layer further includes the plurality of gate signal introduction lines.

The end part of the first grid line is connected with a second connecting part, and the end part of the grid signal leading-in line is connected with a third connecting part; the second transparent conductive layer further comprises a second connection electrode; the first substrate further comprises a fourth connecting via hole penetrating through the first gate insulating layer and the first interlayer insulating layer, and a fifth connecting via hole penetrating through the first interlayer insulating layer; the second connection electrode electrically connects the second connection portion and the third connection portion through the fourth connection via hole and the fifth connection via hole.

The first metal conducting layer further comprises a redundant grid line extending along a first direction, and the redundant grid line is connected with the first common electrode line; at least one of the first dimming cell groups includes only the redundant dimming cell, and a first gate line connected to a gate of the first thin film transistor in the first dimming cell group is connected to the first common electrode line.

Wherein the width of the slot is greater than or equal to 18 μm.

The display panel comprises a third substrate, a fourth substrate and a second liquid crystal layer, wherein the third substrate and the fourth substrate are oppositely arranged, and the second liquid crystal layer is arranged between the third substrate and the fourth substrate; the third substrate is positioned on one side of the second substrate, which is far away from the first liquid crystal layer; the display panel is provided with a display area and a non-display area surrounding the display area;

an orthographic projection of the display region on the first substrate is located within an orthographic projection of the dimming region on the first substrate.

In a second aspect, an embodiment of the disclosure provides a display device, which includes any one of the display modules described above.

Drawings

FIG. 1 is a schematic diagram of an exemplary dual cell display module.

Fig. 2 is a schematic layout view of the dimming cells of the light control panel in the display module shown in fig. 1.

Fig. 3 is a cross-sectional view of a light adjusting region of a light control panel in the display module shown in fig. 1.

Fig. 4 is a cross-sectional view of a peripheral region of a light control panel in the display module shown in fig. 1.

Fig. 5 is a cross-sectional view of a display area of a display panel in the display module shown in fig. 1.

Fig. 6 is a cross-sectional view of a non-display area of a display panel in the display module shown in fig. 1.

FIG. 7 is a schematic view of a first black matrix layer of a light control panel in the display module shown in FIG. 1.

Fig. 8 is a schematic view of a first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure.

Fig. 9 is a schematic view of another first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure.

Fig. 10 is a layout of a display module according to an embodiment of the present disclosure.

Fig. 11 is a schematic view of a display module according to an embodiment of the disclosure.

Fig. 12 is a schematic view of a first transparent conductive layer in a display module according to an embodiment of the disclosure.

Fig. 13 is a schematic view of a first metal conductive layer in a display module according to an embodiment of the disclosure.

Fig. 14 is a schematic view of an active semiconductor layer in a display module according to an embodiment of the disclosure.

Fig. 15 is a schematic view of a second metal conductive layer in a display module according to an embodiment of the disclosure.

Fig. 16 is a schematic view illustrating a distribution of via holes in an interlayer insulating layer in a display module according to an embodiment of the disclosure.

Fig. 17 is a schematic view of a second transparent conductive layer in a display module according to an embodiment of the disclosure.

Fig. 18 is a schematic connection diagram of a first common electrode and a first common electrode line in a display module according to an embodiment of the disclosure.

Fig. 19 is a schematic connection diagram of a second connection portion and a third connection portion in a display module according to an embodiment of the disclosure.

Fig. 20 is a schematic view of another first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1 is a schematic diagram of an exemplary dual-cell display module, as shown in fig. 1, which includes a light control panel 100 and a display panel 200 stacked in a stacked manner. The light control panel 100 is used for controlling the light transmittance of the light emitted by the backlight source; the display panel 200 is used for displaying a screen.

FIG. 2 is a schematic layout view of a light modulating unit of a light control panel in the display module shown in FIG. 1; FIG. 3 is a cross-sectional view of a light adjusting region of a light control panel in the display module shown in FIG. 1; fig. 4 is a cross-sectional view of a peripheral region of a light control panel in the display module shown in fig. 1. As shown in fig. 2 to 4, the light control panel 100 has a light adjusting region Q11 and a peripheral region Q12 surrounding the light adjusting region Q11; the dimming region Q11 has dimming components, and the peripheral region Q12 has signal transmission lines for providing signals for the dimming components; in the following description, a signal transmission line is taken as the first common electrode line 20 as an example, and it should be understood that the signal transmission line is not limited to the first common electrode line 20, and may also include a ground line, etc., and therefore the signal transmission line is the first common electrode line 20 and does not limit the protection scope of the embodiments of the present disclosure.

Specifically, the light control panel 100 includes a first substrate and a second substrate disposed opposite to each other, and a first liquid crystal layer 30 disposed between the first substrate and the second substrate, and a first lower polarizer (not shown) is disposed on a side of the first substrate away from the first liquid crystal layer; the first substrate includes a first base 11, a plurality of dimming cells 01 disposed on the first base 11 and located in the dimming area Q11, a plurality of redundant dimming cells (not shown) disposed on the first base 11 and located in the peripheral area Q11, and a first common electrode line 20, wherein the redundant dimming cells are disposed on a side of the first common electrode line 20 close to the dimming area Q11; the dimming unit 01 and the redundant dimming unit may have the same structure, and the redundant dimming unit may repair the dimming unit 01 when there is a failure in the dimming unit Q11. Each of the dimming cells 01 and the redundant dimming cells may include a first thin film transistor T1, a dimming electrode 010, and a first common electrode 020. The second substrate includes a second base 21, a first black matrix layer BM1 disposed on the second base 21; the first black matrix layer BM1 has a plurality of first hollow portions located in the dimming area Q11, and one first hollow portion corresponds to one dimming electrode 010, for example: the first hollow portions are arranged in one-to-one correspondence with the light modulation electrodes 010, and orthographic projections of the first hollow portions and the light modulation electrodes 010 on the first substrate 11 are completely overlapped.

With reference to fig. 3, in the first substrate, the light modulation electrode 010 and the first common electrode 020 are sequentially disposed on the first substrate 11, wherein the light modulation electrode 010 can be a plate electrode, the first common electrode 020 can be a slit electrode, and since the light control panel 100 is used to adjust the light transmittance of the backlight, the light control panel 100 can transmit light, the light modulation electrode 010 and the first common electrode 020 are made of a transparent conductive material, for example: indium tin oxide ITO. In addition, since the same voltage can be applied to the first common electrode 020 of each light modulation unit 01 and the redundant light modulation unit in operation, each first common electrode 020 can be formed integrally. The first thin film transistors T1 are bottom gate thin film transistors, and the gates thereof are made of a metal conductive material, and since the patterning process (wet etching) of the gates is different from the patterning process (dry etching) of the light adjustment electrodes 010, the gates of the first thin film transistors T1 can be directly formed on the layer where the light adjustment electrodes 010 are located. The first common electrode line 20 may be disposed at the same layer as the gate of each of the first thin film transistors T1, and may be made of the same material, that is, the first common electrode line 20 is formed at the same time when the gate of each of the first thin film transistors T1 is formed. A first gate insulating layer 12 is formed on the layer on which the gate electrode of each first thin film transistor T1 is located. The active layer of each first thin film transistor T1 is formed on the first gate insulating layer 12. A respective source electrode and drain electrode are formed on the active layer of each first thin film transistor T1. A first interlayer insulating layer 13 is formed on the source and drain electrodes of each of the first thin film transistors T1, and a first common electrode 020 is formed on the first interlayer insulating layer 13; at this time, the first connection electrode 14 may be formed at a layer where the first common electrode 020 is formed, and the first common electrode 020 and the first connection electrode 14 may be made of the same material, that is, they may be formed in one patterning process. The first substrate further has a first connection via penetrating the first gate insulating layer 12 and the first interlayer insulating layer 13, and a third connection via penetrating the first interlayer insulating layer 13, and the first connection electrode 14 may electrically connect the drain electrode of the first thin film transistor T1 and the dimming electrode 010 through the first connection via and the second connection via. It should be noted that the first connecting via and the third connecting via may be formed by a single patterning process, and may be independently disposed and may be connected to each other. In addition, the first substrate further includes a second connection via penetrating the first gate insulating layer 12 and the first interlayer insulating layer 13, and the first common electrode 020 and the first common electrode line 20 are electrically connected through the second connection via.

For example: with continued reference to fig. 2, the dimming cells 01 and the redundant dimming cells in the first substrate may be arranged in an array, forming a plurality of first dimming cell groups 10a arranged side by side along the second direction, the dimming cells 01 and the redundant dimming cells in each first dimming cell group 10a being arranged along the first direction, while also forming a plurality of second dimming cell groups 10b arranged side by side along the first direction, the dimming cells 01 and the redundant dimming cells in each second dimming cell group 10b being arranged along the second direction. It should be noted that the first direction and the second direction intersect, for example, they form an angle of 90 °, that is, one of the first direction and the second direction is the row direction X, and the other is the column direction Y. In the embodiments of the present disclosure, the first direction is taken as the row direction X, and the second direction is taken as the column direction Y. In addition, the following description is given taking as an example that the dimming cells 01 and the redundant dimming cells in the first substrate may be arranged in an array.

FIG. 5 is a cross-sectional view of a display area of a display panel in the display module shown in FIG. 1; FIG. 6 is a cross-sectional view of a non-display area of a display panel in the display module shown in FIG. 1; as shown in fig. 5 and 6, the display panel 200 has a display area and a non-display area surrounding the display area; the display panel 200 includes: a third substrate and a fourth substrate which are oppositely arranged, and a second liquid crystal layer 50 which is arranged between the third substrate and the fourth substrate, wherein a second lower polarizer (not shown) is formed on one side of the third substrate which is far away from the second liquid crystal layer 50, and a first upper polarizer (not shown) is formed on one side of the fourth substrate which is far away from the liquid crystal layer. Specifically, the third substrate includes a third substrate 31 disposed on the third substrate 31 and located in the plurality of sub-pixels of the display area; each sub-pixel includes a pixel electrode 030, a second thin film transistor T2, a second common electrode 040, a second common electrode line 40 disposed on the third substrate 31 and located in the non-display region, and a redundant sub-pixel (not shown), and the pixel electrode 030 in each sub-pixel is electrically connected to the drain of the second thin film transistor T2 through a connection electrode 34. The redundant sub-pixels are located on one side of the second common electrode line 40 close to the display area, and the redundant sub-pixels have the same structure as the sub-pixels and are used for repairing the sub-pixels when the sub-pixels have problems. The fourth substrate includes a fourth substrate 41, a second black matrix layer BM2 provided on the fourth substrate 41, and a color filter layer 42; the color filter layer 42 includes color filters of different colors, such as: the color filter is arranged corresponding to the sub-pixels and the redundant sub-pixels one by one. The second black matrix layer BM2 has a second hollow portion formed at a position corresponding to the color filter. In addition, one sub-pixel in the display panel 200 may be disposed corresponding to one dimming cell 01 in the light control panel 100, and one redundant sub-pixel may be disposed corresponding to one redundant dimming cell. Of course, a plurality of sub-pixels arranged in an array in the display panel 200 may be disposed corresponding to one dimming unit 01 in the light control panel 100, and correspondingly, a plurality of redundant sub-pixels arranged in an array may be disposed corresponding to one redundant dimming unit.

Note that, with reference to fig. 5 and 6, the second thin film transistor T2 is described as an example of a bottom gate thin film transistor in the embodiment of the present disclosure, but the second thin film transistor T2 may also be a top gate thin film transistor, and the embodiment of the present disclosure is not limited thereto. Here, a second gate insulating layer 32 is disposed between the gate electrode of the second thin film transistor T2 and the active layer, and a second interlayer insulating layer 33 is disposed between the pixel electrode and the source and drain electrodes of the second thin film transistor T2. In addition, the difference between the display panel 200 and the light control panel 100 is only that the color filter layer 42 and the first upper polarizer are provided in the display panel, and the remaining structure is substantially the same except for the difference in name, so the structure of the display panel 200 will not be described in detail herein.

Specifically, when a voltage is applied to the first common electrode 020 and the light adjusting electrode 010 on the first substrate, an electric field is formed between the first common electrode and the light adjusting electrode 010, so that a deflection angle of liquid crystal molecules in the first liquid crystal layer 300 is controlled, and further, a light transmittance of light emitted from the backlight source is controlled.

With continued reference to fig. 4 and 6, since the light control panel 100 has less color filter layer 42 than the display panel 200, the distance between the first black matrix layer BM1 and the first common electrode lines 20 in the peripheral region Q12 of the light control panel 100 is greater than the distance between the second black matrix layer BM2 and the second common electrode lines 40 in the non-display region of the display panel 200. FIG. 7 is a schematic view of a first black matrix layer of a light control panel in the display module shown in FIG. 1; as shown in fig. 7, the first black matrix layer BM1 is in a continuous pattern at a position corresponding to the peripheral region Q12, so as to avoid light leakage in the peripheral region Q12 of the light control panel 100. And the utility model discloses the people discovers, because the distance between the first black matrix layer BM1 of peripheral region Q12 to first common electrode line 20 is nearer on the accuse light panel, and the first black matrix layer BM1 of this position department is continuous pattern, consequently, lead to the electric charge on the first common electrode line 20 to couple to first black matrix layer BM1 very easily, and can conduct to district Q11 of adjusting luminance, thereby lead to adjusting luminance the liquid crystal molecule of district Q11 to deflect unusually, and then the problem that the marginal bright line appears when leading to the display module to shut down.

In view of the above problems, the following technical solutions are provided in the embodiments of the present disclosure. It should be noted that, in the following description, the signal transmission line is also described as the first common electrode line 20 as an example.

In a first aspect, an embodiment of the present disclosure provides a display module, which includes a light control panel 100 and a display panel 200 stacked in a stacked manner; the light control panel 100 and the display panel 200 are substantially the same as the light control panel 100 and the display panel 200 of the display module shown in fig. 1, respectively, except that the first black matrix layer BM1 of the second substrate of the light control panel 100 is different from the first black matrix layer BM1 of the display module shown in fig. 1. Fig. 8 is a schematic diagram of a first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure, as shown in fig. 8, a peripheral region Q12 of the first black matrix layer BM1 is formed with a slot 300, and an orthogonal projection of at least a part of the position of the slot 300 on the first substrate 11 is located at a side of an orthogonal projection of the first common electrode line 20 on the first substrate 11, which is close to the light modulation region Q11. With this arrangement, the charges coupled to the first black matrix layer BM1 by the first common electrode line 20 can be prevented from being conducted to the dimming area Q11 of the second substrate through the slot 300 on the first black matrix layer BM1, so that the electric field of the dimming area Q11 is prevented from being influenced by the charges coupled to the first black matrix layer BM1 by the first common electrode line 20, and the problem of bright lines when the device is turned off is avoided.

In some embodiments, with continued reference to fig. 8, the slot 300 on the first black matrix layer BM1 is a continuous pattern surrounding the dimming area Q11. That is, the portion of the first black matrix layer BM1 corresponding to the first common electrode line 20 and the portion corresponding to the dimming region Q11 can be separated by the slot 300, which is equivalent to forming a separation zone between the first common electrode line 20 and the dimming region Q11, so that charges coupled to the first black matrix layer BM1 from the first common electrode line 20 can be effectively prevented from being conducted to the dimming region Q11 of the second substrate.

As shown in fig. 8, if the dimming area Q11 is rectangular, the slot 300 is in a rectangular ring pattern. Of course, if the dimming area Q11 is circular, the slot 300 may also be a circular ring pattern. The shape of the slit 300 is not particularly limited in the disclosed embodiment.

In some embodiments, the number of the slots 300 on the first black matrix layer BM1 may be multiple, such as 2, 3 or even more. FIG. 9 is a schematic view of another first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure; as shown in fig. 9, in the embodiment of the present disclosure, the number of the slots 300 on the first black matrix layer BM1 is 2, and the slots are the first slot 301 and the second slot 302 respectively; the second slot 302 is closer to the dimming area Q11 than the first slot 301. The first common electrode line 20 is disposed around the dimming area Q11, and at this time, the first slot 301 and the second slot 302 are both disposed around the dimming area Q11. Take dimming area Q11 as a rectangle for example. The light adjusting area Q11 includes a first side a and a second side b oppositely disposed in the row direction X, and a third side c and a fourth side d oppositely disposed in the column direction Y. The first and

second slots

301 and 302 each include first and second groove portions 300a and 300b oppositely disposed in the row direction X, and third and fourth groove portions 300c and 300d oppositely disposed in the column direction Y. Fig. 10 is a layout of a display module according to an embodiment of the present disclosure; as shown in fig. 10, the distance from the first slot 300a of the second slot 302 to the first side a of the dimming region Q11 is equal to the distance from the second slot 300b of the second slot 302 to the second side a of the dimming region Q11, and both are d 1; the minimum distance between the first slot part 300a of the second slot 302 and the first common electrode line 20 is equal to the minimum distance between the second slot part 300a of the second slot 302 and the first common electrode line 20, and both are d 2; the distance from the third slot 300c of the second slot 302 to the third side c of the dimming region Q11 is equal to the distance from the fourth slot 300d of the second slot 302 to the fourth side d of the dimming region Q11, and both are d 3; the minimum distance between the third slot 300c of the second slot 302 and the first common electrode line 20 is equal to the minimum distance between the fourth slot 300d of the second slot 302 and the first common electrode line 20, and is d 4. In the disclosed embodiments, d1: d2 ═ kd3: d4, 0.8 < k < 1.2. It is preferable that k be 1 so as to ensure that the slits in the first black matrix layer BM1 have substantially the same or the same insulating ability in the row direction X and the column direction Y of the dimming region Q11 with respect to the charges coupled to the first black matrix layer BM1 by the first common electrode lines 20. Thus, even if the charges coupled to the first black matrix layer BM1 by the first common electrode lines 20 enter the dimming area, the influence on the dimming area in the row direction X and the column direction Y is the same, and the display abnormality of the display panel 200 caused by the protrusion of the influence of a certain area of the dimming area is avoided as much as possible. In some embodiments of the present invention, the,

it should be noted that, although the number of the slots 300 is 2 in the above description, in an actual product, the number of the slots 300 depends on the width of the first common electrode line 20 in the peripheral region Q12, the size of the display module, and other factors, and of course, the number of the slots 300 may also be 1. In the embodiment of the present disclosure, when the number of the slots 300 is plural, the following condition is satisfied. The slot 300 closest to the dimming area Q11 has a distance from the first slot 300a to the first side a of the dimming area Q11 equal to the distance from the second slot 300d to the second side b of the dimming area Q11, and has a distance d 1; a slot closest to the dimming area Q11, the minimum distance from the first slot portion 300a to the first common electrode line 20 of which is equal to the minimum distance from the second slot portion 300b to the first common electrode line 20, and the distance is d 2; the slot 300 closest to the dimming area Q11 has a distance from the third slot 300c to the third side c of the dimming area Q11 equal to the distance from the fourth slot 300d to the fourth side d of the dimming area Q11, and has a distance d 3; the slot 300 closest to the dimming area Q11 has the minimum distance from the third slot 300c to the first common electrode line 20 equal to the minimum distance from the fourth slot 300d to the first common electrode line 20, and the distance is d 4; d1, d2, kd3, d4, k < 0.8 < 1.2.

For example: d1: d 2: d3: d4, the ratio is 4: 1-6: 1, preferably d1: d 2: d3: d 4: 5:1, and the ratio can be specifically set according to the size d1: d2 (or d3: d4) of the display module.

In some embodiments, when the number of the slots 300 is plural, and the plural slots 300 are disposed around the dimming area Q11, for example, a rectangular display module is taken, wherein the distance between two adjacent slots 300 in the row direction X is about 140 μm, and the distance in the column direction Y is about 210 μm.

In some embodiments, the first common electrode 020 of the first substrate 11 of the light control panel 100 is provided with a first alignment layer at a side close to the first liquid crystal layer 300, and the second alignment layer is provided at a side of the first black matrix layer BM1 of the second substrate 21 close to the first liquid crystal layer 300, and grooves are formed on the first and second alignment layers through a rubbing process to provide an initial alignment direction to the liquid crystal molecules of the first liquid crystal layer 30. Signal connection lines for supplying external signals to the dimming devices in the dimming cell 01 are also provided on the first substrate 11 of the light control panel 100. And the signal connection lines may be formed by electrically connecting sub-signal lines located at different layers in order to facilitate the wiring of the signal connection lines. In the embodiment of the present disclosure, the signal connection line is formed by electrically connecting the first sub-signal line and the second sub-signal line which are located at different positions. For example: the first sub-signal connection line and the gate of the first thin film transistor T1 are disposed in the same layer and have the same material, and the second sub-signal connection line and the source and the drain of the first thin film transistor T1 are disposed in the same layer and have the same material, that is, the first sub-signal connection line and the gate of the first thin film transistor T1 are fabricated in a one-step patterning process, and the second sub-signal connection line and the source and the drain of the first thin film transistor T1 are fabricated in a one-step patterning process. In this case, the first sub-signal line and the second sub-signal line need to be electrically connected through a via hole penetrating the first gate insulating layer. Here, the connection positions of the first sub-signal line and the second sub-signal line for signal connection are located in the peripheral region Q12. Because the first sub-signal line and the second sub-signal line are located at different layers, the positions of the two electrical connections need to be overlapped by two layers of structures to realize the electrical connection, thus, the thickness of the connection position of the first sub-signal line and the second sub-signal line is caused to be different from the thickness of the other positions, thereby causing the rubbing of the first alignment layer at the position to form the groove and other position abnormality, so the arrangement of the liquid crystal molecules in the area is abnormal, so the first black matrix layer BM1 is required to shield the part, and therefore, the slot 300 in the embodiment of the present disclosure needs to bypass the connection position of the first sub-signal line and the second sub-signal line, that is, as shown in fig. 10, the slot 300 is formed with a protrusion 310 at a connection position corresponding to the first sub-signal line and the second sub-signal line, so that there is no overlap in the orthographic projections of the connection positions of the slot 300 and the first and second sub-signal lines on the first substrate 11.

In one example, the signal connection line is configured to provide a common voltage signal to the first common electrode 020, and the first sub-signal line of the signal connection line may be the first common electrode line 20, and the second sub-signal line may be the first common voltage lead-in line; one end of the first common voltage lead-in wire is connected with the first common electrode wire 20, and the other end is connected with the first common electrode 020; at this time, there is an overlap between an orthogonal projection of the protrusion 310 of the slot 300 on the first substrate 11 and an orthogonal projection of the first common electrode line 20 on the first substrate 11. That is, the protruding portion 310 protrudes toward the side away from the dimming area Q11. Hereinafter, the first sub-signal line may be the first common electrode line 20, and the second sub-signal line may be the first common voltage lead-in line. In some embodiments, there is an overlap between the orthographic projection of the slot 300 on the first substrate 11 and the orthographic projection of the redundant dimming cell on the first substrate 11. For example: the redundant dimming unit is located on one side of the first common electrode line 20 close to the dimming area Q11, and is adjacent to the first common electrode line 20. In the embodiment of the present disclosure, there is an overlap between the orthographic projection of the slot 300 on the first substrate 11 and the orthographic projection of the redundant dimming cell on the first substrate 11, that is, the position of the slot 300 is closer to the first common electrode line 20, so that the charges coupled to the first black matrix layer BM1 by the first common electrode line 20 can be effectively prevented from being conducted to the dimming area.

In some embodiments, the width of the groove on the first black matrix layer BM1 is greater than or equal to 18 μm. Of course, the width of the slot 300 may be specifically set according to the signal line on the first substrate 11, the position of the dimming cell 01, the redundant dimming cell, and the like.

In some embodiments, the width of the display area of the display panel 200 in the display module is smaller than the width of the light-controlling panel 100, so as to prevent the deviation of the alignment precision between the display panel 200 and the light-controlling panel 100 from affecting the normal display of the display panel 200. Fig. 11 is a schematic view of a display module according to an embodiment of the disclosure, and as shown in fig. 11, a display panel 200 has a display area and a non-display area surrounding the display area; the orthographic projection of the display area on the first substrate 11 is located within the orthographic projection of the dimming area Q11 on the first substrate 11. That is, there is a certain attachment tolerance (Δ Xmax) between the display area of the display panel 200 and the dimming area Q11 of the light control panel 100.

In order to make the structure of the light control panel 100 more clear in the embodiments of the present disclosure, the following description specifically describes the structure of each layer on the first substrate in the light control panel 100. Wherein, the display module is a rectangular display module as an example. At this time, the dimming region Q11 is rectangular, and the peripheral region Q12 is rectangular ring-shaped. The dimming cell 01 is located in the dimming area Q11, and the redundant dimming cell is located in the peripheral area Q12. The plurality of dimming cells 01 and the plurality of redundant dimming cells are arranged side by side in a column direction Y to form a plurality of first dimming cell groups 10a, and the dimming cells 01 and the redundant dimming cells in each of the plurality of first dimming cell groups 10a are arranged in a row direction X; the plurality of dimming cells 01 and the plurality of redundant dimming cells are arranged side by side in the row direction X to form a plurality of second dimming cell groups 10b, and the dimming cells 01 and the redundant dimming cells in each of the plurality of second dimming cell groups 10b are arranged in the column direction Y; the gates of the first thin film transistors T1 of the dimming cells and the redundant dimming cells in the same first dimming cell group 10a are connected to the same first gate line; the light modulation units 01 and the redundant light modulation units in the same second light modulation unit group 10b are provided with data voltage signals through two first data lines, the source electrodes of the first thin film transistors T1 which are adjacently arranged are connected with different first data lines, and the first common electrodes 20 of the light modulation units 01 and the redundant light modulation units in the same second light modulation unit group 10b are connected with the same first common voltage leading-in line.

In one example, the first substrate includes a first base 11, and a first transparent conductive layer, a first metal conductive layer, a first gate insulating layer 12, an active semiconductor layer, a second metal conductive layer, a first interlayer insulating layer 13, and a second transparent conductive layer sequentially disposed on the first base 11. Among them, for example: the first transparent conductive layer may include, for example: a light adjustment electrode 010; the first metal conductive layer may include a first common electrode line 20, a first gate line, and a gate electrode of each first thin film transistor T1; the active semiconductor layer includes an active layer of each of the first thin film transistors T1; the second metal conductive layer may include a source electrode and a drain electrode of each of the first thin film transistors T1, a first data line; the second transparent conductive layer may include a first common electrode 020. The first transparent conductive layer, the first metal conductive layer, the first gate insulating layer 12, the active semiconductor layer, the second metal conductive layer, the first interlayer insulating layer 13, and the second transparent conductive layer will be specifically described below.

For example: fig. 12 is a schematic view of a first transparent conductive layer in a display module according to an embodiment of the disclosure; as shown in fig. 12, the first transparent conductive layer 1 is disposed on the first substrate 11, the first transparent conductive layer 1 includes a dimming electrode 010, and the dimming electrode 010 is located in a part of the dimming area Q11 and the peripheral area Q12; the light control electrode 010 has a plurality of first opening portions 011 arranged side by side in the column direction Y and a plurality of second opening portions 012 arranged side by side in the row direction X, each of the plurality of first opening portions 011 extends in the row direction X, each of the plurality of second opening portions 012 extends in the column direction Y, the first opening portion 011 may be in a zigzag shape as shown in fig. 12, and of course, other patterns such as a straight line may be used, and the shape of the first opening portion 011 is not particularly limited in the embodiment of the present disclosure. The reason why the first opening portion 011 is provided on the light adjustment electrode 010 is to avoid electrically connecting the first gate line with the light adjustment electrode 010 when the first gate line is formed later; the second opening 012 is provided in the light modulation electrode 010 to avoid overlapping of the first data line formed later and the orthographic projection of the first common electrode 010 on the first substrate 11 to form an overlap capacitor, so as to affect the signal written in the first data line. It should be noted here that the dimming electrodes 010 in the redundant dimming cells may be connected together, while the dimming electrodes 010 in the redundant dimming cells and the dimming electrodes 010 in the dimming cells 01 are off, and the dimming electrodes 010 in the dimming cells 01 are off.

With continued reference to fig. 12, the first transparent conductive layer 1 further includes a plurality of first connection portions 013 disposed at intervals in the peripheral region Q12, where the first connection portions 013 are used to electrically connect the dimming electrodes 010 in the redundant dimming cells to the first common electrode lines 20 formed subsequently. The dimming electrode 010 and the first connection portion 013 in the redundant dimming unit may be integrally formed. The shape of the first connection portion 013 may be a rectangle as shown in fig. 12, but may be other shapes such as a circle, and is not limited herein.

For example: fig. 13 is a schematic view of a first metal conductive layer in a display module according to an embodiment of the disclosure; as shown in fig. 13, the first metal conductive layer 2 is formed on the first transparent conductive layer 1. The first metal conductive layer 2 includes a plurality of first gate lines 201 arranged side by side in a column direction Y, each of the plurality of first gate lines 201 extends in a row direction X, the first gate lines 201 are arranged in one-to-one correspondence with the first opening portions 011, and an orthogonal projection of the first gate lines 201 on the first substrate 11 falls within an orthogonal projection of the first opening portions 011 on the first substrate 11. The first metal conductive layer 2 further includes a gate 202 of each first thin film transistor T1, and the gate 202 of the first thin film transistor T1 is connected to the first gate line 201, which may be an integrated structure. The first metal conductive layer 2 further includes a first common electrode line 20 located in the peripheral region Q12, and the first common electrode line 20 and the first connection portion 013 in the first transparent conductive layer 1 may directly overlap to electrically connect the first common electrode 010 and the first common electrode line 20.

With continued reference to fig. 13, the end portion of the first gate line 201 is connected with a second connection portion 205, and the second connection portion 205 may be integrally formed with the first gate line 201 to electrically connect a subsequently formed gate signal lead-in line with the first gate line 201.

With continued reference to fig. 13, the first metal conductive layer 2 further includes a redundancy gate line 206; when only the redundant dimming cell is included in the first dimming cell group 10a, the gate 202 of the first thin film transistor T1 in the redundant dimming cell is connected to the redundant gate line 206, and since the redundant dimming cell does not need to operate during displaying, the redundant gate line 206 and the first common electrode line 20 can be connected to form an integral structure.

Note that, on one side of the peripheral region Q12, there is a bonding region where connection pads are provided for bonding with an external circuit, for example: COF, FPC, PCB; and the connection pads also need to be electrically connected to the respective signal lead-in lines (fanout lines) to supply signals to the respective signal lines on the first substrate. Of course, the first substrate is further provided with a Gate driving circuit (e.g., Gate On Array (GOA)) and other structures. With reference to fig. 13, the first substrate further includes a detection signal line 204 and a compensation signal line 203 disposed on the first substrate 11 and located in the peripheral region Q12; the compensation signal line 203 and the detection signal line 204 are sequentially disposed on the side of the first common electrode line 20 away from the dimming area Q11. The detection signal line 204 is electrically connected to a first gate line 201 closest to the bonding region, and is used for detecting a gate signal. The compensation signal line 203 is used for compensating the signal inputted by the dimming unit 01.

For example: a first gate insulating layer 12 is formed on the first metal conductive layer 2 to insulate the active semiconductor layer 3 formed later. Fig. 14 is a schematic view of an active semiconductor layer in a display module according to an embodiment of the disclosure; as shown in fig. 14, the active semiconductor layer 3 includes an active layer 301 of each of the first thin film transistors T1, and an orthographic projection of the active layer 301 of each of the first thin film transistors T1 on the first substrate 11 at least partially overlaps with an orthographic projection of the gate electrode 202 thereof on the first substrate 11 to realize a switching characteristic of the first thin film transistor T1. In addition, the active semiconductor layer can be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like.

For example: fig. 15 is a schematic view of a second metal conductive layer in a display module according to an embodiment of the disclosure; as shown in fig. 15, the second metal conductive layer 4 is formed on the active semiconductor layer 3, the second metal conductive layer 4 includes the source electrode 402 and the drain electrode 403 of each first thin film transistor T1, and the source electrode 402 and the drain electrode 403 of each first thin film transistor T1 overlap with an orthographic projection of its active layer on the first substrate 11, so that electrical connection between the source electrode 402 and the drain electrode 403 of each first thin film transistor T1 and its active layer 301 is achieved. The second metal conductive layer 4 further includes a plurality of first data lines 401 arranged side by side along the row direction X, each of the plurality of first data lines 401 extends along the column direction Y, the first data lines 401 and the second openings 012 on the first common electrode 010 are arranged in a one-to-one correspondence manner, and an orthographic projection of each first data line 401 on the first substrate 11 falls within an orthographic projection of the second opening 012 on the first common electrode 010 on the first substrate corresponding thereto. The second metal conductive layer 4 further comprises a plurality of first common voltage lead-in wires 406 arranged side by side in the row direction X, each first common voltage lead-in wire 406 extending in the column direction Y. The first common voltage introduction line 406 may be connected to the first common electrode line 20 through a third connection electrode formed later. Of course, each first common voltage lead-in 406 is also connected to the first common electrode 020 formed subsequently and located in the same column. In one example, the first data lines 401 and the first common voltage lead-in lines 406 in the second metal conductive layer 4 are alternately arranged along the row direction X, so that the wiring on the display substrate is more uniform, which helps to improve the uniformity of the light output of the light control panel 100.

With reference to fig. 15, gate signal introducing lines 404 located in the peripheral area Q12 are further disposed on the second metal conductive layer 4, one gate signal introducing line 404 is connected to one first gate line 201, and each gate signal introducing line 404 is further electrically connected to a gate driving circuit. Specifically, the end of the gate signal introduction line 404 is connected with the third connection portion 405, the third connection portion 405 and the gate signal introduction line 404 may be an integrally formed structure, and the third connection portion 405 and the second connection portion 205 are electrically connected to electrically connect the gate signal introduction line 404 and the first gate line 201.

In addition, as shown in fig. 15, all of the first dimming cell groups 10a in the peripheral region Q12 are redundant dimming cells, and the first gate lines 301 (e.g., the first gate line 301 shown in fig. 13) in the region that are connected to the redundant dimming cells in the first dimming cell group 10a are connected to the first common electrode line 20. The reason why the first gate line 301 is connected to the first common electrode line 20 is that the redundant dimming unit does not need to operate when the display module is displaying normally.

For example: a first interlayer insulating layer 13 is formed on the second metal conductive layer 4 to insulate the second metal conductive layer 4 from a second transparent conductive layer 5 to be formed later. FIG. 16 is a schematic view illustrating a via hole distribution in an interlayer insulating layer in a display module according to an embodiment of the disclosure; as shown in fig. 16, after the first interlayer insulating layer 13 is formed, the first gate insulating layer 12 and the first interlayer insulating layer 13 are etched to form a first connection via 131, a second connection via 132, and a fourth connection via 134, and to form a third connection via 133 and a fifth connection via 135 penetrating the first interlayer insulating layer, wherein the first connection via 131 and the third connection via 133 are used to electrically connect the dimming electrode 010 with the drain electrode 403 of the first thin film transistor T1 by the first connection electrode 14 formed later; the second connecting via is used to electrically connect the first common electrode 020 and the first common electrode line 20, which are formed later. The fourth and fifth connection vias 134 and 135 serve to electrically connect the second connection portion 205 and the third connection portion 405 through a subsequently formed second connection electrode to electrically connect the first gate line 201 and the gate signal introduction line 401.

With continued reference to fig. 16, since the width of the two portions of the first common electrode line 20 disposed oppositely in the row direction X is greater than the width of the two portions disposed oppositely in the column direction Y, the second connecting vias 132 of the two portions of the first common electrode line 20 disposed oppositely in the row direction X may be arranged in an array to reliably connect the first common electrode 020 and the first common electrode line 20 formed subsequently.

In addition, at this time, the first substrate further includes a sixth connection via 136 penetrating the first gate insulating layer 12 and the first interlayer insulating layer 13 and a seventh connection via 137 penetrating the first interlayer insulating layer 13, and the sixth connection via 136 and the seventh connection via 137 are used to electrically connect the first common electrode line 20 and the first common voltage lead-in line 406 (i.e., a position corresponding to the protrusion 310 in fig. 10) through a third connection electrode formed in the second transparent conductive layer later.

For example: fig. 17 is a schematic view of a second transparent conductive layer in a display module according to an embodiment of the disclosure, as shown in fig. 17, the second transparent conductive layer 5 is formed on the interlayer insulating layer 13, the second transparent conductive layer 5 includes first common electrodes 020, first connection electrodes 14, and second connection electrodes 502 of each dimming cell 01 and each redundant dimming cell; a plurality of third openings 501 arranged side by side in the column direction Y are formed on the first common electrode 020, and each third opening 501 extends in the row direction X. The third opening 501 is disposed corresponding to the first gate line 201, and an orthographic projection of the first gate line 201 on the first substrate 11 falls within an orthographic projection of the third opening 501 on the first substrate 11, so as to prevent the first gate line 201 and the first common electrode 020 from forming a coupling capacitor.

Referring to fig. 4, the first connection electrode 14 electrically connects the dimming electrode 010 with the drain electrode 403 of the first thin film transistor T1 through the first and third connection vias 131 and 133. Fig. 18 is a schematic connection diagram of the first common electrode and the first common electrode line in the display module according to the embodiment of the disclosure, and as shown in fig. 18, the first common electrode 020 is electrically connected to the first common electrode line 20 through the second connection via 132. Generally, the width of the second connection portion 205 is greater than that of the first gate line 201, a plurality of fourth connection vias 134 and fifth connection vias 135 may be provided at the position of each second connection portion 205, and a plurality of fourth connection vias 134 and fifth connection vias 135 may be arranged in an array, so as to achieve reliable connection between the gate signal lead-in line 404 and the second connection portion 205. Fig. 19 is a schematic connection diagram of the second connection portion and the third connection portion in the display module according to the embodiment of the disclosure, and as shown in fig. 19, the second connection electrode 502 electrically connects the second connection portion 205 and the third connection portion 405 through the fourth connection via 134 and the fifth connection via 135 to electrically connect the first gate line 201 and the gate signal lead-in line 401. Of course, a third connection electrode is further included in the second transparent conductive layer 5, and electrically connects the first common electrode line 20 and the first common voltage introduction line 406 through the sixth connection via 136 and the seventh connection via 137.

It should be noted that, the orthographic projection of the first common electrode 020 on the first substrate 11 in the second transparent conductive layer 5 covers the orthographic projection of the first data line 401 on the first substrate 11, and since the voltage input by the first common electrode 020 in operation is a constant voltage, the shielding electrode which covers the first data line 401 is equivalent to the shielding electrode of the first data line 401, so that the problem of light leakage caused by ineffective deflection of the liquid crystal molecules at the position of the first data line 401 can be effectively avoided.

Thus, the introduction of each film layer on the first substrate is completed.

For the first substrate, a first black matrix layer BM1 corresponding to the first substrate is provided; in the first substrate, the first common electrode 020 in the second transparent conductive layer 5 is equivalent to the shielding electrode of the first data line 401, so that the shielding portion is not provided at the position of the first data line 401 for blocking light. FIG. 20 is a schematic view of another first black matrix layer of a light control panel in a display module according to an embodiment of the disclosure; as shown in fig. 20, the first black matrix layer BM1 includes a first light-shielding portion BM11 located in the dimming region Q11 and a second light-shielding portion BM12 located in the peripheral region Q12; the first light shielding portion BM11 includes a plurality of sub-light shielding portions BM111 arranged side by side in the column direction Y, each sub-light shielding portion BM111 extending in the row direction X; and an orthographic projection of one sub-light-shielding portion BM111 on the first substrate 11 covers an orthographic projection of one first gate line 301 on the first substrate 11, and is used for blocking light to a position corresponding to the first gate line 201. In one example, if the first gate line 201 is in a zigzag shape, for example: jagged, S-shaped wavy, etc., and the sub-light shielding portions also have the same shape. The second light-shielding portion BM112 of the peripheral region Q12 with respect to the first black matrix layer BM1 is provided thereon with an annular slit 300, and the other positions of the second light-shielding portion BM12 are not transparent except for the position of the slit 300.

In a second aspect, an embodiment of the present disclosure provides a display device, including the above display module. Of course, a backlight or the like may be included.

It should be noted that, the display device provided in this embodiment may be: any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should be taken as limitations of the present invention.

It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A display module comprises a display panel and a light control panel which are arranged in a laminated manner; the light control panel is provided with a light adjusting area and a peripheral area surrounding the light adjusting area; the light control panel includes: the liquid crystal display panel comprises a first substrate, a second substrate and a first liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the first liquid crystal layer is arranged between the first substrate and the second substrate; it is characterized in that the preparation method is characterized in that,

the first substrate includes:

a first substrate having a first surface and a second surface,

the second substrate includes:

a second substrate, which is a substrate,

2. The display module of claim 1, wherein the slot comprises a continuous pattern surrounding the dimming area.

3. The display module of claim 2, wherein the number of the slots is at least one, the signal transmission line is disposed around the dimming area,

wherein d1, d2, kd3, d4, k is more than 0.8 and less than 1.2.

4. The display module of claim 3, wherein d1: d2 is in a range of 4:1 to 6: 1.

5. The display module of claim 1, wherein the first substrate further comprises signal connection lines disposed on the first substrate; the signal connecting line comprises a first sub-signal line and a second sub-signal line which are electrically connected and are positioned at different layers; the connection position of the first sub signal line and the second sub signal line is positioned in the peripheral area; the slot is formed with a protrusion at a connection position corresponding to the first sub-signal line and the second sub-signal line, so that the slot and an orthographic projection of the connection position of the first sub-signal line and the second sub-signal line on the first substrate do not overlap.

6. The display module according to claim 5, wherein the first sub-signal line comprises a first common electrode line, and the second sub-signal line comprises a first common voltage lead-in line; one end of the first public voltage lead-in wire is connected with the first public electrode wire, and the other end of the first public voltage lead-in wire is connected with the first public electrode;

7. The display module of claim 1, wherein the signal transmission line comprises a first common electrode line.

8. The display module of claim 7, wherein the first substrate further comprises:

9. The display module of claim 8, wherein an orthographic projection of the slot on the first substrate overlaps an orthographic projection of the redundant dimming cell on the first substrate.

10. The display module according to claim 8, wherein the plurality of dimming cells and the plurality of redundant dimming cells are arranged side by side along a second direction to form a plurality of first dimming cell groups, the dimming cell and the redundant dimming cell in each of the plurality of first dimming cell groups being arranged along a first direction; the plurality of dimming cells and the plurality of redundant dimming cells are arranged side by side along a first direction to form a plurality of second dimming cell groups, and the dimming cells and the redundant dimming cells in each of the plurality of second dimming cell groups are arranged along a second direction; the gates of the first thin film transistors of the dimming units and the redundant dimming units in the same first dimming unit group are connected with the same first grid line; each dimming unit and the redundant dimming unit in the same second dimming unit group are provided with data voltages through two first data lines, and the source electrodes of the adjacent first thin film transistors are connected with different first data lines;

the first substrate further includes:

11. The display module according to claim 10, wherein the first black matrix layer comprises a first light shielding portion located in the dimming area and a second light shielding portion located in the peripheral area;

12. The display module of claim 10, wherein the dimming electrode further comprises: a plurality of second opening portions arranged side by side in the first direction, each of the plurality of second opening portions extending in the second direction; and the orthographic projection of the first data line on the first substrate is in the orthographic projection of the second opening part on the first substrate.

13. The display module according to claim 10, wherein the second transparent conductive layer further comprises a plurality of third openings formed on the first common electrode and arranged side by side in the second direction; each of the plurality of third openings extends along a first direction, one third opening is arranged corresponding to one first grid line, and orthographic projections of the third openings and the first grid line are at least partially overlapped.

14. The display module according to claim 10, wherein the first transparent conductive layer further comprises a plurality of first connecting portions disposed at intervals, and the first connecting portions are electrically connected to the dimming electrodes in the redundant dimming units and directly connected to the first common electrode lines.

15. The display module according to claim 10, wherein the first substrate further comprises a gate driving circuit disposed on the first substrate and located in the peripheral region, and a plurality of gate signal introducing lines, detection signal lines, and compensation signal lines connected to the gate driving circuit; one of the gate signal lead-in lines is connected to one of the first gate lines; the detection signal line is connected with one first grid line;

16. The display module according to claim 15, wherein a second connection part is connected to an end of the first gate line, and a third connection part is connected to an end of the gate signal introduction line; the second transparent conductive layer further comprises a second connection electrode; the first substrate further comprises a fourth connecting via hole penetrating through the first gate insulating layer and the first interlayer insulating layer, and a fifth connecting via hole penetrating through the first interlayer insulating layer; the second connection electrode electrically connects the second connection portion and the third connection portion through the fourth connection via hole and the fifth connection via hole.

17. The display module according to claim 10, wherein the first metal conductive layer further comprises a redundancy gate line extending in a first direction, and the redundancy gate line is connected to the first common electrode line; at least one of the first dimming cell groups only includes the redundant dimming cell, and the gate of the first thin film transistor in the first dimming cell group is connected to the redundant gate line.

18. The display module of any of claims 1-17, wherein the width of the slot is greater than or equal to 18 μ ι η.

19. The display module according to any one of claims 1-17, wherein the display panel comprises a third substrate and a fourth substrate disposed opposite to each other, and a second liquid crystal layer disposed between the third substrate and the fourth substrate; the third substrate is positioned on one side of the second substrate, which is far away from the first liquid crystal layer; the display panel is provided with a display area and a non-display area surrounding the display area;

20. A display device comprising the display module of any one of claims 1-19.