CN214506881U - Peak current control circuit of buck-boost converter - Google Patents
Peak current control circuit of buck-boost converter Download PDFInfo
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- CN214506881U CN214506881U CN202022911010.4U CN202022911010U CN214506881U CN 214506881 U CN214506881 U CN 214506881U CN 202022911010 U CN202022911010 U CN 202022911010U CN 214506881 U CN214506881 U CN 214506881U
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Abstract
A buck-boost converter peak current control circuit comprising: the boost-buck conversion unit is used for providing voltage for a load; the peak current processing unit is connected to the buck-boost conversion unit and comprises a clock circuit; the trigger unit is respectively connected with the buck-boost conversion unit and the peak current processing unit, and the trigger unit controls the buck-boost conversion unit according to the output result of the peak current processing unit. The utility model discloses a four switches step-down converter peak current control circuit realizes step-down mode, step-down mode and the level and smooth switching between the mode that steps up, can not arouse inductive current and output voltage's big fluctuation, and four switches can not be simultaneously at the switch when step-down or step-up mode of step-down converter simultaneously, can improve the conversion efficiency of converter.
Description
Technical Field
The utility model relates to a boost-buck converter control circuit field, more specifically the saying so relates to a boost-buck converter peak current control circuit.
Background
The four-switch buck-boost converter can work in buck, buck-boost and boost modes, and can keep output stable when the input voltage is greater than, close to and less than the output voltage.
The existing buck-boost converter is relatively complex in switching control among three modes, and sudden switching among the modes causes sudden change of inductive current, so that output voltage is abnormal; or when the buck-boost converter is in the buck mode or the boost mode, the loss of the four switches is still increased at the same time, so that the conversion efficiency of the converter is reduced.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a buck-boost converter peak current control circuit.
The utility model discloses it is the problem of current step-up and step-down converter to solve.
Compared with the prior art, the utility model discloses technical scheme and beneficial effect as follows:
a buck-boost converter peak current control circuit comprising: the boost-buck conversion unit is used for providing voltage for a load; the peak current processing unit is connected to the buck-boost conversion unit and comprises a clock circuit; the trigger unit is respectively connected with the buck-boost conversion unit and the peak current processing unit, and the trigger unit controls the buck-boost conversion unit according to the output result of the peak current processing unit.
As a further improvement, the buck-boost conversion unit comprises: the drain electrode of the first switch tube is connected to the first voltage input end, and the first switch tube is an enhanced NMOS tube; the drain electrode of the second switch tube is connected to the source electrode of the first switch tube, the source electrode of the second switch tube is grounded, and the second switch tube is an enhanced NMOS tube; the source electrode of the third switching tube is grounded, and the third switching tube is an enhanced NMOS tube; a drain electrode of the fourth switching tube is connected to the voltage output end, a source electrode of the fourth switching tube is connected to the drain electrode of the third switching tube, and the fourth switching tube is an enhanced NMOS tube; and one end of the inductor is connected between the source electrode of the first switching tube and the drain electrode of the second switching tube, and the other end of the inductor is connected between the drain electrode of the third switching tube and the source electrode of the fourth switching tube.
As a further improvement, the buck-boost conversion unit further comprises: a first end of the first capacitor is connected to the first voltage input end, and a second end of the first capacitor is grounded; a first end of the second capacitor is connected to the voltage output end, and a second end of the second capacitor is grounded; and one end of the load resistor is connected to the voltage output end, and the other end of the load resistor is grounded.
As a further improvement, the peak current processing unit includes: the input end of the current sampling circuit is connected to the first voltage input end; the input end of the ramp compensation circuit is connected to the first output end of the clock circuit; a summer having a first input connected to the output of the current sampling circuit and a second input connected to the output of the ramp compensation circuit; the input end of the first processing circuit is connected to the voltage output end; and the second processing circuit is connected to the output end of the summator and the output end of the first processing circuit, and the output end of the second processing circuit is connected to the trigger unit.
As a further refinement, the first processing circuit comprises: a first voltage dividing resistor, a first end of the first voltage dividing resistor being connected to the voltage output end; a first end of the second voltage-dividing resistor is connected to an output end of the first voltage-dividing resistor, and a second end of the second voltage-dividing resistor is grounded; the non-inverting input end of the operational amplifier is connected between the second end of the first voltage-dividing resistor and the first end of the second voltage-dividing resistor, and the inverting input end of the operational amplifier is connected to a reference voltage; and the input end of the bias voltage circuit is connected to the output end of the operational amplifier.
As a further refinement, the second processing circuit comprises: a first comparator, wherein the non-inverting input end of the first comparator is connected to the output end of the summator, and the inverting input end of the first comparator is connected to the output end of the operational amplifier; a non-inverting input terminal of the second comparator is connected to the non-inverting input terminal of the first comparator, and an inverting input terminal of the second comparator is connected to the output terminal of the bias voltage circuit; a non-inverting input terminal of the third comparator is connected to the voltage output terminal, and an inverting input terminal of the third comparator is connected to the second voltage input terminal; a first input end of the first AND gate is connected to the grid electrode of the first switch tube, and a second input end of the first AND gate is connected to the output end of the first comparator; a first input end of the second AND gate is connected to the grid electrode of the third switching tube, and a second input end of the second AND gate is connected to the output end of the second comparator; and a first input end of the third AND gate is connected to the second output end of the clock circuit, and a second input end of the third AND gate is connected to the output end of the third comparator.
As a further improvement, the trigger unit includes: a first end of the first trigger is connected to the second output end of the clock circuit, a second end of the first trigger is connected to the output end of the first and gate, a third end of the first trigger is connected to the grid electrode of the first switch tube, and a fourth end of the first trigger is connected to the grid electrode of the second switch tube; a first end of the second trigger is connected to the output end of the second and gate, a second end of the second trigger is connected to the output end of the third and gate, and a third end of the second trigger is connected to the gate of the third switching tube; and the fourth end of the second trigger is connected to the grid electrode of the fourth switching tube.
As a further improvement, the voltage value of the second voltage input end is a times of that of the first voltage input end, and the value of a is 0.8-0.95.
As a further improvement, the first flip-flop and the second flip-flop are both set flip-flops.
The utility model has the advantages that: the utility model discloses a four switches step-down converter peak current control circuit realizes step-down mode, step-down mode and the level and smooth switching between the mode that steps up, can not arouse inductive current and output voltage's big fluctuation, and four switches can not be simultaneously at the switch when step-down or step-up mode of step-down converter simultaneously, can improve the conversion efficiency of converter.
Drawings
Fig. 1 is a circuit diagram of peak current control of a buck-boost converter according to an embodiment of the present invention.
Fig. 2 is a waveform diagram illustrating operation of a peak current control circuit of a buck-boost converter according to an embodiment of the present invention.
Fig. 3 is a method for controlling peak current of a buck-boost converter according to an embodiment of the present invention.
In the figure: 1. buck-boost conversion unit Q1. first switch tube Q2 second switch tube
Q3. third switch tube Q4 fourth switch tube 2 peak current processing unit
21. Current sampling circuit 22, ramp wave compensation circuit 23 and clock circuit
24. Summer 25, first processing circuit 251, bias voltage circuit
GM. operational amplifier R1, first divider resistor R2, second divider resistor
26. Second processing circuit comp1, first comparator comp2, second comparator
COMP3. third comparator U1. first AND gate U2. second AND gate U3. third AND gate
3. Trigger unit RS1, first trigger RS2, second trigger
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention will be combined to clearly and completely describe the technical solutions of the embodiments of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, a peak current control circuit of a buck-boost converter includes: the boost-buck conversion unit 1 is used for providing voltage for a load; a peak current processing unit 2, wherein the peak current processing unit 2 is connected to the buck-boost conversion unit 1; and the trigger unit 3 is respectively connected to the buck-boost conversion unit 1 and the peak current processing unit 2, and the trigger unit 3 controls the buck-boost conversion unit 1 according to an output result of the peak current processing unit 2. The utility model discloses a four switches step-down converter peak current control circuit realizes step-down mode, step-down mode and the level and smooth switching between the mode that steps up, can not arouse inductive current and output voltage's big fluctuation, and four switches can not be simultaneously at the switch when step-down or step-up mode of step-down converter simultaneously, can improve the conversion efficiency of converter.
Referring to fig. 1, the buck-boost converter unit 1 includes: a first switch tube Q1, a drain of the first switch tube Q1 is connected to a first voltage input end, and the first switch tube Q1 is an enhancement NMOS tube; a second switch tube Q2, a drain of the second switch tube Q2 is connected to the source of the first switch tube Q1, a source of the second switch tube Q2 is grounded, and the second switch tube Q2 is an enhancement NMOS tube; a third switching tube Q3, wherein the source of the third switching tube Q3 is grounded, and the third switching tube Q3 is an enhancement NMOS tube; a fourth switching tube Q4, a drain of the fourth switching tube Q4 is connected to the voltage output end, a source of the fourth switching tube Q4 is connected to a drain of the third switching tube Q3, and the fourth switching tube Q4 is an enhancement NMOS tube; one end of the inductor is connected between the source electrode of the first switching tube Q1 and the drain electrode of the second switching tube Q2, and the other end of the inductor is connected between the drain electrode of the third switching tube Q3 and the source electrode of the fourth switching tube Q4.
Referring to fig. 1, the buck-boost converter unit 1 further includes: a first end of the first capacitor is connected to the first voltage input end, and a second end of the first capacitor is grounded; a first end of the second capacitor is connected to the voltage output end, and a second end of the second capacitor is grounded; and one end of the load resistor is connected to the voltage output end, and the other end of the load resistor is grounded.
Referring to fig. 1, the peak current processing unit 2 includes: the input end of the current sampling circuit 21 is connected to the first voltage input end; a ramp compensation circuit 22; the input end of the ramp compensation circuit 22 is connected to the first output end of the clock circuit 23; a summer 24, a first input terminal of the summer 24 is connected to the output terminal of the current sampling circuit 21, and a second input terminal of the summer 24 is connected to the output terminal of the ramp compensation circuit 22; a first processing circuit 25, wherein an input terminal of the first processing circuit 25 is connected to the voltage output terminal; a second processing circuit 26, said second processing circuit 26 being connected to the output of said summer 24 and to the output of said first processing circuit 25, the output of said second processing circuit 26 being connected to said trigger unit 3.
Referring to fig. 1, the first processing circuit 25 includes: a first voltage dividing resistor R1, wherein a first end of the first voltage dividing resistor R1 is connected to the voltage output end; a second voltage-dividing resistor R2, a first end of the second voltage-dividing resistor R2 is connected to an output end of the first voltage-dividing resistor R1, and a second end of the second voltage-dividing resistor R2 is grounded; an operational amplifier GM having a non-inverting input connected between the second terminal of the first voltage-dividing resistor R1 and the first terminal of the second voltage-dividing resistor R2, and an inverting input connected to a reference voltage; an input terminal of the bias voltage circuit 251 is connected to an output terminal of the operational amplifier GM.
Referring to fig. 1, the second processing circuit 26 includes: a first comparator COMP1, a non-inverting input terminal of the first comparator COMP1 is connected to the output terminal of the summer 24, and an inverting input terminal of the first comparator COMP1 is connected to the output terminal of the operational amplifier GM; a second comparator COMP2, a non-inverting input terminal of the second comparator COMP2 is connected to a non-inverting input terminal of the first comparator COMP1, and an inverting input terminal of the second comparator COMP2 is connected to an output terminal of the bias voltage circuit 251; a third comparator COMP3, wherein a non-inverting input terminal of the third comparator COMP3 is connected to the voltage output terminal, and an inverting input terminal of the third comparator COMP3 is connected to a second voltage input terminal; a first and gate U1, a first input end of the first and gate U1 is connected to the gate of the first switching tube Q1, and a second input end of the first and gate U1 is connected to the output end of the first comparator COMP 1; a second and gate U2, a first input end of the second and gate U2 is connected to the gate of the third switching tube Q3, and a second input end of the second and gate U2 is connected to an output end of the second comparator COMP 2; a third and gate U3, a first input end of the third and gate U3 is connected to the second output end of the clock circuit 23, and a second input end of the third and gate U3 is connected to the output end of the third comparator COMP3.
Referring to fig. 1, the trigger unit 3 includes: a first flip-flop RS1, a first terminal of the first flip-flop RS1 being connected to the second output terminal of the clock circuit 23, a second terminal of the first flip-flop RS1 being connected to the output terminal of the first and gate U1, a third terminal of the first flip-flop RS1 being connected to the gate of the first switch transistor Q1, and a fourth terminal of the first flip-flop RS1 being connected to the gate of the second switch transistor Q2; a second flip-flop RS2, a first end of the second flip-flop RS2 is connected to the output end of the second and gate U2, a second end of the second flip-flop RS2 is connected to the output end of the third and gate U3, and a third end of the second flip-flop RS2 is connected to the gate of the third switching tube Q3; the fourth end of the second flip-flop RS2 is connected to the gate of the fourth switching transistor Q4.
Preferably, the voltage value of the second voltage input end is a times of that of the first voltage input end, and the value of a is 0.8-0.95. In this example, the value of a is 0.85. The value a is adjusted according to the actual application.
Referring to fig. 1, the first flip-flop RS1 and the second flip-flop RS2 are set flip-flops.
The utility model provides a pair of buck-boost converter peak current control circuit's theory of operation does:
1. the output voltage generates output feedback voltage through voltage dividing resistors R1 and R2, the output feedback voltage and reference voltage VREF generate Buck _ Vc voltage through an operational amplifier GM, and Buck _ Vc generates Boost _ Vc voltage through a bias voltage circuit; the clock signal generated by the clock circuit 23 generates a sawtooth-shaped ramp compensation voltage Slope through the ramp compensation circuit 22, the input current generates an Isen voltage through the current sampling circuit 21, and the Isen and Slope voltages are added to generate an Isen + Slope voltage; the Isen + Slope voltage and the Buck _ Vc voltage generate a Buck _ Rst signal through a comparator COMP1, and the Isen + Slope voltage and the Boost _ Vc voltage generate a Boost _ Rst signal through a comparator COMP 2; the phase of the Buck _ Rst signal and a driving signal Q1_ Gate of Q1 generates a reset signal Rst1, and the phase of the Boost _ Rst signal and a driving signal Q3_ Gate of Q3 generates a reset signal Rst 2; the output voltage VOUT and an input voltage VIN which is 0.85 times of the output voltage VOUT generate a Boost _ On signal through a comparator COMP3, and the Boost _ On signal and a Clock signal Clock phase are in phase-reversal to generate a Set signal Set 2; the Clock signal Clock and the reset signal Rst1 are respectively connected with S and R of the RS flip-flop RS1 to generate driving signals Q1_ Gate and Q2_ Gate of Q1 and Q2, and the Set signal Set2 and the reset signal Rst2 are respectively connected with S and R of the RS flip-flop RS1 to generate driving signals Q3_ Gate and Q4_ Gate of Q1 and Q2;
2. when the output voltage is less than 0.85 times of the input voltage, at this time, Boost _ On is a low level signal, Set2 is also low, the RS flip-flop RS2 outputs Q3_ Gate as a low level, and Q4_ Gate as a high level; when the Clock signal Clock arrives, the RS trigger RS1 is set, then Q1_ Gate is high level, Q2_ Gate is low level; when the Q1 and Q4 tubes are opened, the input current rises, the voltage Isen + Slope generated by adding the input current to the ramp wave through the current sampling circuit 21 also rises, when the voltage of Isen + Slope is larger than Buck _ Vc, the comparator COMP1 generates high-level Buck _ Rst, the reset signal enables Q1_ Gate to be low and Q2_ Gate to be high through the RS flip-flop RS 1; until the next clock comes to start a new cycle. At this time, the circuit operates in the Buck mode, and the waveforms of the points are shown in the Buck mode of fig. 2.
3. When the output voltage is greater than 0.85 times of the input voltage and the input voltage is closer to the output voltage, Boost _ On is a high level signal, when the Clock signal Clock comes, Set2 is high, the RS flip-flop RS2 outputs Q3_ Gate as high level, and Q4_ Gate as low level; meanwhile, the RS1 flip-flop is also set, so that the Q1_ Gate is at a high level, and the Q2_ Gate is at a low level; at the moment, the Q1 and the Q3 are opened, the input current rises, the voltage Isen + Slope generated by adding the input current with the ramp wave through the current sampling circuit 21 also rises, when the voltage of Isen + Slope is greater than Boost _ Vc, the comparator COMP2 generates high-level Boost _ Rst, and the reset signal enables Q3_ Gate to be changed into low and Q4_ Gate to be changed into high through the RS trigger RS 2; at the moment, the Q1 and the Q4 are opened, the voltage Isen + Slope generated by adding the input current to the Slope wave through the current sampling circuit 21 continues rising, when the voltage Isen + Slope is larger than Buck _ Vc, the comparator COMP1 generates high-level Buck _ Rst, and the reset signal enables Q1_ Gate to become low and Q2_ Gate to become high through the RS flip-flop RS 1; until the next clock comes to start a new cycle. At this time, the circuit works in a Buck-Boost mode, and the waveforms of all points are shown in a Buck-Boost mode of FIG. 2.
4. When the input voltage is less than the output voltage, the Boost _ On is a high level signal, when the Clock signal Clock comes, the Set2 is high, the RS flip-flop RS2 outputs Q3_ Gate as a high level, and Q4_ Gate as a low level; meanwhile, the RS1 flip-flop is also set, so that the Q1_ Gate is at a high level, and the Q2_ Gate is at a low level; at the moment, the Q1 and the Q3 are opened, the input current rises, the voltage Isen + Slope generated by adding the input current with the ramp wave through the current sampling circuit 21 also rises, when the voltage of Isen + Slope is greater than Boost _ Vc, the comparator COMP2 generates high-level Boost _ Rst, and the reset signal enables Q3_ Gate to be changed into low and Q4_ Gate to be changed into high through the RS trigger RS 2; at the moment, the Q1 and the Q4 are opened, the voltage Isen + Slope generated by adding the input current to the ramp wave through the current sampling circuit 21 continues rising until the voltage Isen + Slope is still less than Buck _ Vc when the clock signal arrives, the comparator COMP1 does not turn over, the Q1_ Gate is kept at a high level, and the Q2_ Gate is kept at a low level; a new cycle is started. At this time, the circuit operates in a Boost mode, and the waveforms of the points are shown in the Boost mode of fig. 2.
Referring to fig. 3, a method for controlling a peak current of a buck-boost converter includes:
s1, starting the cycle, determining whether the voltage output value of the third comparator COMP3 is greater than the second voltage input value; if the judgment result is yes, the first switching tube Q1 and the third switching tube Q3 are opened, the second switching tube Q2 and the fourth switching tube Q4 are closed until the second comparator COMP2 is turned over, and the operation goes to S2; if not, the process goes to S2;
s2, the first switch tube Q1 and the fourth switch tube Q4 are opened, and the second switch tube Q2 and the third switch tube Q3 are turned off;
s3, determining which of the first comparator COMP1 toggles and the clock circuit 23 signal comes first; if the first comparator COMP1 turns over first, the second switching tube Q2 and the fourth switching tube Q4 are opened, the first switching tube Q1 and the third switching tube Q3 are turned off, and then the process returns to S1; if the signal of the clock circuit 23 comes first, the process returns to S1.
The utility model provides a pair of buck-boost converter peak current control method's theory of operation does:
first, the cycle starts, and whether the output voltage is greater than 0.85 times of the input voltage is judged: if the output voltage is greater than 0.85 times the input voltage, Q1 and Q3 are turned on, Q2 and Q4 are turned off, until the comparator COMP2 flips to output a high level, Q1 and Q4 are turned on, and Q2 and Q3 are turned off; if the output voltage is less than 0.85 times of the input voltage, without waiting for the comparator COMP2 to flip, Q1 and Q4 are turned on, and Q2 and Q3 are turned off; then, if the comparator COMP1 flips to high before the Clock signal Clock comes, Q1 and Q3 turn off, Q2 and Q3 turn on, until a new Clock signal comes, and a new period starts; if the comparator COMP1 does not flip until the Clock signal Clock arrives, a new cycle starts directly.
The above examples are only for illustrating the technical solutions of the present invention and not for limiting the same. It will be understood by those skilled in the art that any modification and equivalent arrangement that do not depart from the spirit and scope of the invention should fall within the scope of the claims of the invention.
Claims (9)
1. A buck-boost converter peak current control circuit, comprising:
the boost-buck conversion unit is used for providing voltage for a load;
the peak current processing unit is connected to the buck-boost conversion unit and comprises a clock circuit;
the trigger unit is respectively connected with the buck-boost conversion unit and the peak current processing unit, and the trigger unit controls the buck-boost conversion unit according to the output result of the peak current processing unit.
2. The peak current control circuit of a buck-boost converter according to claim 1, wherein the buck-boost converter unit comprises:
the drain electrode of the first switch tube is connected to the first voltage input end, and the first switch tube is an enhanced NMOS tube;
the drain electrode of the second switch tube is connected to the source electrode of the first switch tube, the source electrode of the second switch tube is grounded, and the second switch tube is an enhanced NMOS tube;
the source electrode of the third switching tube is grounded, and the third switching tube is an enhanced NMOS tube;
a drain electrode of the fourth switching tube is connected to the voltage output end, a source electrode of the fourth switching tube is connected to the drain electrode of the third switching tube, and the fourth switching tube is an enhanced NMOS tube;
and one end of the inductor is connected between the source electrode of the first switching tube and the drain electrode of the second switching tube, and the other end of the inductor is connected between the drain electrode of the third switching tube and the source electrode of the fourth switching tube.
3. The peak current control circuit of a buck-boost converter according to claim 2, wherein the buck-boost converter unit further comprises:
a first end of the first capacitor is connected to the first voltage input end, and a second end of the first capacitor is grounded;
a first end of the second capacitor is connected to the voltage output end, and a second end of the second capacitor is grounded;
and one end of the load resistor is connected to the voltage output end, and the other end of the load resistor is grounded.
4. The peak current control circuit of claim 2, wherein the peak current processing unit comprises:
the input end of the current sampling circuit is connected to the first voltage input end;
the input end of the ramp compensation circuit is connected to the first output end of the clock circuit;
a summer having a first input connected to the output of the current sampling circuit and a second input connected to the output of the ramp compensation circuit;
the input end of the first processing circuit is connected to the voltage output end;
and the second processing circuit is connected to the output end of the summator and the output end of the first processing circuit, and the output end of the second processing circuit is connected to the trigger unit.
5. The buck-boost converter peak current control circuit according to claim 4, wherein the first processing circuit comprises:
a first voltage dividing resistor, a first end of the first voltage dividing resistor being connected to the voltage output end;
a first end of the second voltage-dividing resistor is connected to an output end of the first voltage-dividing resistor, and a second end of the second voltage-dividing resistor is grounded;
the non-inverting input end of the operational amplifier is connected between the second end of the first voltage-dividing resistor and the first end of the second voltage-dividing resistor, and the inverting input end of the operational amplifier is connected to a reference voltage;
and the input end of the bias voltage circuit is connected to the output end of the operational amplifier.
6. The buck-boost converter peak current control circuit according to claim 5, wherein the second processing circuit comprises:
a first comparator, wherein the non-inverting input end of the first comparator is connected to the output end of the summator, and the inverting input end of the first comparator is connected to the output end of the operational amplifier;
a non-inverting input terminal of the second comparator is connected to the non-inverting input terminal of the first comparator, and an inverting input terminal of the second comparator is connected to the output terminal of the bias voltage circuit;
a non-inverting input terminal of the third comparator is connected to the voltage output terminal, and an inverting input terminal of the third comparator is connected to the second voltage input terminal;
a first input end of the first AND gate is connected to the grid electrode of the first switch tube, and a second input end of the first AND gate is connected to the output end of the first comparator;
a first input end of the second AND gate is connected to the grid electrode of the third switching tube, and a second input end of the second AND gate is connected to the output end of the second comparator;
and a first input end of the third AND gate is connected to the second output end of the clock circuit, and a second input end of the third AND gate is connected to the output end of the third comparator.
7. The peak current control circuit of claim 6, wherein the trigger unit comprises:
a first end of the first trigger is connected to the second output end of the clock circuit, a second end of the first trigger is connected to the output end of the first and gate, a third end of the first trigger is connected to the grid electrode of the first switch tube, and a fourth end of the first trigger is connected to the grid electrode of the second switch tube;
a first end of the second trigger is connected to the output end of the second and gate, a second end of the second trigger is connected to the output end of the third and gate, and a third end of the second trigger is connected to the gate of the third switching tube; and the fourth end of the second trigger is connected to the grid electrode of the fourth switching tube.
8. The peak current control circuit of claim 6, wherein the voltage value of the second voltage input terminal is a times larger than that of the first voltage input terminal, and the value of a is 0.8-0.95.
9. The peak current control circuit of claim 7, wherein the first flip-flop and the second flip-flop are set flip-flops.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022911010.4U CN214506881U (en) | 2020-12-07 | 2020-12-07 | Peak current control circuit of buck-boost converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022911010.4U CN214506881U (en) | 2020-12-07 | 2020-12-07 | Peak current control circuit of buck-boost converter |
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| CN214506881U true CN214506881U (en) | 2021-10-26 |
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Effective date of registration: 20220401 Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: Unit 410, 1702 Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen City, Fujian Province Patentee before: INMICRO (XIAMEN) MICROELECTRONIC TECHNOLOGY CO.,LTD. |