CN214429467U

CN214429467U - Power supply circuit and power supply

Info

Publication number: CN214429467U
Application number: CN202120205044.3U
Authority: CN
Inventors: 沈逸伦
Original assignee: Agco Microelectronics Shenzhen Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2021-01-25
Filing date: 2021-01-25
Publication date: 2021-10-19
Anticipated expiration: 2031-01-25

Abstract

The utility model discloses a power supply circuit and power supply. The power supply circuit comprises a rectifying circuit, a charging circuit, a feedback circuit and a storage circuit. The rectifying circuit is used for receiving an input voltage to generate rectified electric energy. The charging circuit is coupled to the rectifying circuit and has a negative correlation modulation input end and a power supply electric energy end, wherein the negative correlation modulation input end is used for receiving a modulation voltage and selectively outputting a charging current at the power supply electric energy end according to the modulation voltage, and the charging current is in negative correlation with the modulation voltage. The feedback circuit is coupled to the negative correlation modulation input end, and is used for receiving the high-voltage signal and the supply voltage and outputting the modulation voltage to the negative correlation modulation input end, and the feedback circuit is used for adjusting the modulation voltage according to the difference value between the supply voltage and the reference voltage. The storage circuit is coupled to the power end of the power supply and is used for being charged by the charging current to pull up the supply voltage.

Description

Power supply circuit and power supply

Technical Field

The utility model relates to a power supply unit, especially a supply circuit and power supply.

Background

A power supply is a device that converts ac power into low-voltage stable dc power for use in the device. When the ac power is the commercial power, the ac voltage of the power supply is generally between 100V and 250V, and the supply voltage can be a stable dc voltage such as 21V, 12V, 5V, or 3.3V. In the related art, a transformer is used to step down a high-voltage ac of an ac voltage into a low-voltage ac, and then the low-voltage ac is converted into a dc voltage. The transformer is large in size, so that the size of the power supply cannot be reduced. In addition, when the range of the supply voltage becomes larger, the voltage resistance required by the transformer also increases, however, the size of the voltage resistance assembly is larger, and the size of the power supply is further increased, so that the power supply in the related art is inconvenient to use in portable equipment or other small-sized electric appliances.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a power supply circuit, including rectifier circuit, charging circuit, feedback circuit and storage circuit. The rectifying circuit is used for receiving an input voltage to generate rectified electric energy. The charging circuit is coupled to the rectifying circuit and has a negative correlation modulation input end and a power supply electric energy end, wherein the negative correlation modulation input end is used for receiving the modulation voltage and selectively outputting a charging current at the power supply electric energy end according to the modulation voltage, and the magnitude of the charging current is in negative correlation with the magnitude of the modulation voltage. The feedback circuit is coupled to the negative correlation modulation input end and used for receiving the high-voltage signal and the supply voltage and outputting the modulation voltage to the negative correlation modulation input end, and the feedback circuit adjusts the modulation voltage according to the difference value between the supply voltage and the reference voltage. The storage circuit is coupled to the power end of the power supply and is used for being charged by the charging current to pull up the voltage of the power end of the power supply. The supply voltage and the modulation voltage exhibit a positive correlation. The high voltage signal is positively correlated with the modulation voltage.

An embodiment of the utility model provides a power supply, including supply circuit, power switch and pulse width modulation signal generator. The power switch is used for selectively switching on or off to perform power conversion so as to regulate and control the supply voltage of the power supply. The PWM signal generator is used for providing a PWM signal to control the power switch, and is coupled to the power supply end of the power supply circuit and used for receiving electric energy from the power supply end to maintain the operation of the PWM signal generator.

Drawings

Fig. 1 is a schematic circuit diagram of a power supply circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of fixed power supply and adjustment of a power supply time window of the power supply circuit in fig. 1.

Fig. 3 is a schematic circuit diagram of another power supply circuit according to an embodiment of the present invention.

Fig. 4 is a signal waveform diagram of the power supply circuit of fig. 3.

Fig. 5 is a block diagram of a power supply according to an embodiment of the present invention.

Reference numerals:

1,3,50 power supply circuit

10 rectifier circuit

12 charging circuit

14,34 feedback circuit

140 control circuit

142,342 impedance path

340 analog-to-digital conversion circuit

5: power supply

52 pulse width modulation signal generator

54 power switch

Cin input capacitance

Cs storage circuit

D1, D2 diode

D3 clamping circuit

Ic charging current

N1 negative correlation modulation input

N2 power supply end

Q2 amplifier circuit

Q3 output circuit

Q1, R6 variable resistor

R1-R5 resistance

SPWM pulse width modulation signal

t 0-t 13 time

VAC input voltage

Vc1, Vc3 amplified Voltage

Vc2, Vc4 modulation voltage

VDD supply voltage

VDD _ Bottom lower limit Voltage

Upper limit voltage of VDD _ Top

VG control voltage

VG1 to VG3 waveforms of control voltages

VHV high voltage signal

VOUT (output voltage)

Vref-reference Voltage

VSS ground voltage

Detailed Description

Fig. 1 is a schematic circuit diagram of a power supply circuit 1 according to an embodiment of the present invention. The power supply circuit 1 can receive an input voltage VAC and provide a suitable supply voltage VDD according to the input voltage VAC. Specifically, the power supply circuit 1 may output a higher charging current Ic to increase the supply voltage VDD when the input voltage VAC is lower; when the input voltage VAC is higher, the charging circuit Cs outputs a lower charging current Ic or stops outputting the charging current Ic to slow down or stop charging, and the storage circuit Cs continuously releases the power to supply the supply voltage VDD, so as to maintain the supply voltage VDD within the operating range. In other words, the power supply circuit 1 can provide a substantially constant power, which can improve the operation efficiency and reduce the area of the power supply circuit 1. The input voltage VAC may be supplied by a commercial power or other ac voltage source, and may have a root mean square value of 100V to 240V and a peak value of 155V to 373V. When the power supply circuit 1 is applied to a Flyback power supply (Flyback Transformer), the input voltage VAC may be an auxiliary winding coil voltage of the Flyback power supply, and the auxiliary winding coil voltage and a secondary side supply voltage of the Flyback power supply have a Transformer winding turn ratio relationship, and the secondary side supply voltage of the Flyback power supply may vary from 3.3V to 27V. The supply voltage VDD may be a dc voltage and may be used as a power source of a Pulse Width Modulator (PWM) at a primary side of the flyback power supply, and the supply voltage VDD may be set to be higher than 8V.

The power supply circuit 1 may include an input capacitor Cin, a rectifying circuit 10, a charging circuit 12, a feedback circuit 14, and a storage circuit Cs. The input capacitor Cin may be coupled to the rectifying circuit 10, the rectifying circuit 10 may be coupled to the charging circuit 12, the charging circuit 12 may be coupled to the storage circuit Cs, the storage circuit Cs may be coupled to the feedback circuit 14, and the feedback circuit 14 may be coupled to the charging circuit 12.

The input capacitor Cin may receive the input voltage VAC and filter high-frequency noise in the input voltage VAC, and the rectifier circuit 10 may rectify the input voltage VAC after filtering the noise to generate rectified power. The voltage of the rectified electrical energy may be referred to as the rectified voltage. The input capacitor Cin includes a first terminal and a second terminal. The rectifier circuit 10 may include a diode D1 and a diode D2. The diode D1 includes a first terminal coupled to the first terminal of the input capacitor Cin; and a second end. The diode D2 includes a first terminal coupled to the second terminal of the input capacitor Cin; and a second terminal coupled to the second terminal of the diode D1.

The charging circuit 12 has a negative correlation modulation input terminal N1 and a power supply terminal N2, the negative correlation modulation input terminal N1 is for receiving a modulation voltage Vc2, and the power supply terminal N2 is for selectively outputting a charging current Ic according to the modulation voltage Vc 2. The magnitude of the charging current Ic is inversely related to the magnitude of the modulation voltage Vc 2. The storage circuit Cs can be charged by the charging current Ic to pull up the supply voltage VDD of the power terminal N2. The storage circuit Cs may include a storage capacitor having a first terminal coupled to the power terminal N2; and a second end coupled to the ground terminal. The ground terminal may provide a ground voltage VSS, e.g., 0V. The voltage VDD may be output to an external circuit for power supply. The feedback circuit 14 receives the high voltage signal VHV and the supply voltage VDD and outputs the modulation voltage Vc2 to the negative correlation modulation input terminal N1. The feedback circuit 14 adjusts the modulation voltage Vc2 according to the difference between the supply voltage VDD and the reference voltage Vref. When receiving the same high voltage signal VHV, the supply voltage VDD and the modulation voltage Vc2 exhibit positive correlation. The reference voltage Vref may be a predetermined voltage level, such as 12V. When the supply voltage VDD increases, the difference between the supply voltage VDD and the reference voltage Vref decreases, and the modulation voltage Vc2 increases; when the supply voltage VDD decreases, the difference between the supply voltage VDD and the reference voltage Vref increases, and the modulation voltage Vc2 decreases.

The charging circuit 12 includes an amplifying circuit Q2, a resistor R1, a resistor R2, a resistor R3, a clamp circuit D3, and an output circuit Q3. The resistor R1 includes a first terminal coupled to the second terminal of the diode D1 and the second terminal of the diode D2; and a second end. The resistor R2 includes a first terminal coupled to the second terminal of the resistor R1; and a second end. The amplifying circuit Q2 includes a control terminal; a first terminal coupled to a second terminal of the resistor R2; and a second end. The control terminal of the amplifying circuit Q2 may be the negative correlation modulation input terminal N1. The resistor R3 includes a first terminal coupled to the second terminal of the amplifying circuit Q2; and a second end coupled to the ground terminal. The clamping circuit D3 includes a first terminal coupled to the first terminal of the amplifying circuit Q2; and a second end coupled to the ground terminal. The output circuit Q3 comprises a control terminal coupled to a first terminal of the clamping circuit D3; a first terminal coupled to a second terminal of the resistor R1; and a second end. The second terminal of the output circuit Q3 may be a power supply power terminal N2. The amplifying circuit Q2 may be a first transistor, the output circuit Q3 may be a second transistor, and the first transistor and the second transistor may be N-type oxide semiconductor field-effect transistors (MOSFETs), NPN bipolar transistors (BJTs) or other types of transistors. In fig. 1, the amplifier circuit Q2 is NPNBJT, and the output circuit Q3 is an N-type MOSFET. The clamp circuit D3 may be a Zener diode (Zener diode). The resistor R1, the resistor R2, and the resistor R3 may be fixed resistors.

Feedback circuit 14 includes a control circuit 140 and an impedance path 142. The impedance path 142 is coupled to the charging circuit 12 and the control circuit 140. The control circuit 140 may be an operational amplifier, and includes a first input terminal for receiving a reference voltage Vref, a second input terminal for receiving a supply voltage VDD, and an output terminal for generating an amplified voltage Vc1 according to the reference voltage Vref and the supply voltage VDD. The impedance path 142 includes a resistor R4, a variable resistor Q1, and a resistor R5. The resistor R4 includes a first terminal coupled to the second terminal of the resistor R1; and a second end. The variable resistor Q1 includes a control terminal coupled to the output terminal of the control circuit 140; a first terminal coupled to a second terminal of the resistor R4; and a second end. The resistor R5 includes a first terminal coupled to the second terminal of the variable resistor Q1; and a second end coupled to the ground terminal. The variable resistor Q1 may be a third transistor, which may be an N-type MOSFET, NPN BJT, or other type of transistor. In fig. 1, the variable resistor Q1 may be an N-type MOSFET. The resistor R4 and the resistor R5 may be fixed resistors. When receiving the same supply voltage VDD, the high voltage signal VHV and the modulation voltage Vc2 exhibit positive correlation.

The amplifying circuit Q2 generates a first current according to the modulation voltage Vc2, the first current flows from the rectifying circuit 10 through the resistor R1, the resistor R2, the amplifying circuit Q2, the resistor R3 to the ground, and the control voltage VG is established at the second end of the resistor R2. The first current may be a collector current of the amplifying circuit Q2. The control voltage VG is negatively related to the high voltage signal VHV and the modulation voltage Vc 2. The resistor R1, the resistor R4, the variable resistor Q1, and the resistor R5 may be regarded as a voltage-dividing circuit. The modulation resistance of the variable resistor Q1 can be controlled by the amplified voltage Vc 1. When the same supply voltage VDD is received and the high voltage signal VHV increases, the modulation voltage Vc2 also increases, the amplifying circuit Q2 may be further turned on to generate an increased first current, which increases the voltage drop of the resistor R2 to decrease the control voltage VG; when the same supply voltage VDD is received and the high voltage signal VHV is decreased, the modulation voltage Vc2 is also decreased, the amplifying circuit Q2 is turned on to generate a decreased first current, and the decreased first current decreases the voltage drop of the resistor R2, so that the control voltage VG is increased. This makes the high voltage signal VHV and the control voltage VG have negative correlation, for example, when the high voltage signal VHV has an M-shaped waveform, the modulation voltage Vc2 also has an M-shaped waveform, and the control voltage VG has a W-shaped waveform. The clamp D3 limits the control voltage VG to the clamp voltage to protect the output Q3 from high voltage damage. The clamping voltage may be 30V.

The first terminal of the output circuit Q3 can receive the high voltage signal VHV, and the output circuit Q3 can adjust the charging current Ic flowing through the output circuit Q3 according to the control voltage VG. Specifically, the control terminal of the output circuit Q3 can receive the control voltage VG to selectively generate the charging current Ic. When the control voltage VG is greater than the threshold voltage of the output circuit Q3, the output circuit Q3 generates the charging current Ic, and the magnitude of the charging current Ic is in positive correlation with the difference between the control voltage VG and the threshold voltage; when the control voltage VG is less than the threshold voltage of the output circuit Q3, the output circuit Q3 stops generating the charging current Ic. The charging current Ic may be the drain current of the output circuit Q3. The charging current Ic can charge the storage circuit Cs to establish the supply voltage VDD. Therefore, the control voltage VG can control the charging capability of the output circuit Q3.

The feedback circuit 14 can adjust the power-taking time window of the power supply circuit 1 to control when the charging circuit 12 needs to take power. The control circuit 140 outputs the amplified voltage Vc1 according to the reference voltage Vref and the supply voltage VDD. The control terminal of the variable resistor Q1 receives the amplified voltage Vc1 to change the modulation resistance of the variable resistor Q1, thereby adjusting the modulation voltage Vc2 and the control voltage VG. The amplified voltage Vc1 is negatively correlated with the modulation resistance value. When the amplifying voltage Vc1 increases, the modulation resistance value decreases, and the modulation voltage Vc2 decreases and the control voltage VG increases; when the amplified voltage Vc1 falls, the modulation resistance value rises, the modulation voltage Vc2 rises, and the control voltage VG falls. When the supply voltage VDD is smaller than the reference voltage Vref and the control voltage VG rises until it is greater than the high-voltage signal VHV, the power-taking time window is opened, and the output circuit Q3 is turned on to charge the storage circuit Cs; when the supply voltage VDD is greater than the reference voltage Vref and the control voltage VG drops until it is less than the high-voltage signal VHV, the power-taking time window is closed, and the output circuit Q3 is turned off to stop charging the storage circuit Cs. When the control voltage VG is longer than the high-voltage signal VHV, the opening time of the power taking time window is longer; when the time that the control voltage VG is larger than the high-voltage signal VHV is shorter, the opening time of the power taking time window is shorter.

The power supply circuit 1 can output fixed power and adjust the power-taking time window, maintain the voltage VDD in the operation range, improve the operation efficiency and reduce the circuit area.

Fig. 2 is a schematic diagram of fixed power supply and adjustment of the power supply time window of the power supply circuit 1. VHV represents the waveform of the high voltage signal VHV, and VG1 to VG3 represent the waveforms of the control voltage VG corresponding to the 3 supply voltages VDD, respectively. The waveforms VG1 to VG3 are all inversely related to the waveform VHV, so that a substantially constant power is generated between the high-voltage signal VHV and the charging current Ic. The lower supply voltage VDD corresponds to waveform VG 1; the intermediate supply voltage VDD corresponds to waveform VG 2; the higher supply voltage VDD corresponds to waveform VG 3. When the supply voltage VDD increases, the feedback circuit 14 decreases the control voltage VG to shorten the power-taking time window and reduce the charging time of the storage circuit Cs; when the supply voltage VDD decreases, the feedback circuit 14 increases the control voltage VG to increase the power-taking time window and increase the charging time of the storage circuit Cs.

Fig. 3 is a schematic circuit diagram of another power supply circuit 3 according to an embodiment of the present invention. The difference between the supply circuit 3 and the supply circuit 1 is the feedback circuit 34. The following is explained with respect to the feedback circuit 34. Feedback circuit 34 includes an analog-to-digital converter 340 and an impedance path 342. The impedance path 342 may be coupled to the analog-to-digital converter 340. The adc 340 may be coupled to the storage circuit Cs, and may generate a representative value according to the supply voltage VDD, and quantize the representative value according to a predetermined signal range to convert the representative value into the digital signal Vc 3. The digital signal Vc3 may be a 3-bit digital signal. For example, the predetermined signal range may be 10V to 12V, and the analog-digital conversion circuit 340 may divide the predetermined signal range into 8 parts. When the representative value is greater than 12V, the analog-to-digital conversion circuit 182 may generate a maximum value 3b111 of the supply voltage signal Sc; when the representative value is less than 10V, the analog-to-digital conversion circuit 182 may generate a minimum value of 3b000 of the supply voltage signal Sc. The representative value may be an average value, a local minimum value, a local maximum value, or other supply voltage VDD at a specific time point of the supply voltage VDD in a corresponding time period of the previous power-taking time window. For example, the analog-to-digital converter 340 may further include a low-pass filter to generate an average value of the supply voltage VDD. In another example, the analog-to-digital converter 340 may further include a sampling circuit to generate a local minimum and a local maximum of the supply voltage VDD. In another example, the adc 340 may further include a sampling circuit, which samples the voltage VDD after the power-taking time window is opened or after a predetermined delay time elapses after the power-taking time window is closed to generate the supply voltage VDD at a specific time point. The predetermined delay time may be greater than or equal to 0. The impedance path 342 may include a resistor R4 and a variable resistor R6. The resistor R4 includes a first terminal coupled to the second terminal of the resistor R1; and a second end. The variable resistor R6 includes a control terminal coupled to the adc 340; a first terminal coupled to a second terminal of the resistor R4; and a second end coupled to the ground terminal. The control terminal of the variable resistor R6 can receive the digital signal Vc3 to provide a modulation resistance value, thereby generating the modulation voltage Vc 4. When the supply voltage VDD is low, the converted digital signal Vc3 causes the variable resistor R6 to have a low modulation resistance value, and causes the modulation voltage Vc4 to have a low voltage; when the supply voltage VDD is high, the converted digital signal Vc3 causes the variable resistor R6 to have a high modulation resistance value, and causes the modulation voltage Vc4 to have a high voltage, which is lower than the high voltage.

Compared with the analog implementation of the feedback circuit 14 in the power supply circuit 1, the digital implementation of the feedback circuit 34 in the power supply circuit 3 increases the stability of the power supply circuit 3, and also increases the operating efficiency and reduces the circuit area.

Fig. 4 is a signal waveform diagram of the power supply circuit 3, which includes 3 power-taking time windows respectively corresponding to three time periods when the control voltage VG is greater than the high-voltage signal VHV, the first power-taking time window is between time t1 and time t4, the second power-taking time window is between time t6 and time t8, and the third power-taking time window is between time t10 and time t 12. In 3 time windows of power taking, the charging circuit 12 charges the storage circuit Cs, and the supply voltage VDD substantially increases; outside the 3-get time window, the storage circuit Cs is discharged and the supply voltage VDD is lowered. The supply voltage VDD is maintained between an upper limit voltage VDD-Top and a lower limit voltage VDD-Bottom. For example, the upper limit voltage VDD-Top may be 12V and the lower limit voltage VDD-Bottom may be 10V. During the time period from t0 to t1, the time period from t4 to t6, and the time period from t8 to t10, the control voltage VG is smaller than the high-voltage signal VHV, the output circuit Q3 is turned off, the charging circuit 12 stops charging the storage circuit Cs, and the storage circuit Cs continues to discharge, so that the supply voltage VDD decreases.

Between time t1 and time t2, the control voltage VG is greater than the high voltage signal VHV, the output circuit Q3 is turned on, the charging circuit 12 charges the storage circuit Cs, the supply voltage VDD rises, and the first power-taking time window is opened. Between time t2 and time t3, the high voltage signal VHV continues to fall and is no longer higher than the supply voltage VDD maintained by the storage circuit Cs, and the high voltage signal VHV cannot continue to charge the storage circuit Cs, so the supply voltage VDD falls. Between time t3 and time t4, the high voltage signal VHV continues rising after crossing the valley bottom and is again higher than the supply voltage VDD maintained by the storage circuit Cs, the high voltage signal VHV resumes charging the storage circuit Cs, and the supply voltage VDD rises again. At time t4, the control voltage VG starts to be smaller than the high voltage signal VHV, the first power-taking time window is closed, and the supply voltage VDD reaches the peak value. Between time t4 and t6, the output circuit Q3 is turned off, and the charging circuit 12 stops charging the storage circuit Cs, so the supply voltage VDD decreases. After the predetermined delay time has elapsed at time t4, at time t5, the feedback circuit 34 generates the updated modulation voltage Vc4(1) corresponding to the representative value Vs (1) of the supply voltage VDD according to the previous period (e.g., time t0 to time t4), and the charging circuit 12 decreases the control voltage VG according to the updated modulation voltage Vc4(1) at time t 5.

Between time t6 and time t8, the control voltage VG is greater than the high-voltage signal VHV, the output circuit Q3 is turned on, the charging circuit 12 charges the storage circuit Cs, the supply voltage VDD rises, and the second power-taking time window is opened; however, as the high-voltage signal VHV continuously drops to the vicinity of the trough, the high-voltage signal VHV is no longer higher than the supply voltage VDD of the storage circuit Cs, so that the storage circuit Cs cannot be charged by the high-voltage signal VHV; therefore, the supply voltage VDD drops in a period near the valley of the high voltage signal VHV. At time t7, the high-voltage signal VHV continues rising after crossing the bottom of the valley and is again higher than the supply voltage VDD maintained by the storage circuit Cs, and the high-voltage signal VHV resumes charging the storage circuit Cs and the supply voltage VDD rises again. At time t8, the control voltage VG starts to be smaller than the high voltage signal VHV, the second power-taking time window is closed, and the supply voltage VDD reaches the peak value. Between time t8 and t10, the output circuit Q3 is turned off, and the charging circuit 12 stops charging the storage circuit Cs, so the supply voltage VDD decreases. After the predetermined delay time has elapsed at the time point t8, at the time point t9, the feedback circuit 34 generates the updated modulation voltage Vc4(2) again according to the representative value Vs (2) of the supply voltage VDD corresponding to the previous period (e.g., the time point t4 to the time point t8), and the charging circuit 12 decreases the control voltage VG according to the updated modulation voltage Vc4(2) at the time point t 9.

Between time t10 and time t12, the control voltage VG is greater than the high-voltage signal VHV, the output circuit Q3 is turned on, the charging circuit 12 charges the storage circuit Cs, the supply voltage VDD rises, and the third power-taking time window is opened; however, as the high-voltage signal VHV continuously drops to the vicinity of the trough, the high-voltage signal VHV is no longer higher than the supply voltage VDD of the storage circuit Cs, so that the storage circuit Cs cannot be charged by the high-voltage signal VHV; the supply voltage VDD drops corresponding to a period near the valley of the high voltage signal VHV. At time t11, the high-voltage signal VHV continues rising after crossing the bottom of the valley and is again higher than the supply voltage VDD maintained by the storage circuit Cs, and the high-voltage signal VHV resumes charging the storage circuit Cs and the supply voltage VDD rises again. At time t12, the control voltage VG starts to be smaller than the high voltage signal VHV, the third power-taking time window is closed, and the supply voltage VDD reaches the peak value. Before the time window from the time point t12 to the next time of getting power is opened, the output circuit Q3 is turned off, and the charging circuit 12 stops charging the storage circuit Cs, so the supply voltage VDD is decreased. After the predetermined delay time has elapsed at the time point t12, at the time point t13, the feedback circuit 34 generates the updated modulation voltage Vc4(3) again according to the representative value Vs (3) of the supply voltage VDD corresponding to the previous period (e.g., the time point t8 to the time point t12), and the charging circuit 12 increases the control voltage VG according to the updated modulation voltage Vc4(3) at the time point t 13.

Fig. 5 is a block diagram of a power supply 5 according to an embodiment of the present invention. The power supply 5 includes a power supply circuit 50, a pwm signal generator 52, and a power switch 54. The power supply circuit 50, which may be implemented by the power supply circuit 1 or the power supply circuit 3, provides the voltage VDD to the pwm signal generator 52, the pwm signal generator 52 provides the pwm signal SPWM to control the power switch 54, and the pwm signal generator 52 is coupled to the power supply terminal N2 of the power supply circuit and receives power from the power supply terminal N2 to maintain the pwm signal generator 52 operating. In response to the received pwm signal SPWM, the power switch 54 may be selectively turned on or off for power conversion, so as to change the on-frequency and duty cycle (duty cycle) of the power switch 54 according to the pwm signal SPWM, and further regulate the output voltage VOUT of the power supply 5.

The power supply 5 adopts the power supply circuit 1 or supplies power

The circuit 3 generates the voltage VDD, thereby improving the operation efficiency and reducing the circuit area.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the claims of the present invention should be covered by the present invention.

Claims

1. A power supply circuit, comprising:

a rectifying circuit for receiving an input voltage to generate a rectified electrical energy;

a charging circuit, coupled to the rectifying circuit, having a negative correlation modulation input terminal and a power supply power terminal, wherein the negative correlation modulation input terminal is used for receiving a modulation voltage and selectively outputting a charging current at the power supply power terminal according to the modulation voltage, and the magnitude of the charging current is negative correlation with the magnitude of the modulation voltage;

a feedback circuit, coupled to the negative correlation modulation input terminal, for receiving a high voltage signal and a supply voltage of the power supply power terminal, and outputting the modulation voltage to the negative correlation modulation input terminal; and

the storage circuit is coupled to the power supply end and used for being charged through the charging current to pull up the supply voltage;

wherein the feedback circuit adjusts the modulation voltage in a positive correlation manner according to the high voltage signal.

2. The power supply circuit of claim 1, wherein the charging circuit comprises:

the amplifying circuit is coupled to an impedance path and used for generating a first current according to the modulation voltage;

a first resistor coupled to the rectifying circuit;

a second resistor coupled to the first resistor, the impedance path and the amplifying circuit for establishing a control voltage according to the first current, wherein the control voltage is negatively related to the modulation voltage;

a third resistor coupled between the amplifying circuit and a ground terminal; and

and the output circuit is coupled to the second resistor and the amplifying circuit and used for adjusting a charging current flowing through the output circuit according to the control voltage.

3. The power supply circuit of claim 2, wherein the charging circuit further comprises: and the clamping circuit is coupled with the second resistor and the amplifying circuit and used for limiting the control voltage within a clamping voltage.

4. The power supply circuit of claim 2 wherein the amplifying circuit is a first transistor and the output circuit is a second transistor.

5. The power supply circuit of claim 1 wherein the feedback circuit adjusts the modulation voltage in a positive correlation with the supply voltage and adjusts the modulation voltage in a negative correlation with a difference between a reference voltage and the supply voltage.

6. The power supply circuit of claim 5 wherein said feedback circuit comprises:

a control circuit for outputting an amplified voltage according to the reference voltage and the supply voltage;

an impedance path coupled to the charging circuit to receive the rectified power, wherein the impedance path comprises:

a variable resistor having a first end coupled to the charging circuit, a second end coupled to a ground end, and a control end, for receiving the amplified voltage to provide a modulation resistance, wherein the amplified voltage and the modulation resistance are in negative correlation;

wherein when the amplified voltage increases, the modulation resistance value decreases to decrease the modulation voltage,

when the amplified voltage drops, the modulation resistance value rises to raise the modulation voltage.

7. The power supply circuit of claim 6 wherein the impedance path further comprises a fourth resistor and a fifth resistor, wherein the fourth resistor has a first end coupled to the charging circuit and a second end coupled to the variable resistor; the fifth resistor is coupled between the second end of the variable resistor and the ground terminal.

8. The power supply circuit of claim 6 wherein said control circuit is an operational amplifier including a first input for receiving said reference voltage; a second input terminal for receiving the supply voltage; and an output terminal for generating the amplified voltage.

9. The power supply circuit of claim 1 wherein the feedback circuit comprises:

an analog-to-digital converter, coupled to the storage circuit, for generating a representative value according to the supply voltage and converting the representative value into a digital signal;

an impedance path coupled to the charging circuit for receiving the high voltage signal, wherein the impedance path comprises:

a variable resistor having a first end, a second end and a control end coupled to the charging circuit for receiving the digital signal to provide a modulation resistance value; and

wherein, when the supply voltage is lower, the converted digital signal causes the variable resistor to have a lower modulation resistance value and causes the modulation voltage to have a lower voltage;

wherein when the supply voltage is higher, the converted digital signal causes the variable resistance to have a higher modulation resistance value and causes the modulation voltage to have a higher voltage, wherein the lower voltage is less than the higher voltage.

10. A power supply, comprising:

the power supply circuit of claim 1;

a power switch for selectively turning on or off to perform power conversion to regulate an output voltage of the power supply; and

the power supply circuit comprises a power supply circuit, a pulse width modulation signal generator and a control circuit, wherein the power supply circuit is used for supplying a power supply voltage to the power supply circuit, and the pulse width modulation signal generator is used for providing a pulse width modulation signal to control the power switch, and is coupled to the power supply end of the power supply circuit and used for receiving the supply voltage from the power supply end to maintain the operation of the pulse width modulation signal generator.