CN214410025U - Capacitor fingerprint chip and capacitor fingerprint detection equipment - Google Patents

Abstract

This specification discloses electric capacity fingerprint chip and electric capacity fingerprint check out test set, electric capacity fingerprint chip includes: the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal; the sensor array, the sampling circuit and the driving conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit; the sampling circuit is a fully differential mode sampling circuit and is used for reducing power supply common mode noise introduced by overlapping of transition edges of the level conversion clock signal and the excitation signal. The capacitance fingerprint chip and the capacitance fingerprint detection device provided by the specification can eliminate noise interference without influencing fingerprint image identification.

Description

Capacitor fingerprint chip and capacitor fingerprint detection equipment

Technical Field

This description relates to fingerprint sensor technical field, especially relates to a electric capacity fingerprint chip and electric capacity fingerprint check out test set.

Background

Fingerprint identification technology is the most mature technology in many current biometric identification technologies, the application of the technology is the most extensive, and the technology is the most common identity authentication mode. The capacitive fingerprint identification technology is the most mainstream identity identification technology at present, and compared with the ultrasonic fingerprint identification technology and the optical fingerprint identification technology, the capacitive fingerprint identification technology has the advantages of small volume, good image quality, high durability, low power consumption and the like. When fingerprint identification is carried out by using the capacitive fingerprint chip, a finger is firstly pressed on the surface of the sensor, and the surface of the finger and a metal layer on the top of the sensor respectively form two poles of an equivalent capacitor; at the moment, fingerprint valleys and ridges on the fingers form capacitance values with different sizes with the top metal layer of the sensor; the subsequent sensor can generate corresponding electric signals according to the capacitance values with different sizes and convert the electric signals into fingerprint images through the chip.

A capacitive fingerprint chip will typically include a sensor, a readout circuit and an analog-to-digital conversion circuit portion. When being applied to fingerprint detection of electronic equipment, the traditional capacitive fingerprint chip can be matched with a power driving chip to work in cooperation with the capacitive fingerprint chip. The capacitive fingerprint chip related to this time abandons the power driving chip, and the core processing chip of the electronic equipment is used for directly controlling the capacitive fingerprint chip to work, so that the manufacturing cost of the whole capacitive fingerprint detection system and the space occupied by the capacitive fingerprint detection system can be reduced.

When the size of the capacitive fingerprint chip is further reduced, for example, when the capacitive fingerprint chip is applied to the side of an electronic device, the shape of the capacitive fingerprint chip is designed to be a long strip shape when the capacitive fingerprint chip is used for detecting fingerprint information within an expected range, and the long edge extends along the side of the electronic device.

At present, the capacitance fingerprint chip integrated with the single chip with the capacitance fingerprint detection function is easy to be interfered by applied electronic equipment or the outside along with the reduction of the size, and further the fingerprint image detected by the capacitance fingerprint chip is interfered.

SUMMERY OF THE UTILITY MODEL

In view of the shortcomings of the prior art, it is an object of the present specification to provide a capacitive fingerprint chip and a capacitive fingerprint detection device, which can eliminate noise interference without affecting the recognition of fingerprint images.

To achieve the above object, an embodiment of the present disclosure provides a capacitive fingerprint chip, including:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

the sensor array, the sampling circuit and the driving conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

the sampling circuit is a fully differential mode sampling circuit and is used for reducing power supply common mode noise introduced by overlapping of transition edges of the level conversion clock signal and the excitation signal.

As a preferred embodiment, the sampling circuit of the fully differential mode comprises a first input terminal and a second input terminal; the first input and the second input are both connected to sensors in the sensor array.

As a preferred embodiment, the sensor array comprises a first sensor and a reference sensor, the reference sensor is arranged at the periphery or edge position of the first sensor; and the first input end or the second input end of the sampling circuit in the fully differential mode is connected with the reference sensor.

In a preferred embodiment, the first input and the second input of the fully differential mode sampling circuit are connected to two different sensors in the sensor array.

As a preferred embodiment, the analog-to-digital converter performs analog-to-digital conversion on the output signal of the sampling circuit in the fully differential mode.

An embodiment of the present specification provides a capacitive fingerprint chip, including:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

a second voltage domain, wherein a sensor array and a drive conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

the subtracting circuit is arranged in a second voltage domain and provided with a third input end and a fourth input end, the third input end and the fourth input end respectively receive two signals output by the sensor array, the subtracting circuit outputs difference signals of the third input end and the fourth input end, and the analog-to-digital converter performs analog-to-digital conversion on the difference signals; the subtraction circuit removes power supply common mode noise existing in the second voltage domain of the two signals output by the sensor array.

In a preferred embodiment, the two signals output by the sensor array are signals output by two different sensors of the sensor array at the same time.

As a preferred embodiment, the two different sensors of the sensor array are: a first sensor and a reference sensor; the reference sensor is disposed at a periphery of the first sensor.

In a preferred embodiment, the two signals output by the sensor array are two signals output by the same sensor of the sensor array at different times.

As a preferred embodiment, the second voltage domain further comprises a sampling circuit, which is arranged between the subtraction circuit and the analog-to-digital converter.

An embodiment of the present specification provides a capacitive fingerprint chip, including:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

the sensor array, the sampling circuit and the driving conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

and the high-pass filter is arranged in the first voltage domain or the second voltage domain and is used for filtering common-mode noise of the external power supply received by the first voltage domain.

In a preferred embodiment, a digital high-pass filter is disposed in the first voltage domain to filter out common-mode noise of the received external power supply.

In a preferred embodiment, an analog high-pass filter is disposed in the second voltage domain to filter out common mode noise of the floating power supply.

An embodiment of the present specification provides a capacitance fingerprint detection apparatus, including:

the capacitive fingerprint chip according to any one of the above embodiments, wherein the capacitive fingerprint chip is disposed on a side of an electronic device;

the device comprises a device core processing chip, a capacitor fingerprint chip and a power supply, wherein the capacitor fingerprint chip is electrically communicated with the device core processing chip through a conducting wire, and the device core processing chip provides an external power supply for the capacitor fingerprint chip;

the equipment power supply supplies power to the equipment core processing chip;

wherein the device core processing chip is closer to the device power supply than the capacitive fingerprint chip.

Has the advantages that:

the capacitive fingerprint chip provided by the embodiment of the specification can reduce power supply common mode noise caused by overlapping of transition edges of a level conversion clock signal and an excitation signal by arranging a fully differential mode sampling circuit, so that the identification of a fingerprint image is not influenced. And the first voltage domain and the second voltage domain are separated from the same chip based on the semiconductor technology, and the voltage domain where the sensor array is located is driven by the drive conversion circuit, so that the size of the chip can be reduced, and meanwhile, the sensitivity can be improved.

In another embodiment, by providing a subtraction circuit and processing the two signals output by the sensor array, the common mode noise of the power supply in the second voltage domain of the two signals output by the sensor array can be removed, so that the recognition of the fingerprint image is not affected.

In still another embodiment, a high-pass filter is arranged in the first voltage domain or the second voltage domain to filter frequencies generating common-mode noise interference, so that the common-mode noise interference of a power supply can be eliminated, and the identification of the fingerprint image is not affected.

Specific embodiments of the present specification are disclosed in detail with reference to the following description and the accompanying drawings, which specify the manner in which the principles of the specification may be employed. It should be understood that the embodiments of the present description are not so limited in scope.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.

It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Drawings

In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present specification, and other drawings can be obtained by those skilled in the art without inventive exercise.

Fig. 1 is a schematic structural diagram of a capacitive fingerprint chip and an apparatus core processing chip provided in this embodiment;

fig. 2 is a schematic diagram of an operation mode of a capacitive fingerprint chip according to this embodiment;

fig. 3 is a timing diagram of an activation signal and a level shift clock signal provided in this embodiment;

FIG. 4 is a timing diagram illustrating non-overlapping rising edges of an excitation signal and a level-shifted clock signal;

FIG. 5 is a timing diagram illustrating the overlap of rising edges of an excitation signal and a level-shifted clock signal;

fig. 6 is a schematic structural diagram of a fully differential mode sampling circuit provided in this embodiment;

fig. 7 is a schematic structural diagram of another capacitive fingerprint chip provided in this embodiment;

fig. 8 is a schematic structural diagram of another capacitive fingerprint chip provided in this embodiment;

fig. 9 is a schematic structural diagram of a subtraction circuit provided in an embodiment of the present disclosure;

fig. 10 is a schematic diagram of the arrangement of the high pass filter.

Description of reference numerals:

1. a capacitive fingerprint chip; 2. a device core processing chip; 3. a first voltage domain; 4. a second voltage domain; 5. an array of sensors; 51. a first sensor; 52. a reference sensor; 6. a sampling circuit; 61. a first input terminal; 62. a second input terminal; 63. a first output terminal; 64. a second output terminal; 7. a drive conversion circuit; 8. digital logic; 9. a subtraction circuit; 91. a third input terminal; 92. a fourth input terminal; 93. a third output terminal; 94. a fourth output terminal;

AVDD: a supply voltage; AVSS: a power ground; FVDD: a floating power supply voltage; FVSS: a floating power ground;

SCLK: a level shift clock signal; TX: an excitation signal;

PMU: a power management unit;

A/D: an analog-to-digital converter;

data Buffer: a data buffer;

SPI: a serial interface;

OSC: an oscillator;

VGA: a variable gain amplifier;

CF: a capacitor;

HOST: a host;

FIFO: a first-in first-out memory.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only a part of the embodiments of the present specification, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort shall fall within the protection scope of the present specification.

It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In some application scenarios, for example, when the capacitive fingerprint chip 1 is disposed on the side of a mobile phone, the chip is required to have a smaller volume and be in a narrow and long shape as a whole, and the chip is far away from a power supply, so that the power supply battery environment of the chip is complex, and the power supply has large noise, which causes common-mode noise interference between the power supply voltage of the capacitive fingerprint chip 1 and the power supply ground. Common mode noise of a power supply can generate interference on the fingerprint image under a certain working mode, so that the fingerprint image is abnormal. The interference of the power supply common mode noise can be improved by increasing the clock driving capability and enhancing the grounding, however, the interference cannot be eliminated in the prior art. Therefore, the embodiments of the present specification provide a capacitive fingerprint chip 1, which not only can reduce the chip volume, but also can eliminate the common mode noise interference of the power supply, thereby not affecting the fingerprint image recognition.

Please refer to fig. 1. The embodiment of the specification discloses a capacitance fingerprint chip 1 which can comprise a first voltage domain 3 and a second voltage domain 4. The chip can be divided into a first voltage domain 3 and a second voltage domain 4 by arranging an Isolation Trench (STI Isolation for short). Specifically, the first voltage domain 3 and the second voltage domain 4 are mainly physically isolated in the CMOS manufacturing process, so as to avoid mutual interference between different voltage domains.

The first voltage domain 3 is internally provided with a power management unit, an analog-to-digital converter, a serial interface and a digital logic unit. The first voltage domain 3 receives an external power supply and a level shift clock signal. The sensor array 5, the sampling circuit 6, and the drive conversion circuit 7 are provided in the second voltage domain 4. The second voltage domain 4 receives the excitation signal provided by the first voltage domain 3 and provides a floating ground power supply for the sensor array 5 through the drive switching circuit 7. The sampling circuit 6 is a fully differential mode sampling circuit 6 and is used for reducing power supply common mode noise caused by overlapping of transition edges of a level conversion clock signal and an excitation signal.

The capacitive fingerprint chip 1 provided in the embodiment of the present specification can reduce power supply common mode noise caused by overlapping of transition edges of a level conversion clock signal and an excitation signal by providing the sampling circuit 6 in a fully differential mode, so that the recognition of a fingerprint image is not affected. In addition, the first voltage domain 3 and the second voltage domain 4 are separated on the same chip based on the semiconductor technology, and the voltage domain where the sensor array 5 is located is driven by the driving conversion circuit 7, so that the size of the chip can be reduced, and the sensitivity can be improved.

In the present embodiment, the external power supply includes a power supply voltage AVDD and a power ground AVSS, and the floating power supply includes a floating power supply voltage FVDD and a floating power ground FVSS. The digital logic unit may comprise digital logic 8 and an Oscillator (OSC) for generating the clock required for the operation of the chip. The digital logic unit is used for generating sequential logic of the whole chip. The digital logic unit may generate the stimulus signal TX. Stimulus signal TX is one of the sequential logics. The drive conversion circuit 7 supplies the floating power supply voltage FVDD and the floating power supply FVSS to the sensor array 5 upon receiving the excitation signal supplied from the first voltage domain 3. The voltage of the floating ground FVSS is adjustable relative to the voltage of the power ground AVSS, and the sensitivity of the fingerprint identification by the capacitive fingerprint chip 1 is related to the two voltages, and the sensitivity can be adjusted by adjusting the two voltages.

In this embodiment, the Power Management Unit (PMU) is configured to control an on-chip operating Power supply and to generate a 1.8V supply voltage and a reference voltage. The Analog-to-Digital Converter (a/D) is used for Analog-to-Digital converting the output signal of the sampling circuit 6 in the fully differential mode. The analog-to-digital converter (A/D) may be in either a row analog-to-digital converter mode or a system analog-to-digital converter mode. The Serial Interface (SPI) is used for data communication between the capacitive fingerprint chip 1 and a HOST (HOST).

Specifically, the first voltage domain 3 may further be provided with a Data Buffer (Data Buffer) for buffering digital signals output by the analog-to-digital converter (a/D), that is, fingerprint Data, and the Data Buffer may be implemented by a Static Random Access Memory (SRAM) or a FIFO memory. The first voltage domain 3 may further include a Variable Gain Amplifier (VGA) between the sampling circuit 6 and the analog-to-digital converter (a/D), for amplifying the received output signal of the sampling circuit 6 and transmitting the amplified signal to the analog-to-digital converter (a/D).

Preferably, the data buffer is a FIFO memory. As shown in fig. 2, when the capacitive fingerprint chip 1 detects a fingerprint image, three actions of fingerprint image scanning, analog-to-digital conversion data storage and image data reading by a host are performed in parallel. That is, while the serial interface SPI transmits data, the driving conversion circuit 7 receives the excitation signal TX, and the sensor array 5 scans the fingerprint image information.

The digital logic unit controls the working state of the capacitance fingerprint chip 1, and the output excitation signal TX controls the driving conversion circuit 7 to generate a floating power supply voltage FVDD and a floating power supply voltage FVSS. The capacitor CF in fig. 1 is used to keep the voltage difference between the floating power supply voltage FVDD and the ground power supply ground FVSS approximately constant.

In the present embodiment, the sampling circuit 6 of the fully differential mode includes a first input terminal 61 and a second input terminal 62, as shown in fig. 6. The sampling circuit 6 further comprises a first output 63 and a second output 64, the first output 63 and the second output 64 being connectable to a Variable Gain Amplifier (VGA) for transferring the differential signal to the VGA. The first input 61 and the second input 62 are both connected to sensors in the sensor array 5. The sensor array 5 is designed in a multi-channel mode, and a plurality of channels are converted in parallel at the same time, that is, each sensor in the sensor array 5 is converted in parallel at the same time. The effect of the common mode noise interference of the power supply on each sensor is consistent and the interference can be eliminated by setting the sampling circuit 6 in fully differential mode.

Preferably, the sensor array 5 comprises a first sensor 51 and a reference sensor 52. The reference sensor 52 may be one or several, chosen according to design requirements. The reference sensor 52 is disposed at a peripheral or edge position of the first sensor 51. The reference sensor 52 may be connected to the first input 61 or the second input 62 of the fully differential mode sampling circuit 6. The reference sensor 52 differs from the first sensor 51 in that: the negative input of the reference sensor 52 is not connected to the finger equivalent capacitance, but rather to a reference capacitance. The capacitance value of the reference capacitor is a constant value, and thus the output value of the reference sensor 52 is also a constant value.

In this embodiment, the first input terminal 61 and the second input terminal 62 of the fully differential mode sampling circuit 6 are connected to two different sensors in the sensor array 5, which may be two different first sensors 51; one may be the first sensor 51 and the other may be the reference sensor 52.

When a finger is pressed on a chip, the first sensor 51 generates a corresponding electric signal according to the capacitance formed by the surface of the finger and the sensor, the electric signal is sampled by the fully differential mode sampling circuit 6 and is transmitted to a Variable Gain Amplifier (VGA) for amplification, finally, an analog-to-digital converter (A/D) is quantized and stored in a Static Random Access Memory (SRAM), and a serial interface (SPI) transmits data to a HOST (HOST) at a proper time. The driving signal TX outputted from the digital logic unit controls the driving switching circuit 7 to generate a floating power voltage FVDD and a floating power ground FVSS, and the off-chip capacitor CF is used to keep a voltage difference between the floating power voltage FVDD and the ground power ground FVSS approximately constant. The capacitor CF can keep the voltage at the two ends not to suddenly change, the voltage can be considered to be constant in a short time, the FVDD and the FVSS supply power to the sensor, and the difference between the FVDD and the FVSS is constant, so that power supply noise cannot be introduced into the sensor.

In the present embodiment, as shown in fig. 1, the capacitive fingerprint chip 1 may be connected to the device core processing chip 2 (see below) through a conductive wire. The device core processing chip 2 provides the first voltage domain 3 with a supply voltage AVDD, a supply ground AVSS and a level shifted clock signal SCLK. The level shift clock signal SCLK may be provided by SPI. Since the power and ground lines from the device core processing chip 2 to the capacitive fingerprint chip 1 have a certain length (for example, a length of several centimeters), and the conductive lines have strong parasitic effects (parasitic resistance and inductance), common mode noise may be generated on the power supply voltage AVDD and the power supply ground AVSS. In the process of SCLK level conversion, the power voltage AVDD and the power ground AVSS generate 2-frequency-doubled glitches, and the power voltage AVDD minus the power ground AVSS generates smaller glitches.

As shown in fig. 3, the clock frequency of the stimulus signal TX is much smaller than the clock frequency of the level-shifted clock signal SCLK. Most of the time period, the rising edge of SCLK does not overlap with the rising edge of TX, which is a small probability event. Only in the case where SCLK overlaps with the TX rising edge does the glitch of supply voltage AVDD minus supply ground AVSS interfere with the fingerprint image.

As shown in fig. 4, the rising edges of the excitation signal TX and the level shift clock signal SCLK are non-overlapping, and the supply voltage AVDD minus the power ground AVSS is stable for most of the time, without glitches, and without disturbing the fingerprint image. As shown in fig. 5, the rising edges of the excitation signal TX and the level shift clock signal SCLK overlap, which is a few cases where the fingerprint image is disturbed by the glitch of the supply voltage AVDD minus the supply ground AVSS.

The noise interference of supply voltage AVDD and supply ground AVSS is consistent with the glitch effect on the sensors on each channel of sensor array 5. By arranging the sampling circuit 6 in a fully differential mode, the consistent burrs are subtracted, so that the influence of the burrs on output signals is eliminated, namely the interference of power supply common mode noise on fingerprint images is eliminated.

As shown in fig. 7 to 9, the embodiment of the present specification further discloses a capacitive fingerprint chip 1, which may include a first voltage domain 3, a second voltage domain 4 and a subtraction circuit 9. The first voltage domain 3 is internally provided with a power management unit, an analog-to-digital converter, a serial interface and a digital logic unit. The first voltage domain 3 receives an external power supply and a level shift clock signal. The sensor array 5 and the drive conversion circuit 7 are provided in the second voltage domain 4. The second voltage domain 4 receives the excitation signal provided by the first voltage domain 3 and provides a floating ground power supply for the sensor array 5 through the drive switching circuit 7. The subtraction circuit 9 is located in the second voltage domain 4. The subtracting circuit 9 is provided with a third input 91 and a fourth input 92, the third input 91 and the fourth input 92 receiving two signals output by the sensor array 5, respectively. The subtraction circuit 9 outputs a difference signal of the third input terminal 91 and the fourth input terminal 92. The analog-to-digital converter performs analog-to-digital conversion on the difference signal. The subtraction circuit 9 removes the power supply common mode noise present in the second voltage domain 4 from the two signals output by the sensor array 5.

In the capacitive fingerprint chip 1 according to the present embodiment, the subtraction circuit 9 is provided to process the two signals output from the sensor array 5, so that the power supply common mode noise existing in the second voltage domain 4 of the two signals output from the sensor array 5 can be removed, and the fingerprint image recognition is not affected.

In the present embodiment, the two signals output by the sensor array 5 may be signals output by two different sensors of the sensor array 5 at the same time. Wherein, the two different sensors of the sensor array 5 may be: a first sensor 51 and a reference sensor 52. The reference sensor 52 is disposed at the periphery of the first sensor 51.

In another embodiment, the two signals output by the sensor array 5 may be two signals output by the same sensor of the sensor array 5 at different times.

As shown in fig. 8, in the present embodiment, the second voltage domain 4 may further include a sampling circuit 6. The sampling circuit 6 is disposed between the subtraction circuit 9 and the analog-to-digital converter.

As shown in fig. 9, the third input terminal 91 and the fourth input terminal 92 of the subtraction circuit 9 are respectively connected to the sensor array 5, and respectively receive two signals output by the sensor array 5. The subtracting circuit 9 further comprises a third output 93 and a fourth output 94, the third output 93 and the fourth output 94 may be connected to a Variable Gain Amplifier (VGA) for transferring the signal via the subtracting circuit 9 to the VGA.

The embodiment of the present specification also discloses a capacitive fingerprint chip 1, which may include a first voltage domain 3 and a second voltage domain 4. The first voltage domain 3 is internally provided with a power management unit, an analog-to-digital converter, a serial interface and a digital logic unit. The first voltage domain 3 receives an external power supply and a level shift clock signal. The sensor array 5, the sampling circuit 6, and the drive conversion circuit 7 are provided in the second voltage domain 4. The second voltage domain 4 receives the excitation signal provided by the first voltage domain 3 and provides a floating ground power supply for the sensor array 5 through the drive switching circuit 7. A high-pass filter is arranged in the first voltage domain 3 or the second voltage domain 4 and is used for filtering common-mode noise of the external power supply received by the first voltage domain 3.

In the capacitive fingerprint chip 1 provided by the embodiment, the high-pass filter is arranged in the first voltage domain 3 or the second voltage domain 4, so that the frequency generating the common-mode noise interference is filtered, the common-mode noise interference of a power supply can be eliminated, and the identification of a fingerprint image is not influenced.

As shown in fig. 10, when data of the first sensor 51 of 4 channels are read at a time, the spectrograms are analyzed and observed, and frequency points of common-mode noise interference are found to appear respectively: 1/4Fpix, 1/8Fpix, 1/12Fpix, … 1/4N Fpix. That is, the disturbance occurs every 4 pixels. Therefore, the frequency points which can generate interference are filtered, and the frequency of the image pixel points is reserved, so that the abnormal phenomenon of the fingerprint image caused by common-mode noise interference can be solved.

The high-pass filter has the functions of filtering low frequency and retaining high frequency. Either an analog high pass filter or a digital high pass filter may be selected. When the data of the first sensor 51 of 4 channels is read at a time, the pass band cutoff frequency and the stop band cutoff frequency of the high-pass filter are selected near Fpix and 1/4Fpix, respectively.

In one embodiment, a digital high-pass filter is disposed in the first voltage domain 3 to filter out common mode noise of the received external power supply. In another embodiment, an analog high-pass filter is disposed in the second voltage domain 4 to filter out common-mode noise of the floating power supply.

The embodiment of the present specification further discloses a capacitive fingerprint detection device, which may include a capacitive fingerprint chip 1, a device core processing chip 2, and a device power supply. The capacitive fingerprint chip 1 may be the capacitive fingerprint chip 1 in any of the above embodiments, which is not described herein again. The capacitance fingerprint chip 1 is arranged on the side of the electronic equipment. The capacitance fingerprint chip 1 is electrically communicated with the equipment core processing chip 2 through a conducting wire. The device core processing chip 2 provides an external power supply for the capacitance fingerprint chip 1. The device power supply supplies power to the device core processing chip 2. The device core processing chip 2 is closer to the device power supply than the capacitance fingerprint chip 1.

In the capacitance fingerprint detection device provided by this embodiment, because the device core processing chip 2 is closer to the device power supply than the capacitance fingerprint chip 1, that is, the capacitance fingerprint chip 1 is farther from the device power supply, the common mode noise of the power supply interferes with the fingerprint image in a certain working mode, so that the fingerprint image is abnormal. In the capacitive fingerprint chip 1 in the above embodiment of the present specification, the sampling circuit 6 in the fully differential mode, or the subtraction circuit 9, or the high-pass filter is provided, so that noise interference can be eliminated, and thus the fingerprint image recognition is not affected.

It should be noted that, in the description of the present specification, the terms "first", "second", and the like are used for descriptive purposes only and for distinguishing similar objects, and no order is present therebetween, and no indication or suggestion of relative importance is to be made. Further, in the description of the present specification, "a plurality" means two or more unless otherwise specified.

Any numerical value recited herein includes all values from the lower value to the upper value, in increments of one unit, provided that there is a separation of at least two units between any lower value and any higher value. For example, if it is stated that the number of a component or a value of a process variable (e.g., temperature, pressure, time, etc.) is from 1 to 90, preferably from 20 to 80, and more preferably from 30 to 70, it is intended that equivalents such as 15 to 85, 22 to 68, 43 to 51, 30 to 32 are also expressly enumerated in this specification. For values less than 1, one unit is suitably considered to be 0.0001, 0.001, 0.01, 0.1. These are only examples of what is intended to be explicitly recited, and all possible combinations of numerical values between the lowest value and the highest value that are explicitly recited in the specification in a similar manner are to be considered.

Unless otherwise indicated, all ranges include the endpoints and all numbers between the endpoints. The use of "about" or "approximately" with a range applies to both endpoints of the range. Thus, "about 20 to about 30" is intended to cover "about 20 to about 30", including at least the endpoints specified.

The term "consisting essentially of …" describing a combination shall include the identified element, ingredient, component or step as well as other elements, ingredients, components or steps that do not materially affect the basic novel characteristics of the combination. The use of the terms "comprising" or "including" to describe combinations of elements, components, or steps herein also contemplates embodiments that consist essentially of such elements, components, or steps. By using the term "may" herein, it is intended to indicate that any of the described attributes that "may" include are optional.

A plurality of elements, components, parts or steps can be provided by a single integrated element, component, part or step. Alternatively, a single integrated element, component, part or step may be divided into separate plural elements, components, parts or steps. The disclosure of "a" or "an" to describe an element, ingredient, component or step is not intended to foreclose other elements, ingredients, components or steps.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes.

Claims (14)

1. A capacitive fingerprint chip, comprising:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

the sensor array, the sampling circuit and the driving conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

the sampling circuit is a fully differential mode sampling circuit and is used for reducing power supply common mode noise introduced by overlapping of transition edges of the level conversion clock signal and the excitation signal.

2. The capacitive fingerprint chip of claim 1, wherein the fully differential mode sampling circuit comprises a first input and a second input; the first input and the second input are both connected to sensors in the sensor array.

3. The capacitive fingerprint chip of claim 2, wherein the sensor array comprises a first sensor and a reference sensor, the reference sensor being disposed at a periphery or edge location of the first sensor; and the first input end or the second input end of the sampling circuit in the fully differential mode is connected with the reference sensor.

4. The capacitive fingerprint chip of claim 2, wherein the first input and the second input of the fully differential mode sampling circuit are coupled to two different sensors in the sensor array.

5. The capacitive fingerprint chip of claim 2, wherein the analog-to-digital converter analog-to-digital converts the output signal of the fully differential mode sampling circuit.

6. A capacitive fingerprint chip, comprising:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

a second voltage domain, wherein a sensor array and a drive conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

the subtracting circuit is arranged in a second voltage domain and provided with a third input end and a fourth input end, the third input end and the fourth input end respectively receive two signals output by the sensor array, the subtracting circuit outputs difference signals of the third input end and the fourth input end, and the analog-to-digital converter performs analog-to-digital conversion on the difference signals; the subtraction circuit removes power supply common mode noise existing in the second voltage domain of the two signals output by the sensor array.

7. The capacitive fingerprint chip of claim 6, wherein the two signals output by the sensor array are signals output by two different sensors of the sensor array at the same time.

8. The capacitive fingerprint chip of claim 7, wherein the two different sensors of the sensor array are: a first sensor and a reference sensor; the reference sensor is disposed at a periphery of the first sensor.

9. The capacitive fingerprint chip of claim 6, wherein the two signals output by the sensor array are two signals output by the same sensor of the sensor array at different times.

10. The capacitive fingerprint chip of claim 6, wherein the second voltage domain further comprises a sampling circuit disposed between the subtraction circuit and the analog-to-digital converter.

11. A capacitive fingerprint chip, comprising:

the power supply comprises a first voltage domain, a second voltage domain and a third voltage domain, wherein a power supply management unit, an analog-to-digital converter, a serial interface and a digital logic unit are arranged in the first voltage domain, and the first voltage domain receives an external power supply and a level conversion clock signal;

the sensor array, the sampling circuit and the driving conversion circuit are arranged in the second voltage domain; the second voltage domain receives the excitation signal provided by the first voltage domain, and a floating ground power supply is provided for the sensor array through the drive conversion circuit;

and the high-pass filter is arranged in the first voltage domain or the second voltage domain and is used for filtering common-mode noise of the external power supply received by the first voltage domain.

12. The capacitive fingerprint chip of claim 11, wherein a digital high pass filter is disposed in the first voltage domain to filter out common mode noise of the received external power supply.

13. The capacitive fingerprint chip of claim 11, wherein an analog high pass filter is disposed in the second voltage domain to filter out common mode noise of the floating ground power supply.

14. A capacitive fingerprint sensing apparatus, comprising:

the capacitive fingerprint chip of any one of claims 1, 6, and 11, disposed on a side of an electronic device;

the device comprises a device core processing chip, a capacitor fingerprint chip and a power supply, wherein the capacitor fingerprint chip is electrically communicated with the device core processing chip through a conducting wire, and the device core processing chip provides an external power supply for the capacitor fingerprint chip;

the equipment power supply supplies power to the equipment core processing chip;

wherein the device core processing chip is closer to the device power supply than the capacitive fingerprint chip.

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