CN214380067U - Circuit capable of protecting USB power interface of host - Google Patents
Circuit capable of protecting USB power interface of host Download PDFInfo
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- CN214380067U CN214380067U CN202023056601.4U CN202023056601U CN214380067U CN 214380067 U CN214380067 U CN 214380067U CN 202023056601 U CN202023056601 U CN 202023056601U CN 214380067 U CN214380067 U CN 214380067U
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Abstract
The utility model relates to a circuit that can protect host computer USB power interface, including host computer treater, power supply protection circuit, EMI circuit, electrostatic protection device and USB connector. The circuit of the USB power interface provided by the disclosure can avoid the host from being damaged by power-on when the USB connector is plugged and pulled out, and improves the use reliability of the USB function of the product.
Description
Technical Field
The utility model relates to an electronic circuit technical field especially relates to a can protect circuit of host computer USB power interface.
Background
With the popularization of USB interfaces, USB technology has been widely applied to various digital products and electronic devices in various industries. Many application scenes environment is abominable, can have the condition that USB slave unit loses electric earlier in the USB use, and USB master unit's power can irritate the electricity for slave unit's USB controller this moment, and if USB slave unit did not irritate the electric protection and handle, cause USB slave unit host computer treater to appear irritating the electricity very easily and damage, can lead to other functions of whole product to lose seriously.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a can protect host computer USB power source to prevent that the host computer from receiving the power of irritating when plug USB connector and damaging, guarantee the reliability of product USB function.
In order to achieve the above object, the present disclosure provides a circuit capable of protecting a USB power interface of a host, which includes a host processor, a power supply protection circuit, an EMI circuit, an electrostatic protection device, and a USB connector.
The power supply protection circuit is electrically connected with a power line of the USB controller in the host processor and the USB connector, and provides a reliable power supply for the USB controller in the host processor; the EMI circuit is electrically connected with a data line of a USB controller in the host processor and the electrostatic protection device and is used for eliminating common-mode interference on a transmission data line; the static protection device is electrically connected with the EMI circuit and the USB connector, and is used for eliminating static carried by plugging and unplugging the USB connector on the USB data line and protecting the host processor from being damaged by the static; the USB connector is electrically connected with the electrostatic protector and the power supply protection circuit and is connected with an external USB main equipment connector to provide a power supply enabling signal for the power supply protection circuit, provide a USB data signal for the host processor and electrify the USB controller.
Optionally, the host processor is a processor with a function of a USB controller, and a first end of the USB controller is connected to the power supply protection circuit; the second end and the third end of the USB controller are connected with the EMI circuit;
optionally, the power supply protection circuit includes a first capacitor, a PMOS, a second capacitor, a first resistor, a second resistor, an NPN triode, a third resistor, a fourth resistor, and a first power supply.
The source stage of the PMOS is used as the power supply input end of the power supply protection circuit and is connected with a first power supply; the drain of the PMOS is used as the power output end of the power supply protection circuit and is connected with the host processor;
the first end of the first capacitor is respectively connected with the first power supply and the source stage of the PMOS, and the second end of the first capacitor is grounded; and the first end of the second capacitor is respectively connected with the host processor and the drain of the PMOS, and the second end of the second capacitor is grounded.
The first end of the first resistor is connected with the first power supply and the source stage of the PMOS respectively, and the second end of the first resistor is connected with the grid of the PMOS and the first end of the second resistor respectively.
A collector of the NPN triode is connected to the second end of the second resistor, a base of the NPN triode is connected to the first end of the third resistor and the first end of the fourth resistor, respectively, and an emitter of the NPN triode and the second end of the fourth resistor are grounded.
Optionally, the EMI circuit is a common mode filter, and a first end and a second end of the common mode filter are connected to the host processor; and the third end and the fourth end of the common mode filter are respectively connected with the electrostatic protection device and the USB connector.
Optionally, the electrostatic protection device includes a first TVS and a second TVS, and a first end of the first TVS is connected to the USB connector and the EMI circuit; the first end of the second TVS is connected with the USB connector and the EMI circuit; the second terminal of the first TVS and the second terminal of the second TVS are grounded.
Optionally, the first end of the USB connector is connected to a power supply protection circuit, and the second end and the third end of the USB connector are both connected to the electrostatic protection device and the EMI circuit.
Through the technical scheme, the power supply protection circuit is added to the power signal wire of the USB interface. When the USB main equipment is inserted into the outside of the USB connector, the power supply provided by the USB main equipment provides an enabling signal for the power supply protection circuit, and the power supply protection circuit is enabled, and then the internal power supply of the host computer supplies power for the USB controller of the host computer processor. According to the scheme, the power supply of the USB main equipment and the power supply of the USB controller of the host processor are isolated, and because the power supply of the USB controller of the host processor comes from the power supply of the host, if the host is powered off first, the power supply of the USB slave equipment and the power supply of the host are powered off at the same time, so that the power-filling risk is avoided.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
Fig. 1 is a circuit structure diagram of a USB power interface of a host according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a USB power interface of a host according to an embodiment of the present invention;
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
The embodiment of the present invention shown in fig. 1 provides a circuit capable of protecting a USB power interface of a host, which includes a host processor 1, a power supply protection circuit 2, an EMI circuit 3, an electrostatic protection device 4, and a USB connector 5.
The power supply protection circuit 2 is electrically connected with a power supply of the USB controller in the host processor 1 and the USB connector 5, and the power supply protection circuit provides a reliable power supply for the USB controller in the host processor; the EMI circuit 3 is electrically connected with a data line of a USB controller in the host processor 1 and the electrostatic protection device 4, and is used for eliminating common-mode interference on a transmission data line; the static protection device 4 is electrically connected with the EMI circuit 3 and the USB connector 5, and is used for eliminating static carried by a USB data line when the USB connector is plugged and pulled out, so as to protect a host processor from being damaged by the static; the USB connector 5 is electrically connected with the electrostatic protector 4 and the power supply protection circuit 2, simultaneously supports the insertion of an external USB main equipment connector, provides a power supply enabling signal for the power supply protection circuit 2, provides a USB data signal for the host processor 1 and powers on the USB controller.
Optionally, as shown in fig. 2, the host processor 1 is a processor with a function of a USB controller U1, and a first terminal of the USB controller U1 is connected to the power protection circuit 2; the second terminal and the third terminal of the USB controller U1 are connected with the EMI circuit 3;
optionally, the power supply protection circuit 2 includes a first capacitor C1, a PMOS P1, a second capacitor C2, a first resistor R1, a second resistor R2, an NPN transistor Q1, a third resistor R3, a fourth resistor R4, and a first power supply V1.
The source stage of the PMOS P1 is used as the power supply input end of the power supply protection circuit 2 and is connected with a first power supply; the drain of the PMOS P1 is used as the power output end of the power supply protection circuit 2 and is connected with the USB controller U1 of the host processor 1;
a first end of the first capacitor C1 is respectively connected with the first power supply V1 and the source stage of the PMOS P1, and a second end of the first capacitor C1 is grounded; a first terminal of the second capacitor C2 is connected to the drain of the USB controller U1 and the drain of the PMOS P1 of the host processor 1, respectively, and a second terminal of the second capacitor C2 is grounded.
A first end of the first resistor R1 is connected to the source of the first power source V1 and the source of the PMOS P1, respectively, and a second end of the first resistor R1 is connected to the gate of the PMOS P1 and the first end of the second resistor R2, respectively.
A collector of the NPN transistor Q1 is connected to the second end of the second resistor R2, a base of the NPN transistor Q1 is connected to the first end of the third resistor R3 and the first end of the fourth resistor R4, respectively, and an emitter of the NPN transistor Q1 and the second end of the fourth resistor R4 are grounded.
Optionally, the EMI circuit 3 may be a common mode filter L1, and the first terminal and the second terminal of the common mode filter L1 are connected to the USB controller U1 of the host processor 1; the third terminal and the fourth terminal of the common mode filter L1 are connected to the esd protection device 4 and the USB connector 5, respectively.
Optionally, the esd protection device 4 comprises a first TVS D1 and a second TVS D2, wherein a first terminal of the first TVS D1 is connected to the USB connector 5 and the EMI circuit 3; a first end of the second TVS D2 is connected to the USB connector 5 and the EMI circuit 3; the second terminal of the first TVS D1 and the second terminal of the second TVS D2 are grounded.
Alternatively, the USB connector may be a 4-pin connector P1, a first end of the connector P1 is connected to the power supply protection circuit 2, and a second end and a third end of the connector P1 are connected to the esd protection device 4 and the EMI circuit 3.
To sum up, the utility model provides a simple host computer USB power interface protection circuit of circuit. When a USB host device is inserted into the connector P1, the voltage signal of the Vbus pin of the connector P1 is output high, the voltage signal is divided by the second resistor R2 and the third resistor R3 to turn on the NPN transistor Q1, the collector voltage of the NPN transistor Q1 becomes 0V, the first resistor R1 and the second resistor R2 form a divided voltage to turn on the PMOS P1, and the first power supply V1 provides a power supply voltage for the USB _ Vbus of the USB controller U1 of the host processor 1. The first capacitor C1 and the second capacitor C2 are filter capacitors, and function to reduce ac ripple and smooth dc output. According to the scheme, the power supply of the USB main equipment is isolated from the power supply of the USB controller U1 of the host processor 1, and because the power supply of the USB controller U1 of the host processor 1 comes from the power supply of the host, if the host is powered off first, the power supply of the USB slave equipment and the power supply of the host are powered off at the same time, so that the power-filling risk is avoided.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (6)
1. A circuit for protecting a USB power interface of a host, comprising: a host processor, a power supply protection circuit, an EMI circuit, an electrostatic protection device and a USB connector,
the power supply protection circuit is electrically connected with the host processor and the USB connector; the EMI circuit is electrically connected with a data line of a USB controller in the host processor and the electrostatic protection device; the static protection device is electrically connected with the EMI circuit and the USB connector.
2. The circuit capable of protecting a host USB power interface of claim 1, wherein the host processor is a processor with USB controller functionality.
3. The circuit capable of protecting a host USB power interface according to claim 1, wherein the power protection circuit comprises a first capacitor C1, a PMOS P1, a second capacitor C2, a first resistor R1, a second resistor R2, an NPN transistor Q1, a third resistor R3, a fourth resistor R4 and a first power supply V1,
the source stage of the PMOS P1 is used as the power supply input end of the power supply protection circuit 2 and is connected with a first power supply; the drain of the PMOS P1 is used as the power output end of the power supply protection circuit 2 and is connected with the USB controller U1 of the host processor 1;
a first end of the first capacitor C1 is respectively connected with the first power supply V1 and the source stage of the PMOS P1, and a second end of the first capacitor C1 is grounded; a first terminal of the second capacitor C2 is connected to the drain of the USB controller U1 and the drain of the PMOS P1 of the host processor 1, respectively, and a second terminal of the second capacitor C2 is grounded.
4. The circuit capable of protecting a host USB power interface of claim 1, wherein the EMI circuit is a common mode filter.
5. The circuit capable of protecting a host USB power interface according to claim 1, wherein the esd protection device comprises a first TVS and a second TVS; the first end of the first TVS is connected with the USB connector and the EMI circuit; the first end of the second TVS is connected with the USB connector and the EMI circuit; the second terminal of the first TVS and the second terminal of the second TVS are grounded.
6. The circuit capable of protecting a host USB power interface of claim 1, wherein the USB connector has at least 4 pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023056601.4U CN214380067U (en) | 2020-12-16 | 2020-12-16 | Circuit capable of protecting USB power interface of host |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023056601.4U CN214380067U (en) | 2020-12-16 | 2020-12-16 | Circuit capable of protecting USB power interface of host |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214380067U true CN214380067U (en) | 2021-10-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202023056601.4U Active CN214380067U (en) | 2020-12-16 | 2020-12-16 | Circuit capable of protecting USB power interface of host |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214380067U (en) |
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2020
- 2020-12-16 CN CN202023056601.4U patent/CN214380067U/en active Active
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