CN214337878U

CN214337878U - High-performance numerical control transimpedance amplification circuit

Info

Publication number: CN214337878U
Application number: CN202120720137.XU
Authority: CN
Inventors: 童子权; 谷葳; 杨宇堃; 张鸿昊; 于国辉
Original assignee: Harbin University of Science and Technology
Current assignee: Harbin University of Science and Technology
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2021-10-01
Anticipated expiration: 2031-04-09

Abstract

The utility model relates to a high-performance numerical control transimpedance amplifying circuit, which belongs to the technical field of electronic measurement; the high-performance numerical control transimpedance amplification circuit comprises a voltage conversion unit, a numerical control gain decoding unit, a numerical control gain I/V signal conversion unit, a numerical control gain voltage signal amplification unit and a power amplification unit with signal zero setting; the high-performance numerical control transimpedance amplifier circuit adopts a pure logic circuit design and can realize digital control by utilizing a coding switch; through the T-shaped resistor feedback network for determining the resistance value in two stages, not only is the quantitative adjustment of the gain realized, but also the accuracy of the gain is improved; by adopting the two-stage amplifying circuit, the total gain of the input signal is combined by the respective gains of the two-stage amplifying circuit, thereby reducing the limitation on the signal bandwidth during high-gain application and improving the frequency bandwidth of the input signal.

Description

High-performance numerical control transimpedance amplification circuit

Technical Field

The utility model relates to a high performance numerical control transimpedance amplifier circuit belongs to electron measurement technical field.

Background

The transimpedance amplification circuit has wide application in the fields of weak current signal processing and photoelectric signal processing. In the field of weak current signal processing, current is a basic physical parameter, and signal processing is performed after the current is converted into voltage in many occasions, so that a circuit named as a transimpedance amplifier is generated; in the field of photoelectric signal processing, the application range of a photoelectric detector is very wide, and each link from people's life to industrial production is full of the shadow of the photoelectric detector, the photoelectric detector is generally composed of a photoelectric amplifier and a detection circuit, the working principle of the photoelectric amplifier is to convert a measured optical signal into a continuously-changing current signal through an analog photoelectric sensor, namely the combination of the photoelectric sensor and a transimpedance amplification circuit.

At present, a plurality of low-cost transimpedance amplification circuit modules are available in the market, and the modules are usually gain-adjusted by using potentiometers, so that quantitative adjustment is not convenient and fast; foreign manufacturers also have a digital gain photoelectric signal amplifier, and these transimpedance amplification circuits mostly adopt a single-stage signal amplification circuit to realize functions, so that the frequency bandwidth of signals is greatly influenced by gain along with the increase of gain.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model discloses a high-performance numerical control transimpedance amplifier circuit, which adopts a pure logic circuit design and can realize digital control by utilizing a coding switch; through the T-shaped resistor feedback network for determining the resistance value in two stages, not only is the quantitative adjustment of the gain realized, but also the accuracy of the gain is improved; by adopting the two-stage amplifying circuit, the total gain of the input signal is combined by the respective gains of the two-stage amplifying circuit, thereby reducing the limitation on the signal bandwidth during high-gain application and improving the frequency bandwidth of the input signal.

The purpose of the utility model is realized like this:

a high-performance numerical control transimpedance amplifier circuit is characterized in that: the digital gain control circuit is composed of a voltage conversion unit, a digital gain decoding unit, a digital gain I/V signal conversion unit, a digital gain voltage signal amplification unit and a power amplification unit with signal zero setting;

the voltage conversion unit consists of a linear voltage stabilizing chip 78L05, a linear voltage stabilizing chip 79L05 and a plurality of capacitors; pin 3 of the linear voltage regulation chip 78L05 is connected to + PW, and is coupled to GND through the filter capacitor E5, pin 2 is directly connected to GND, and pin 1 is coupled to GND through the filter capacitor E6, and is output as the +5V voltage of the linear voltage regulation chip; pin 2 of the linear voltage stabilization chip 79L05 is connected to-PW, and is coupled to GND through a filter capacitor E7, pin 1 is directly connected to GND, and pin 3 is coupled to GND through a filter capacitor E8 and is used as-5V voltage output of the linear voltage stabilization chip;

the numerical control gain decoding unit consists of a 3-bit binary rotary coding switch SWDB, a 3-8 line decoder and a plurality of resistors; the 3-bit binary rotary coding switch generates 8 states, and the 8 states correspond to 3-bit logic signals; the common terminal of the 3-bit binary rotary coding switch SWDB is connected with +5V, the K1 pin, the K2 pin and the K3 pin of the 3-bit binary rotary coding switch SWDB are grounded through pull-down resistors, and the generated 3-bit binary logic signals drive a 3-8 line decoder to realize the control of 8 gain states;

the digital control gain I/V signal conversion unit is composed of 1 3-pin analog input connecting terminal 15EDGX3, 1 low-noise operational amplifier U1A, 3 field effect transistors, 6 switching diodes, a plurality of resistors and a plurality of capacitors; inputting a current signal by using a 3-pin analog input connecting terminal 15EDGX3, and trans-impedance amplifying the current signal by using a T-shaped feedback resistance network; the 3-pin analog input connecting terminal 15EDGX3 is an analog input connector and comprises 3 connecting terminals, wherein the connecting terminal 1 is connected to +5V through a current-limiting resistor R5 and is connected to an analog ground GND through C6; the wiring terminal 2 is used as the input of a circuit signal, and the wiring terminal 3 is connected with a simulation ground GND; the low-noise operational amplifier U1A is 1 low-noise operational amplifier in a low-noise double operational amplifier chip, is used for I/V signal conversion of a numerical control gain I/V signal conversion unit, and has a GA-GD gain amplification range; the non-inverting input end of the low-noise operational amplifier U1A is grounded through a resistor R6, and the inverting input end of the low-noise operational amplifier U1A is directly coupled with a wiring terminal 2 of a 3-pin analog input wiring terminal 15EDGX to serve as a signal input end; a pin 1 and a pin 4 of a field effect transistor Q1 are connected in parallel with R7, the pin 4 after being connected in parallel is connected to a pin 2 of a low noise operational amplifier U1A, the pin 1 is connected to a pin 1 of a low noise operational amplifier U1A through R12, the pin 3 is connected with a pin 6, the pin 2 is connected with a pin 5 and then grounded through a resistor R24, and meanwhile, the pin is connected to a gain control end GA through a diode D1; a pin 1 of a field effect transistor Q2 is connected with a pin 1 of a low-noise operational amplifier U1A through a parallel-connected R8 and R9 and a R12; pin 3 is connected with pin 6, pin 4 is connected with GND, pin 2 is connected with pin 5 and then grounded through resistor R25, and simultaneously connected with gain control terminal GG through diode D2, gain control terminal GD through diode D3, and gain control terminal GE through diode D4; a pin 1 of a field effect transistor Q3 is connected with a pin 1 of a low-noise operational amplifier U1A through a parallel-connected R10 and R11 and a R12; pin 3 is connected with pin 6, pin 4 is connected with GND, pin 2 is connected with pin 5 and then grounded through resistor R26, and simultaneously connected to gain control terminal GF through diode D5 and connected to gain control terminal GH through diode D6;

the digital control gain voltage signal amplification unit is composed of 1 low noise operational amplifier U1B, 3 field effect transistors, 6 switching diodes, a plurality of resistors and a plurality of capacitors; the proportional amplification of the voltage signal is realized through a T-shaped feedback resistance network; an output pin 1 of the low-noise operational amplifier U1A in the numerical control gain I/V signal conversion unit is connected with an input pin 6 of an inverting end of the low-noise operational amplifier U1B in the numerical control gain voltage signal amplification unit through a resistor R13; a pin 5 of a non-inverting input end of the low-noise operational amplifier U1B is connected with GND through a resistor R14; a pin 1 and a pin 4 of a field effect transistor Q4 are connected in parallel with R15, the pin 4 after being connected in parallel is connected to a pin 6 of a low noise operational amplifier U1B, the pin 1 is connected to a pin 7 of the low noise operational amplifier U1B through R20, the pin 3 is connected with the pin 6, the pin 2 is connected with a pin 5 and then grounded through a resistor R27, and meanwhile, the pin is connected to a gain control end GA through a diode D7 and connected to a gain control end GB through a diode D8; a pin 1 of a field effect transistor Q5 is connected with a R20 through a R16 and a R17 which are connected in parallel, and is connected with a pin 7 of a low noise operational amplifier U1B, a pin 3 is connected with a pin 6, a pin 4 is connected with GND, a pin 2 is connected with a pin 5 and then is grounded through a resistor R28, and is connected with a gain control end GE through a diode D9 and is connected with a gain control end GF through a diode D10; a pin 1 of a field effect transistor Q6 is connected with a pin 1 of a low-noise operational amplifier U1B through a parallel-connected R18 and R19 and a R20; pin 3 is connected with pin 6, pin 4 is connected with GND, pin 2 is connected with pin 5 and then grounded through resistor R29, and simultaneously connected with gain control terminal GG through diode D11 and connected with gain control terminal GH through diode D12;

the signal zero-setting power amplification unit consists of 1 low-distortion current feedback operational amplifier U2, 2 field effect transistors, 1 SMA interface and a plurality of resistors and is used for adjusting offset voltage and bias current of a signal, the offset voltage is adjusted through a T-shaped resistor network when the signal is amplified in a single stage GA-GD, and the bias current is adjusted when the signal is amplified above GE in a single stage; the R21 is used as an input resistor of the low-distortion current feedback operational amplifier U2, one end of the R21 is connected with an output pin 7 of the low-noise operational amplifier U1B, and the other end of the R21 is connected with an inverted input end pin 2 of the low-distortion current feedback operational amplifier U2; one end of a feedback resistor of the R22 serving as the low-distortion current feedback operational amplifier U2 is connected with a pin 2 of the U2 of the low-distortion current feedback operational amplifier, and the other end of the feedback resistor is connected with an output pin 6 of the U2 of the low-distortion current feedback operational amplifier; one end of the R32 is connected with the + PW, while the other end is connected with the pin 2 of the low-distortion current feedback operational amplifier U2, and is connected to the output pin 6 of the low-distortion current feedback operational amplifier U2 through R22; one end of the R33 is connected with the PW, the other end of the R33 is connected with the pin 2 of the low-distortion current feedback operational amplifier U2, and meanwhile, the R22 is connected to the output pin 6 of the low-distortion current feedback operational amplifier U2; a pin 1 of a field effect transistor Q7 is connected with an output pin 6 of a low distortion current feedback operational amplifier U2 through R22, a pin 2 is connected with a gain control end GG or GH, the pin 6 is connected with-5V through R30, and is connected with +5V through R31; the R23 is used as an output impedance matching resistor, one end of the R23 is connected with the output pin 6 of the low-distortion current feedback operational amplifier U2, and the other end of the R23 is connected with OUT to be used as the output of the circuit; and the total output interface of the circuit selects an SMA interface.

Has the advantages that:

first, the utility model relates to a high performance numerical control transimpedance amplifier circuit adopts pure logic circuit design, utilizes the coding switch can realize digital control.

Second, the utility model relates to a high performance numerical control transimpedance amplifier circuit, through the T type resistance feedback network of the resistance is confirmed to the two-stage, not only realize the quantitative regulation of gain, improve the degree of accuracy of gain moreover.

Third, the utility model relates to a high performance numerical control transimpedance amplifier circuit through adopting two-stage amplifier circuit, makes input signal's total gain combine by two-stage amplifier circuit gain separately to the injecing of signal bandwidth when reducing high gain and applying, improve input signal's frequency bandwidth.

Drawings

Fig. 1 is a schematic diagram of the overall structure of a high-performance digital control transimpedance amplifier circuit according to the present invention.

Fig. 2 is a circuit diagram of a voltage converting unit.

FIG. 3 is a circuit diagram of a digitally controlled gain decoding unit.

FIG. 4 is a circuit diagram of a digital control gain I/V signal conversion unit.

FIG. 5 is a circuit diagram of a digitally controlled gain voltage signal amplifying unit.

Fig. 6 is a circuit diagram of a power amplification unit with signal zeroing.

Detailed Description

The following describes the present invention in further detail with reference to the attached drawings.

The utility model discloses resistance amplifier circuit is striden in high performance numerical control, as shown in FIG. 1, the circuit includes: the digital gain control circuit comprises a voltage conversion unit, a digital control gain decoding unit, a digital control gain I/V signal conversion unit, a digital control gain voltage signal amplification unit and a power amplification unit with signal zero setting.

Referring to fig. 2, the voltage conversion unit is composed of 2 linear voltage stabilization chips and a plurality of capacitors. Pin 3 of the linear regulator chip V1 is connected to + PW power voltage as its voltage input, and is coupled to GND by using the capacitor E5 as power filter. Pin 2 of the linear regulator chip V1 is directly connected to GND, and pin 1 serves as a voltage output pin of the linear regulator chip to output + 5V. Meanwhile, the capacitor E6 is used for power supply filtering and is connected to GND. Pin 2 of the linear regulator chip V2 is connected to-PW power supply voltage as its voltage input. And is coupled to GND by using a capacitor E7 for power supply filtering. Pin 1 of V2 is directly connected to GND, pin 3 of V2 is connected to the voltage output pin of the linear voltage stabilization chip to output-5V voltage, and the voltage is connected to GND by using capacitor E8 as power supply filter.

Referring to fig. 3, the digital controlled gain decoding unit is composed of a coding switch SWDB, a 3-line-8-line decoder 74HC238, and a plurality of resistors. A3-bit binary rotary coding switch generates 8 states, and the 8 states correspond to 3-bit logic signals to drive a 74HC238 decoder, so that the control of 8 gain states is realized. Pin 2 of the common port of SWDB is connected to pin 5 + 5V. Pin 1 of the SWDB is connected to GND through a pull-down resistor R2, and is also connected to pin 1 of the U4 decoder 74HC238, serving as an address input terminal of the 3-line-8-line decoder 74HC 238; pin 4 is connected to GND through a pull-down resistor R3 and to pin 2 of the U4 decoder 74HC238, serving as an address input of the 3-line-8-line decoder 74HC 238; pin 3 is connected to GND through pull-down resistor R4 and to pin 3 of U4 decoder 74HC238, which serves as an address input of 3-line-8-line decoder 74HC 238. The power input pin 16 of 74HC238 is connected to pin 6 of the high enable input plus 5V. Pin 4 and pin 5 are connected to GND as low-level enable terminals to pin 8. The output pin 15 is used as a control end when the gain is GA; the output pin 14 is used as a control end when the gain is GB; the output pin 13 is used as a control end when the gain is GC; the output pin 12 is used as a control end when the gain is GD; the output pin 11 is used as a control end when the gain is GE; the output pin 10 is used as a control end when the gain is GF; the output pin 9 is used as a control end when the gain is GG; the output pin 7 serves as a control terminal when the gain is GH.

Referring to fig. 4, the digital control gain I/V signal conversion unit is composed of a 3-pin analog input connection terminal 15EDGX3, 1 low-noise operational amplifier chip, 3 field effect transistors, 6 switching diodes, several resistors and capacitors. The unit utilizes 15EDGX3 analog input connector to input current signals, and trans-impedance amplification is achieved on the current signals through a T-shaped feedback resistance network. 15EDGX3 is an analog input connector, and has 3 terminals, terminal 1 is connected to current-limiting resistor R5 for connecting +5V, and is connected to C6 for connecting to analog ground GND of the circuit. The terminal 2 is used as the input of circuit signals, and the terminal 3 is connected with the analog ground GND. U1A is 1 integrated operational amplifier in the low noise dual operational amplifier chip, is used as the I/V signal conversion of the numerical control gain I/V signal conversion unit, and the range is GA-GD gain amplification. The non-inverting input terminal of the operational amplifier U1A is grounded through a resistor R6, and the pin 2 of the inverting input terminal of U1A is directly coupled to the terminal 2 of 15EDGX as the input terminal of the signal. The pin 1 and the pin 4 of the field effect transistor Q1 are connected in parallel with the R7, the pin 4 after being connected in parallel is connected to the pin 2 of the operational amplifier U1A, the pin 1 is connected to the pin 1 of the operational amplifier U1A through the R12, the pin 3 is connected with the pin 6, the pin 2 is connected with the pin 5 and then grounded through the resistor R24, and meanwhile, the pin is connected to the gain control end GA through the diode D1. Pin 1 of the field effect transistor Q2 is connected with R12 through parallel R8 and R9, and is connected to pin 1 of the operational amplifier U1A. Pin 3 is connected with pin 6, and pin 4 connects GND, and pin 2 is connected with pin 5 back through resistance R25 ground connection, simultaneously inserts gain control end GG through diode D2, inserts gain control end GD through diode D3, inserts gain control end GE through diode D4. Pin 1 of the field effect transistor Q3 is connected with R12 through parallel R10 and R11, and is connected to pin 1 of the operational amplifier U1A. Pin 3 is connected to pin 6, pin 4 is connected to GND, pin 2 is connected to pin 5 and then grounded through resistor R26, and simultaneously connected to gain control terminal GF through diode D5 and connected to gain control terminal GH through diode D6.

When the operational amplifier is powered by a +/-5V power supply and the step value of the selected gain is 6db, the resistance value of R6 is 1K5 omega, the resistance value of R7 is 1K5 omega, the resistance value of R8 is 1K5 omega, the resistance value of R9 is 1K5 omega, the resistance value of R10 is 500 omega, the resistance value of R11 is 500 omega, and the resistance value of R12 is 1K5 omega. When the step value of the selected gain is 10db, the resistance value of R6 is 1K5 Ω, the resistance value of R7 is 3K3 Ω, the resistance value of R8 is 900 Ω, the resistance value of R9 is 1K Ω, the resistance value of R10 is 220 Ω, the resistance value of R11 is 220 Ω, and the resistance value of R12 is 1K5 Ω. When the step value of the selected gain is 12db, the resistance value of R6 is 1K5 Ω, the resistance value of R7 is 4K5 Ω, the resistance value of R8 is 750 Ω, the resistance value of R9 is 750 Ω, the resistance value of R10 is 320 Ω, the resistance value of R11 is 320 Ω, and the resistance value of R12 is 1K5 Ω.

Referring to fig. 5, the digital control gain voltage signal amplifying unit is composed of 1 low noise operational amplifier chip, 3 field effect transistors, 6 switching diodes, several resistors and capacitors. The unit realizes the proportional amplification of the voltage signal through a T-shaped feedback resistance network.

The output pin 1 of the digital control gain I/V signal conversion unit U1A is connected with the inverting terminal input pin 6 of the digital control gain voltage signal amplification unit U1B through a resistor R13. The pin 5 of the inverting input terminal of U1B is connected to GND through a resistor R14. The pin 1 and the pin 4 of the field effect transistor Q4 are connected in parallel with the R15, the pin 4 after being connected in parallel is connected to the pin 6 of the operational amplifier U1B, the pin 1 is connected to the pin 7 of the operational amplifier U1B through the R20, the pin 3 is connected with the pin 6, the pin 2 is connected with the pin 5 and then grounded through the resistor R27, and meanwhile, the pin is connected to the gain control end GA through the diode D7 and connected to the gain control end GB through the diode D8. Pin 1 of the field effect transistor Q5 is connected with R20 through R16 and R17 which are connected in parallel, and is connected with pin 7 of the operational amplifier U1B, pin 3 is connected with pin 6, pin 4 is connected with GND, pin 2 is connected with pin 5 and then is grounded through a resistor R28, and is connected with the gain control terminal GE through a diode D9, and is connected with the gain control terminal GF through a diode D10. Pin 1 of the field effect transistor Q6 is connected with R20 through parallel R18 and R19, and is connected to pin 1 of the operational amplifier U1B. Pin 3 is connected to pin 6, pin 4 is connected to GND, pin 2 is connected to pin 5 and then grounded through resistor R29, and simultaneously connected to gain control terminal GG through diode D11 and connected to gain control terminal GH through diode D12.

When the operational amplifier is powered by a +/-5V power supply and the step value of the selected gain is 6db, the resistance value of R13 is 1K5 omega, the resistance value of R14 is 1K5 omega, the resistance value of R15 is 1K5 omega, the resistance value of R16 is 1K5 omega, the resistance value of R17 is 1K5 omega, the resistance value of R18 is 200 omega, the resistance value of R19 is 200 omega, and the resistance value of R20 is 1K5 omega. When the step value of the selected gain is 10db, the resistance value of R13 is 1K5 Ω, the resistance value of R14 is 1K5 Ω, the resistance value of R15 is 3K3 Ω, the resistance value of R16 is 900 Ω, the resistance value of R17 is 1K Ω, the resistance value of R18 is 65 Ω, the resistance value of R19 is 70 Ω, and the resistance value of R20 is 1K5 Ω. When the step value of the selected gain is 12db, the resistance value of R13 is 1K5 Ω, the resistance value of R14 is 1K5 Ω, the resistance value of R15 is 4K5 Ω, the resistance value of R16 is 750 Ω, the resistance value of R17 is 750 Ω, the resistance value of R18 is 20 Ω, the resistance value of R19 is 20 Ω, and the resistance value of R20 is 1K5 Ω.

Referring to fig. 6, the power amplifying unit with signal zeroing is composed of 1 low-distortion current feedback operational amplifier, 2 field effect transistors, 1 interface, and several resistors. The unit conditions offset voltage and bias current of signals, adjusts the offset voltage through a T-shaped resistor network when a single stage amplifies 0-30 db, and conditions the bias current when the single stage amplifies more than 40 db.

R21 is an input resistor of U2, and has one end connected to the output pin 7 of U1B and one end connected to the inverting input pin 6 of U2. One end of the feedback resistor of the U2R 22 is connected to the pin 2 of the U2, and the other end is connected to the output pin 6 of the U2. One end of R32 is connected to + PW, the other end is connected to pin 2 of the operational amplifier U2, and the output pin 6 of U2 is connected through R22. One end of R33 is connected with-PW, while the other end is connected with pin 2 of operational amplifier U2 and is connected with output pin 6 of U2 through R22. Pin 1 of the field effect transistor Q7 is connected to the output pin 6 of U2 through R22, pin 2 is connected to the gain control terminal GG or GH, and pin 6 is connected to-5V through R30 and +5V through R31. And R23 is used as an output impedance matching resistor, one end of the R23 is connected with the output pin 6 of the U2, and the other end of the R23 is connected with the SMA interface to be used as the total output of the circuit.

According to the technical parameter that above embodiment provided, the utility model discloses resistance amplifier circuit is striden in high performance numerical control has following functional index: the selectable gain range of the I/V conversion signal is realized, and the selectable gain range is 0-42 dB when the stepping value is 6 dB; the selectable gain range is 0-70 dB when the step value is 10 dB; the selectable gain range is 0-84 dB for a step value of 12 dB.

The basic principles and the main features of the invention and the advantages of the invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A high-performance numerical control transimpedance amplifier circuit is characterized in that: the digital gain control circuit is composed of a voltage conversion unit, a digital gain decoding unit, a digital gain I/V signal conversion unit, a digital gain voltage signal amplification unit and a power amplification unit with signal zero setting;