CN214336720U

CN214336720U - Semiconductor device and electronic device

Info

Publication number: CN214336720U
Application number: CN201921451962.3U
Authority: CN
Inventors: 黎子兰
Original assignee: Guangdong Zhineng Technology Co Ltd
Current assignee: Guangdong Zhineng Technology Co Ltd
Priority date: 2019-08-30
Filing date: 2019-08-30
Publication date: 2021-10-01
Anticipated expiration: 2029-08-30

Abstract

The present disclosure provides a semiconductor device, the device comprising a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; the first semiconductor layer has a smaller forbidden band width than the second semiconductor layer; the first electrode and the third electrode are formed on the first semiconductor layer or the second semiconductor layer, the second electrode is formed on the second semiconductor layer, the third semiconductor layer is arranged below the second electrode, and the third semiconductor layer is a P-type third semiconductor layer. The scheme of the disclosure can at least help to realize one of the following effects: the gate leakage current is reduced, the high threshold voltage, the high power and the high reliability are realized, the low on-resistance and the normally-off state of the device can be realized, and the stable threshold voltage can be provided, so that the semiconductor device has good switching characteristics and is safer in use.

Description

Semiconductor device and electronic device

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and an electronic apparatus.

Background

Group III nitride semiconductors are an important new semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. Because of the advantages of direct band gap, wide forbidden band, high breakdown electric field intensity, high saturated electron speed and the like, the III group nitride semiconductor has wide application prospect in the fields of light-emitting devices, power electronics, radio frequency devices and the like.

It is desirable to develop a semiconductor device having high performance such as high withstand voltage, high power, and low on-resistance by optimizing the design of the device structure and process, utilizing the advantages of the group III nitride semiconductor.

Disclosure of Invention

A brief summary of the disclosure is provided below in order to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

According to an aspect of the present disclosure, there is provided a semiconductor device including

A substrate; a first semiconductor layer formed on the first surface of the substrate; a second semiconductor layer formed on the first surface of the first semiconductor layer; the first semiconductor layer has a smaller forbidden band width than the second semiconductor layer; a first electrode and a third electrode formed on the first or second semiconductor layer, a second electrode formed on the second semiconductor layer; the length range of the third semiconductor layer projected to the substrate is within the length range of the second electrode projected to the substrate, and the third semiconductor layer is a P-type semiconductor layer.

According to another aspect of the present disclosure, there is provided a semiconductor device manufacturing method including: providing a substrate; forming a first semiconductor layer on a first surface of the substrate; forming a third semiconductor layer in the first semiconductor layer; forming a second semiconductor layer on a first surface of the first semiconductor layer; the first semiconductor layer has a smaller forbidden band width than the second semiconductor layer, thereby forming a two-dimensional charge carrier gas at an interface of the first semiconductor layer and the second semiconductor layer; forming a first electrode and a third electrode having a two-dimensional charge carrier gas ohmic contact, and forming a second electrode on a first surface side of a third semiconductor layer, wherein a length range of the third semiconductor layer projected to a substrate is within a length range of the second electrode projected to the substrate.

According to another aspect of the present disclosure, there is provided an electronic device including the semiconductor device described in the present disclosure.

According to another aspect of the disclosure, the electronic device is a power supply device, a server, a charger, a cell phone, or an amplifier.

The scheme of the disclosure can at least help to realize one of the following effects: the semiconductor device can reduce grid leakage current, has high threshold voltage, high power and high reliability, can realize low on-resistance and normally-off state of the device, and can provide stable threshold voltage, so that the semiconductor device has good switching characteristic and is safer in use.

Drawings

The above and other objects, features and advantages of the present disclosure will be more readily understood from the following detailed description of the present disclosure with reference to the accompanying drawings. The drawings are only for the purpose of illustrating the principles of the disclosure. The dimensions and relative positioning of the elements in the figures are not necessarily drawn to scale. In the drawings:

fig. 1 shows a schematic cross-sectional view of a semiconductor device structure according to a first embodiment;

fig. 2 shows a schematic cross-sectional view of a structural modification of the semiconductor device according to the first embodiment;

fig. 3 shows a schematic cross-sectional view of a structural variant of the semiconductor device according to the first embodiment;

fig. 4 shows an energy band diagram of the semiconductor device in the first embodiment;

fig. 5 shows a schematic cross-sectional view of a structural modification of the semiconductor device according to the first embodiment;

fig. 6 shows a schematic cross-sectional view of a semiconductor device structure according to a second embodiment;

fig. 7 shows a schematic cross-sectional view of a semiconductor device structure according to a third embodiment;

fig. 8 shows a schematic cross-sectional view of a semiconductor device structure according to a fourth embodiment;

fig. 9 shows a schematic top view of a semiconductor device structure according to a fifth embodiment;

fig. 10 shows a perspective view of a semiconductor device structure according to a fifth embodiment;

fig. 11 shows a schematic cross-sectional view of a semiconductor device structure according to a sixth embodiment;

fig. 12 to 22 are schematic cross-sectional views showing a method of manufacturing a semiconductor device of a seventh embodiment;

fig. 23 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device of an eighth embodiment;

fig. 24 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device of the ninth embodiment;

fig. 25 shows a schematic cross-sectional view of a manufacturing method of a semiconductor device of the tenth embodiment.

Detailed Description

Exemplary disclosures of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an actual disclosure are described in the specification. It will be appreciated, however, that in the development of any such actual disclosure, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another.

Here, it should be further noted that, in order to avoid obscuring the present disclosure by unnecessary details, only the device structure closely related to the scheme according to the present disclosure is shown in the drawings, and other details not so related to the present disclosure are omitted.

It is to be understood that the disclosure is not limited to the described embodiments, as described below with reference to the drawings. Herein, features between different implementations may be replaced or borrowed where feasible, and one or more features may be omitted in one implementation.

First embodiment

A semiconductor device according to a first embodiment is described with reference to fig. 1.

Specifically, the semiconductor device of the first embodiment is a compound semiconductor device. Further, the compound semiconductor device is a compound semiconductor device including a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a field effect transistor in which a nitride semiconductor material is used. Further, the field effect transistor is a GaN field effect transistor comprising GaN semiconductor material. In particular, the GaN field effect transistor is a normally-off transistor GaN-HEMT.

As shown in fig. 1, in the first embodiment, the semiconductor device, such as an exemplary normally-off transistor GaN-HEMT, includes a substrate 100, and a material of the substrate 100 may be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Alternatively, the substrate 100 may be sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al₂O₃Or single crystal silicon or the like; further, the substrate 100 may be (0001) -plane Al₂O₃(ii) a Further the substrate 100 may be a (111) plane silicon substrate 100. A first semiconductor layer 102 formed on the first surface of the substrate 100, wherein optionally, the first semiconductor layer 102 is a GaN layer. Further, the first semiconductor layer 102 is i-GaN or an unintentionally doped GaN layer. The first semiconductor layer 102 has a second surface opposite to the first surface of the substrate 100 and has a first surface facing away from the first surface of the substrate 100. The epitaxial direction of the GaN layer parallel to the substrate is [ 0001%]And (4) direction.

At the placeA second semiconductor layer 103 is formed on the first surface of the first semiconductor layer 102. The first semiconductor layer 102 has a smaller forbidden bandwidth than the second semiconductor layer 103, thereby forming a two-dimensional charge carrier gas, for example, 2DEG, between the first semiconductor layer 102 and the second semiconductor layer 103. The second semiconductor layer 103 has a second surface opposite to the first surface of the first semiconductor layer 102 and has a first surface facing away from the second surface of the first semiconductor layer 102. Optionally, the second semiconductor layer 103 is an AlN, AlGaN, InAlGaN, InAlN layer, or the like. A first insulating layer 105 formed on a first surface of the second semiconductor layer 103. The first insulating layer 105 may be a passivation layer, optionally the passivation layer material being SiO₂、SiN、 Al₂O₃And the like.

A first electrode 106, a second electrode 108, and a third electrode 107 are formed, which may be formed on the first semiconductor layer 102 or on the second semiconductor layer 103. The first electrode 106 may be an ohmic contact formed by a source electrode and the two-dimensional charge carrier gas, the second electrode 108 may be a schottky contact formed by a gate electrode and the second semiconductor layer, and the third electrode 107 may be an ohmic contact formed by a drain electrode and the two-dimensional charge carrier gas. It will be appreciated that the first electrode 106 and the third electrode 107 may also be a respective first doped region (source region) and second doped region (drain region) of the device, illustratively, regions doped with Si.

The third semiconductor layer 104 is disposed below the second electrode 108, the third semiconductor layer 104 is a P-type third semiconductor layer 104, and optionally, the P-type third semiconductor layer 104 is P-type GaN. Wherein the P-GaN layer can directly contact the second semiconductor layer or be separated from the second semiconductor layer by a certain thickness. Illustratively, a certain first semiconductor material may be spaced between the two. Since the third semiconductor layer 104 has a lower fermi level, the 2DEG located thereabove may be depleted, thereby resulting in a higher threshold voltage of the device and a normally-off state of the device.

The third semiconductor layer 104 is configured, such as its thickness, length, width, P-The doping concentration of the type and the like can be set through device parameters so as to meet the requirement of depleting 95% -100% of 2DEG above the doping concentration. Correspondingly, the threshold voltage of the device is above 0 volt. Illustratively, the doping concentration of the P-type impurity may be 1E +17/cm³-5E+19/cm³。

Further, a length range of an orthographic projection of the third semiconductor layer 104 along the two-dimensional charge carrier gas flow direction is located within a length range of an orthographic projection of the second electrode 108 along the direction (i.e., within a gate length range), and the length range of the third semiconductor layer 104 may be set to be greater than 0 and smaller than the gate length. Or the length range of the third semiconductor layer 104 projected to the substrate is within the length range of the second electrode 108 projected to the substrate. As shown in fig. 1, the third semiconductor layer 104 disposed in the gate length range can avoid depletion of the two-dimensional electron gas in the non-gate stack region, which in turn results in a lower on-resistance and good switching characteristics of the device.

Further, the third semiconductor layer 104 has a second surface opposite to the first surface of the first semiconductor layer 102, and has a first surface facing away from the first surface of the first semiconductor layer. The third semiconductor layer 104 also has a third surface (e.g., a side plane) connecting the first and second surfaces of the third semiconductor layer 104. The third surface of the third semiconductor layer 104 and the first surface of the third semiconductor layer 104 form an included angle C. The included angle C may be 30-90 degrees.

Optionally, the growth surface of the third semiconductor layer 104 is a (11-20) surface.

Further, the third semiconductor layer 104 may have a single-layer structure, or may be formed of a plurality of discrete layers larger than 2. For example, as shown in fig. 2, the third semiconductor layer 104 may be a layer separated along the direction parallel to the substrate 100, and the layers separated along the direction parallel to the substrate 100 may overlap in the orthographic projection or may not overlap in the orthographic projection. The third semiconductor layer 104 may also be formed of discrete layers in a direction perpendicular to the substrate 100 as shown in fig. 3. The discrete layers can be in intimate contact with each other, or can have a spacing between them, which can result in improved device performance and reduced electric fields in the device.

Further, the third semiconductor layer 104 may be a structure with a graded doping concentration. The doping concentration may be gradually changed from the center of the third semiconductor layer 104 to two sides of the parallel substrate 100, or the third semiconductor layer 104 may be a single-side gradual change of the parallel substrate 100, or may be gradually changed from the center of the third semiconductor layer 104 to two sides of the vertical substrate 100, or the third semiconductor layer 104 may be a single-side gradual change of the vertical substrate 100.

Further, the threshold voltage of the device can be controlled by the doping element of the third semiconductor layer 104, the doping concentration, the distance between the third semiconductor layer 104 and the barrier layer, the width of the third semiconductor layer 104, the gate electrode material, and the composition and thickness of the second semiconductor layer. The doping concentration of the third semiconductor layer 104 is preferably about 1E +19cm³The gate electrode material can be Au, and the third semiconductor layer 104 has a length of 0.01 to 10 micrometers and a thickness of 0.01 to 10 micrometers. The length of the third semiconductor layer along the two-dimensional charge carrier gas flow direction (corresponding to the gate length in the device) can accurately control the process parameters such as epitaxial time and the like through lateral external delay, and further realize the very thin length dimension. Since the resistance of the depletion region is usually relatively high, reducing the length of the depletion region can effectively reduce the on-resistance of the device, and is also beneficial to reducing the size of the device and improving the area utilization rate of the wafer.

Fig. 4 is an energy band diagram of the semiconductor device, and it can be seen from fig. 4 that in the present disclosure, when the third semiconductor layer is disposed below the second electrode, a depletion layer of the semiconductor device is narrow, depletion of two-dimensional carrier charges is fast, and controllability of two-dimensional electron gas depletion at a position corresponding to the second electrode (gate stack) in the semiconductor device can be effectively achieved; when the third semiconductor layer is disposed deviating from the second electrode, the two-dimensional electron gas outside the corresponding position (gate stack) of the second electrode is consumed and cannot be controlled by the second electrode, so that the on-state resistance of the semiconductor device is significantly increased, and even the semiconductor device cannot be turned on.

Further, as shown in fig. 5, a fourth semiconductor layer 120 may be disposed between the first semiconductor layer 102 and the second semiconductor layer. Illustratively, the fourth semiconductor layer 120 may be an AlN layer, and the fourth semiconductor layer 120 may reduce the effects of impurity scattering and the like, thereby increasing the mobility of electrons in the channel.

Further, a fifth and/or sixth semiconductor layer may be provided between the second semiconductor layer and the substrate 100. Illustratively, the fifth semiconductor layer 112 may be a group III nitride buffer layer, and the sixth semiconductor layer may be a nitride semiconductor layer, such as an AlN layer. The fifth semiconductor layer may be over the sixth semiconductor layer.

Further, the third semiconductor layer may be formed in the fifth and/or sixth semiconductor layer, and the third semiconductor layer formed in the fifth and/or sixth semiconductor layer is denoted by 104'.

The semiconductor device structure, in particular the structural design of the third semiconductor layers 104, 104', avoids the poor crystal quality and electrical properties of the P-GaN semiconductor layer when a semiconductor layer, such as P-GaN, is grown after the first insulating layer 105 is formed on the first surface of the second semiconductor layer. The semiconductor device structure can obtain a high-quality P-GaN semiconductor layer in or before a channel is manufactured, and further can obtain a reliable normally-closed device with higher threshold voltage and low gate leakage

Second embodiment

A semiconductor device according to a second embodiment is described with reference to fig. 6.

On the basis of the first embodiment, a second insulating layer 101 may be formed between the substrate 100 and the first semiconductor layer 102, a groove may be formed in the insulating layer under the first electrode 106, and a seed layer 111 may be formed in the groove. The seed layer 111 facilitates the formation of a nitride semiconductor layer, such as the first semiconductor layer 102 or the fifth semiconductor layer 112, having low roughness and low dislocation density and enables symmetric epitaxy during lateral epitaxy, improving the growth quality of the semiconductor layer and making efficient use of the wafer area.

Third embodiment

A semiconductor device according to a third embodiment is described with reference to fig. 7.

On the basis of the first embodiment, a third insulating layer 109 may be further provided between the second semiconductor layer and the second electrode 108, and the third insulating layer 109 may be silicon dioxide, silicon nitride, or Al₂O₃And the like. The third insulating layer 109 can further reduce the gate leakage current of the second electrode 108 (gate), and the existence of the third insulating layer 109 can expand the voltage range of the gate, thereby enhancing the reliability of the device.

Fourth embodiment

A semiconductor device according to a fourth embodiment is described with reference to fig. 8.

On the basis of the first embodiment, an opening 10 is formed at the second surface of the substrate 100, and a fourth electrode 110 connected to the third semiconductor layer 104 (e.g., P-GaN) is formed therein. Since the potential of the third semiconductor layer 104 is floating when it is not connected to any electrode or potential, the threshold voltage of the device is unstable. After the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the device can provide a stable threshold voltage.

It is clear that the second or third embodiment can be combined on the basis of the fourth embodiment to obtain the advantageous effects as described above.

Fifth embodiment

A semiconductor device according to a fifth embodiment is described with reference to fig. 9 to 10.

In the fifth embodiment, on the basis of the first embodiment, a fourth electrode 110 connected to the third semiconductor layer 104 may be formed at a position not covered by the orthographic projection of the second electrode 108, extending in the direction perpendicular to the two-dimensional flow of the charge carrier gas in the third semiconductor layer 104 (for example, P-GaN). Since the potential of the third semiconductor layer 104 is floating when it is not connected to any electrode or potential, the threshold voltage of the device is unstable. After the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the device can provide a stable threshold voltage.

It is clear that the second or third embodiment can be combined on the basis of the fifth embodiment to obtain the advantageous effects as described above.

Sixth embodiment

A semiconductor device according to a sixth embodiment is described with reference to fig. 11.

In the sixth embodiment, a fourth electrode 110 connected to the third semiconductor layer 104 (e.g., P-GaN) may be formed at the first electrode 106 of the device on the basis of the first embodiment. Illustratively, the surface of the first electrode 106 contacting the second semiconductor layer may extend downward to form an L-shaped ohmic contact, and is connected to the third semiconductor layer 104. Since the potential of the third semiconductor layer 104 is floating when it is not connected to any electrode or potential, the threshold voltage of the device is unstable. When the third semiconductor layer 104 is connected to the fourth electrode 110, the potential of the third semiconductor layer 104 can be controlled by the fourth electrode 110, so that the semiconductor device can provide a stable threshold voltage.

It is clear that the second or third embodiment can be combined on the basis of the sixth embodiment to obtain the advantageous effects as described above.

Seventh embodiment

A manufacturing method for manufacturing the semiconductor devices of the first and second embodiments will now be exemplarily described with reference to fig. 12 to 22.

Step 100, providing a substrate 100, and selecting a material of the substrate 100 is described in the first embodiment, which is not described herein again.

Step 110, depositing and forming the second insulating layer 101 on the first surface of the substrate 100, wherein the second insulating layer 101 covers the whole surface of the substrate 100. At least a portion of the second insulating layer 101 is removed, preferably at least a portion of the second insulating layer 101 corresponding to a region where the first electrode (source) is subsequently formed is removed, an opening is formed to expose a portion of the substrate 100, and then a seed layer is formed by a deposition process on the second insulating layer by a co-planar deposition. The seed layer 111 and the second insulating layer each have a second surface opposite the first surface of the substrate 100 and a first surface facing away from the first surface of the substrate 100. Wherein the material of the second insulating layer 101 is not limited. The seed layer may be selected to be a material for the growth core of the first semiconductor layer 102.

Alternatively, step 110' deposits a seed material on the first surface of the substrate 100, and photolithographically etches away a portion of the seed material, such that the remaining seed layer serves as a growth core for the first semiconductor layer 102. Preferably, the region of the seed layer that remains corresponds to the region where the first electrode (source) region is subsequently formed. Then, an insulating material is deposited on the first surface of the substrate 100, the substrate 100 and the seed layer are covered completely, and a part of the insulating material is removed to form a second insulating layer so as to expose the seed layer. The seed layer and the second insulating layer each have a second surface opposite the first surface of the substrate 100 and a first surface facing away from the first surface of the substrate 100.

Step 120, forming the first semiconductor layer 102 on the first surface of the second insulating layer and the seed layer by using the seed layer as a central selection area/lateral epitaxy.

It is to be understood that

steps

110, 111 and step 120 described above are not necessary in the first embodiment. The first semiconductor layer 102 (e.g., GaN) may be formed directly after step 100. The growth method of the first semiconductor layer 102 is not particularly limited, and a Metal Organic Chemical Vapor Deposition (MOCVD), a Hydride Vapor Phase Epitaxy (HVPE), or other techniques may be used.

The method for forming the first semiconductor layer 102 by using the seed layer as a central lateral epitaxy is specifically described as follows with reference to fig. 14 to 19:

step 121, selecting/laterally epitaxially growing a first region of the first semiconductor layer 102 containing a low-doped or non-intentionally doped nitride semiconductor with the seed layer as a center, wherein the first region of the first semiconductor layer 102 starts to grow from the position of the seed layer, and the growth of the first region is stopped when the first semiconductor layer 102 does not completely cover the second insulating layer 101 by controlling the growth rate of the first region.

Step 122, taking the first region of the grown first semiconductor layer 102 as a core, continuing the growth of the P-type doped nitride layer on the surface and the side surface of the first region of the first semiconductor layer 102, and after growing the P-type doped nitride layer with a certain thickness, removing a portion of the upper surface of the P-type nitride semiconductor layer 104 or removing a portion of the upper surface of the P-type nitride semiconductor layer 104 and a portion of the first region of the first semiconductor layer 102 to expose the P-type nitride semiconductor layer 104 and the first region of the first semiconductor layer 102. Preferably, the projected length of the P-type nitride semiconductor layer ranges within the length of the projected area of the second electrode 108 to be formed later, and the width of the P-type nitride semiconductor layer may exceed the width of the second electrode. The fabrication of the third semiconductor layer 104 is thus completed, and more specifically, a P-type doped nitride layer such as P-GaN whose lateral growth direction is the [11-20] crystal orientation, and whose growth plane may be a vertical (11-20) plane, and whose specific dimensions may be, for example, about 0.01-10 microns in length and about 0.01-10 microns in height. Compared with the case that the transverse growth direction of the P-GaN is in a crystal orientation of 10-10, and the stable growth surface of the P-GaN is an inclined (1-101) surface, when the transverse growth direction is in a crystal orientation of 11-20, the transverse growth speed of the P-GaN is higher, and the performance of the device is more excellent.

Step 123, taking the third semiconductor layer 104 and the first region of the first semiconductor layer 102 as nucleation centers, continuing to grow a second region of the first semiconductor layer 102 comprising a low-doped or an unintentionally doped nitride semiconductor until the second region of the first semiconductor layer 102 completely covers the substrate 100/the first insulating layer 105. The first regions of the P-type nitride semiconductor layer and the first semiconductor layer may be exposed and made flush by removing portions of the lowly doped or unintentionally doped nitride semiconductor layer and the P-type nitride semiconductor layer, as shown in fig. 16. Or the first surface of the first semiconductor layer 102 facing away from the substrate 100 is higher than the first surface of the third semiconductor layer 104 facing away from the substrate 100.

It is understood that the steps 121 to 123 may be repeated several times to prepare the third semiconductor layer 104 as shown in fig. 19.

It is clear that the growth of the P-type doped nitride layer in step 122 can be performed by controlling the doping concentration of P-type during the process, so as to realize the third semiconductor layer 104 with single-sided or double-sided graded doping as described in the first embodiment. The specific form of P-type doping is not specifically limited herein.

Alternatively, the third semiconductor layer 104 may be formed by ion implantation in the first semiconductor layer 102 to form the third semiconductor layer 104 as described in the first embodiment or the second embodiment.

In step 130, a second semiconductor layer 103 is deposited on the first semiconductor layer 102, and it is clear that a fourth semiconductor layer 120 may also be deposited on the first semiconductor layer 102 before the second semiconductor layer 103 is formed. Thereby forming a two-dimensional charge carrier gas at the interface of the second semiconductor layer 103 and the fourth semiconductor layer 120, or the first semiconductor layer 102 and the second semiconductor layer 103. The second semiconductor layer 103 may be in direct contact with the fourth semiconductor layer 120, or the second semiconductor layer 103 may be in direct contact with the first semiconductor layer 102.

It is clear that the fourth semiconductor layer 120 may be a nitride channel layer, and the second semiconductor layer 103 may be a nitride barrier layer; or the second semiconductor layer 103 may be a nitride barrier layer and the first semiconductor layer 102 may be a nitride channel layer.

In step 140, a first electrode 106 (source electrode) and a third electrode 107 (drain electrode) having a gas ohmic contact with the two-dimensional charge carriers are formed, and a second electrode 108 (gate electrode) is formed over the first surface of the third semiconductor layer 104. The first electrode 106 and the third electrode 107 are not limited in position, and may be formed directly on the second semiconductor layer or may be formed directly deep into the channel layer, and an exemplary structure is shown in fig. 21.

It is understood that, in step 120, the fifth semiconductor layer 112 may be laterally epitaxially formed on the second insulating layer and the first surface of the seed layer, with the seed layer as a center, as shown in fig. 22. The subsequent selective/lateral epitaxial formation of the fifth semiconductor layer 112 and the third semiconductor layer 104' with the seed layer as the center is the same as the aforementioned formation of the first semiconductor layer 102 and the third semiconductor layer 104, and is not repeated herein. Other structures, such as the first semiconductor layer 102 and the second semiconductor layer 103, may then be formed in sequence in a known manner, and an exemplary structure for protecting the fifth semiconductor layer is shown in fig. 22.

Eighth embodiment

A manufacturing method for manufacturing the semiconductor device of the third embodiment will now be exemplarily described with reference to fig. 23.

Wherein between the steps 130 and 140 of the seventh embodiment, the first insulating layer 105 may be further formed by overall depositing an insulating material on the first surface of the second semiconductor layer or the third insulating layer 109 at the position corresponding to the second electrode 108 by a related process, for example, by an etching process, and the insulating material may be silicon dioxide, silicon nitride, Al₂O₃And the like. The second semiconductor layer may have the first and third insulating layers thereon simultaneously or alternatively.

Ninth embodiment

A manufacturing method for manufacturing the semiconductor device of the fourth embodiment will now be exemplarily described with reference to fig. 24.

There may also be step 150 in the seventh embodiment. In step 150, an etching process is performed on the second surface of the substrate 100 at a position corresponding to the position where the third semiconductor layer 104 is formed, so as to form the through hole 10. The vias reach through the third semiconductor layer 104. Then, the fourth electrode 110 is formed on the third semiconductor layer 104 by a process such as deposition, so that a potential of the third semiconductor layer 104 can be controlled, so that a threshold voltage of the device is stabilized.

Tenth embodiment

A manufacturing method for manufacturing the semiconductor device of the fifth embodiment will now be exemplarily described with reference to fig. 25.

There may also be step 150 in the seventh embodiment. In step 150, the third semiconductor layer 104 is grown in an extending manner along a direction perpendicular to the two-dimensional carrier charge flowing direction, a through hole is formed at a position of the first or second surface of the third semiconductor layer 104 that is not covered by the orthographic projection of the second electrode 108 by etching, and a fourth electrode 110 connected to the third semiconductor layer 104 is formed in the through hole by sputtering or other processes, so that a potential can be controlled, and the threshold voltage of the device can be stabilized.

Eleventh embodiment

A power supply device comprising any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, a transformer, and the like, wherein each of the primary circuit and the secondary circuit includes a switching element, and the switching element includes any one of the semiconductor devices in the above-described embodiments.

Twelfth embodiment

A cellular phone comprising any of the semiconductor devices in the above embodiments. The mobile phone includes a display, a charger, and the like, wherein the charger includes any of the semiconductor devices in the above embodiments.

Thirteenth embodiment

An amplifier which can be used for a power amplifier in the field of a mobile phone base station or the like, the power amplifier may include any of the semiconductor devices in the above embodiments.

While the disclosure has been described with reference to specific embodiments, it will be apparent to those skilled in the art that these descriptions are intended in an illustrative rather than in a limiting sense. Various modifications and alterations of this disclosure will become apparent to those skilled in the art from the spirit and principles of this disclosure, and such modifications and alterations are also within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that the semiconductor device comprises:

a substrate;

a first semiconductor layer formed on the first surface of the substrate;

a second semiconductor layer formed on the first surface of the first semiconductor layer;

the first semiconductor layer has a smaller forbidden band width than the second semiconductor layer;

a first electrode and a third electrode formed on the first or second semiconductor layer, a second electrode formed on the second semiconductor layer;

a third semiconductor layer under the second electrode;

the length range of the third semiconductor layer projected to the substrate is within the length range of the second electrode projected to the substrate, and the third semiconductor layer is a P-type semiconductor layer.

2. The semiconductor device according to claim 1, wherein the substrate is sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3, or single crystal silicon.

3. The semiconductor device according to claim 1 or 2, wherein the first semiconductor layer is an intrinsic nitride semiconductor layer or an unintentionally doped nitride semiconductor layer, and an epitaxial direction of the intrinsic nitride semiconductor layer or the unintentionally doped nitride semiconductor layer parallel to the substrate is a [0001] direction.

4. The semiconductor device according to claim 1, wherein a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and the third semiconductor layer depletes 95% to 100% of the two-dimensional charge carrier gas in at least a partial region below the second electrode region, and does not deplete the two-dimensional charge carrier gas in regions other than the partial region.

5. The semiconductor device according to claim 1, wherein a two-dimensional charge carrier gas is formed between the first semiconductor layer and the second semiconductor layer, and the two-dimensional charge carrier gas corresponding to at least a partial region of the second electrode is lower than 5E +11/cm when the bias voltage of the second electrode is 0²。

6. The semiconductor device according to claim 1 or 4, wherein an epitaxial direction parallel to the substrate of the third semiconductor layer is [0001 [ ]]Direction of transverse extension of

7. The semiconductor device according to claim 6, wherein the first semiconductor layer has a second surface opposite to the first surface of the substrate and has a first surface facing away from the first surface of the substrate, wherein the third semiconductor layer has a second surface opposite to the first surface of the first semiconductor layer and has a first surface facing away from the first surface of the first semiconductor layer, wherein the third semiconductor layer further has a third surface connected to the first and second surfaces of the third semiconductor layer, and wherein the third surface of the third semiconductor layer forms an angle of greater than 30 degrees and less than or equal to 90 degrees with the second surface of the third semiconductor layer.

8. The semiconductor device according to claim 4 or 5, wherein the third semiconductor layer has a length of 0.01 to 10 micrometers and a thickness of 0.01 to 10 micrometers.

9. The semiconductor device according to claim 4 or 5, wherein the third semiconductor layer has a single-layer structure or a plurality of discrete layer structures of 2 or more.

10. The semiconductor device according to claim 9, wherein the plurality of discrete layer structures are discrete layer structures in a vertical substrate direction or discrete layer structures in a parallel substrate direction.

11. The semiconductor device according to claim 9, wherein the discrete layer structures are in close contact with each other or have a space therebetween.

12. The semiconductor device according to claim 4 or 5, wherein the third semiconductor layer is in direct contact with the second semiconductor layer or is spaced from the third semiconductor layer by a certain thickness.

13. The semiconductor device according to claim 1, wherein a fourth semiconductor layer is further provided between the first semiconductor layer and the second semiconductor layer.

14. The semiconductor device according to claim 1, wherein a fifth and/or sixth semiconductor layer is further provided between the first semiconductor layer and the substrate.

15. The semiconductor device of claim 1, further comprising a second insulating layer having an opening formed between the first semiconductor layer and the substrate and a seed layer formed within the opening, the seed layer being located below the first electrode.

16. The semiconductor device according to claim 1, further comprising a first and/or third insulating layer between the second semiconductor layer and the second electrode.

17. The semiconductor device according to claim 1, wherein the third semiconductor layer is connected to a fourth electrode.

18. The semiconductor device according to claim 17, wherein the fourth electrode is an independent electrode or the fourth electrode is a non-independent electrode.

19. The semiconductor device according to claim 18, wherein the substrate has a second surface opposite to the first surface, and wherein the fourth electrode connected to the third semiconductor layer is formed at the second surface of the substrate.

20. The semiconductor device according to claim 18, wherein the third semiconductor layer extends in a direction perpendicular to the two-dimensional charge carrier gas flow, and wherein a fourth electrode connected to the third semiconductor layer is formed at a position not covered by the projection of the second electrode.

21. The semiconductor device according to claim 18, wherein a fourth electrode connected to the third semiconductor layer is formed at a first electrode of the semiconductor device.

22. An electronic device, characterized in that the electronic device comprises a semiconductor device according to any one of claims 1-21.

23. The electronic device of claim 22, wherein the electronic device is a power supply device, a server, a charger, a cell phone, or an amplifier.