CN214315687U - Linear constant current drive circuit and linear constant current system - Google Patents
Linear constant current drive circuit and linear constant current system Download PDFInfo
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- CN214315687U CN214315687U CN202120548168.1U CN202120548168U CN214315687U CN 214315687 U CN214315687 U CN 214315687U CN 202120548168 U CN202120548168 U CN 202120548168U CN 214315687 U CN214315687 U CN 214315687U
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Abstract
The utility model discloses a linear constant current drive circuit and linear constant current system. The circuit comprises a constant current module, an input electrolytic capacitor and a power factor boosting module which is connected between the negative electrode of the input electrolytic capacitor and the ground end in series; the power factor boosting module is used for receiving an input voltage and controlling the current flowing through the power factor boosting module to be a first current value when the input voltage is smaller than a threshold voltage; and when the input voltage is greater than the threshold voltage, controlling the current flowing through the power factor boosting module to be smaller than the first current value. The utility model discloses can improve power factor, and can realize more high-power on the basis that does not increase work load according to the nimble split power factor lift module of circuit needs.
Description
Technical Field
The utility model relates to a power electronics technical field especially relates to a can improve linear constant current drive circuit and linear constant current system of power factor.
Background
With the continuous development of the LED lighting technology, more and more lighting devices favored by people adopt LED lamps due to the characteristics of low power consumption, environmental protection and low radiation. The Power Factor (PF) is an important technical data of power electronic systems, and is a coefficient for measuring the efficiency of power electronic equipment, and more power electronic equipment requires higher power factor. Since the LEDs cannot be connected directly to ac, a corresponding current-limited drive arrangement needs to be provided.
Please refer to fig. 1, which is a schematic diagram of a conventional linear current-limiting driving system. The existing linear current-limiting driving system includes: the LED lamp comprises a rectifying circuit 101, an energy storage capacitor C0, an LED lamp 109 and a constant current source 102. An alternating current power supply AC charges an energy storage capacitor C0 at the positive and negative half cycle peak values of a sine half wave through a rectifying circuit 101; the energy storage capacitor C0 converts the input voltage in the form of sine half-wave into high-voltage direct current to be output to the LED lamp 109, and the voltage at the two ends of the energy storage capacitor C0 is always greater than the voltage at the two ends of the LED lamp 109; the constant current source 102 takes the voltage of the energy storage capacitor C0 exceeding the voltage of the LED lamp 109 to maintain the current of the LED lamp 109 constant. The disadvantage of this linear current limiting method is that the energy storage capacitor C0 is connected in parallel between the rectifying circuit 101 and the ground, which results in serious distortion of the charging current for charging the energy storage capacitor C0 and low power factor. The linear current limiting method also has the problem that the high power factor and the output ripple cannot be compatible: the stroboscopic phenomenon exists when the high power factor is met; or no stroboflash is satisfied, the power factor is lower.
The patent application '201710564306.3 input current-limiting module, linear constant current system and method' proposes a linear constant current system which can realize the improvement of power factor value and the output without ripple, and the principle is as follows: an input current limiting module is connected in series between the output end of the rectifier bridge and the lower polar plate of the input electrolytic capacitor, and the magnitude of the charging current for charging the input electrolytic capacitor is limited by the input current limiting module; meanwhile, an output constant current module is connected in series between the lower pole plate of the input electrolytic capacitor and the load, and the output current output to the load is a constant value through the output constant current module. In the patent application '201710564306.3 input current-limiting module, linear constant current system and method', the input current-limiting module and the output constant current module are a series connection whole circuit, which cannot be separated and flexible enough, and the PF value is limited by the maximum power limit value of the output constant current module, so that higher power cannot be realized; if the PF value needs to be further increased, only a brand new scheme can be replaced, the workload is increased, and the cost is increased.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a linear constant current drive circuit and linear constant current system can realize improving power and export simultaneously because of numerical value and do not have the ripple, and can be according to the nimble split of circuit needs, realize more high-power on the basis that does not increase work load.
In order to achieve the above object, the utility model provides a linear constant current driving circuit, the circuit includes: the constant current module is used for controlling the current flowing through the load; the power factor improving circuit comprises an input electrolytic capacitor and a power factor improving module connected between the negative electrode of the input electrolytic capacitor and the ground end in series, wherein the power factor improving module is used for receiving an input voltage and controlling the current flowing through the power factor improving module to be a first current value when the input voltage is smaller than a threshold voltage; and when the input voltage is greater than the threshold voltage, controlling the current flowing through the power factor boosting module to be smaller than the first current value.
In an embodiment, the branch where the input electrolytic capacitor and the power factor boost module are located is connected in parallel with the branch where the constant current module is located.
In an embodiment, the power factor boost module includes a high power factor driver chip, the high power factor driver chip is provided with a feedback pin and a drain pin, and the high power factor driver chip includes: the compensation control unit, the first current mirror, the second current mirror, the first operational amplifier and the first transistor; the compensation control unit is electrically connected to the drain electrode pin and is electrically connected to the negative electrode of the input electrolytic capacitor through the drain electrode pin so as to receive the input voltage, and the compensation control unit is used for generating a compensation current according to the input voltage; the first current mirror is electrically connected with the compensation control unit and used for receiving the compensation current and generating a first mirror current; the second current mirror is electrically connected with the first current mirror and used for receiving the first mirror current and generating a second mirror current; the positive phase input end of the first operational amplifier is used for receiving a first reference voltage, the negative phase input end of the first operational amplifier is electrically connected with the second current mirror and is electrically connected to the feedback pin through an internal sampling resistor, and the output end of the first operational amplifier is electrically connected with the control end of the first transistor; the first end of the first transistor is electrically connected to the drain pin, and the second end of the first transistor is electrically connected to the feedback pin.
The utility model has the advantages that the power factor value can be improved, the output can be realized without ripples, and the system efficiency is optimized; in the system, the power factor improving module is an independent external circuit and is in parallel connection with the rear-stage constant current module, so that the power factor improving module is hardly influenced by the power of the constant current module and can realize higher power; the power factor promotion module can be flexibly disassembled according to the line requirements, the PF value is promoted on the basis of not increasing the workload, meanwhile, the application line can be simplified, and the line cost is saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of a conventional linear current-limiting driving system;
fig. 2 is a schematic diagram of an architecture of an embodiment of a linear constant current system provided by the present invention;
fig. 3 is a schematic diagram of an architecture of a high power factor driver chip provided by the present invention;
FIG. 4 is a circuit diagram of an embodiment of the high power factor driver chip shown in FIG. 3;
FIG. 5 is a waveform diagram illustrating operation of the system of FIG. 2 during an initial boot phase;
fig. 6 is a schematic diagram of an architecture of another embodiment of the linear constant current system provided by the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise. It will be understood that when an element is referred to as being "coupled" to another element, there are intervening elements present. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
Fig. 2-5 are also shown, in which fig. 2 is a schematic diagram of a structure of an embodiment of a linear constant current system, fig. 3 is a schematic diagram of a structure of a high power factor driver chip, fig. 4 is a circuit diagram of an embodiment of the high power factor driver chip shown in fig. 3, and fig. 5 is a waveform diagram of the system shown in fig. 2 during an initial startup phase.
As shown in fig. 2, the system includes: a rectification circuit 1 and a linear constant current drive circuit 2.
Specifically, the rectifier circuit 1 (composed of 4 rectifier diodes) is electrically connected to the alternating current power supply AC, and is configured to rectify and output the alternating current power supply AC.
The linear constant current driving circuit 2 comprises a constant current module 201, an input electrolytic capacitor EC1 and a power factor boosting module 202. The constant current module 201 is used for controlling the current flowing through the load 9; the constant current module 201 may adopt an existing chip capable of outputting a constant current, and details thereof are not repeated herein. The load 9 may be a LED string. The positive electrode of the input electrolytic capacitor EC1 is electrically connected with the output end of the rectifying circuit 1; the power factor boosting module 202 is connected in series between the negative electrode of the input electrolytic capacitor EC1 and the ground. The alternating current power supply AC is rectified by the rectifying circuit 1 and then input to the input electrolytic capacitor EC1 to charge the input electrolytic capacitor EC 1. The positive electrode of the input electrolytic capacitor EC1 is electrically connected to the load 9, and the input electrolytic capacitor EC1 outputs an output current in the form of a direct current to the load 9. The power factor boosting module 202 is configured to receive an input voltage Vd, compare the input voltage Vd with a threshold voltage Vth, and control a current flowing through the power factor boosting module 202 to be a first current value Ith when the input voltage Vd is smaller than the threshold voltage Vth; when the input voltage Vd is greater than the threshold voltage Vth, the current flowing through the power factor boosting module 202 is controlled to be less than the first current value Ith. The current flowing through the power factor boosting module 202 is instantaneous, and the first current value Ith is a plateau current value reached before the input voltage Vd reaches the threshold voltage Vth. It should be noted that, due to the disturbance in the circuit, the current flowing through the power factor boost module 202 may fluctuate; the current flowing through the power factor boosting module 202 may jump before reaching the first current value Ith, and such jump is not considered within the scope of the present application.
That is, the magnitude of the charging current for charging the input electrolytic capacitor EC1 is limited by the power factor boost module 202 to correct the distortion of the input current signal of the AC power source AC, so as to adjust the current supplied to the load 9, thereby increasing the power factor value of the linear constant current system. By setting the power factor boosting module 202, the power factor value of the linear constant current system can be increased to be greater than or equal to 0.7.
In a further embodiment, when the input voltage Vd is greater than the threshold voltage Vth, the current flowing through the power factor boosting module 202 is controlled to decrease with the increase of the input voltage Vd, and the corresponding saddle-shaped voltage current waveform is shown in fig. 5.
In a further embodiment, the branch where the input electrolytic capacitor EC1 and the power factor boost module 202 are located is connected in parallel with the branch where the constant current module 201 is located. In the system, the power factor boost module 202 is an independent external circuit, and is in parallel connection with the rear-stage constant current module 201, so that the power factor boost module is hardly influenced by the power of the constant current module 201, and can realize higher power; the power factor improving module 202 can be flexibly disassembled according to the line requirements, the power factor value is improved on the basis of not increasing the workload, the application line can be simplified, and the line cost is saved.
In a further embodiment, the power factor boosting module 202 includes a high power factor driver chip. Specifically, as shown in fig. 3, the high power factor driving chip is provided with a feedback pin CS and a DRAIN pin DRAIN, and the high power factor driving chip is further provided with a ground pin GND. The high power factor driving chip internally comprises: the compensation control unit 21, the first current mirror 22, the second current mirror 23, the first operational amplifier OP1, and the first transistor Q1. By manufacturing the internal circuit of the power factor boost module 202 in the same high power factor driving chip, the application circuit is simplified, and the circuit cost is saved.
Specifically, the compensation control unit 21 is electrically connected to the DRAIN pin DRAIN and to the negative electrode of the input electrolytic capacitor EC1 through the DRAIN pin DRAIN to receive the input voltage Vd; the compensation control unit 21 is configured to generate a compensation current I1 according to the input voltage Vd. The first current mirror 22 is electrically connected to the compensation control unit 21, and is configured to receive the compensation current I1 and generate a first mirror current I2. The second current mirror 23 is electrically connected to the first current mirror 22, and is configured to receive the first mirror current I2 and generate a second mirror current I3. The non-inverting input terminal of the first operational amplifier OP1 is configured to receive a first reference voltage Vref1, the inverting input terminal thereof is electrically connected to the second current mirror 23 and is electrically connected to the feedback pin CS through an internal sampling resistor R4, and the output terminal thereof is electrically connected to the control terminal of the first transistor Q1. A first terminal of the first transistor Q1 is electrically connected to the DRAIN pin DRAIN, and a second terminal thereof is electrically connected to the feedback pin CS.
In a further embodiment, as shown in fig. 4, the compensation control unit 21 includes: the voltage-dividing subunit, the second operational amplifier OP2, the second transistor Q2 and the compensation resistor R3. The input end of the voltage-dividing subunit is electrically connected to the DRAIN pin DRAIN, and the output end of the voltage-dividing subunit is electrically connected to the negative phase input end of the second operational amplifier OP2, so as to divide the input voltage Vd received from the DRAIN pin and input the divided voltage to the second operational amplifier OP 2. The non-inverting input terminal of the second operational amplifier OP2 is used for receiving a start reference voltage Vref0, and the output terminal thereof is electrically connected to the control terminal of the second transistor Q2. The second transistor Q2 has a first terminal for receiving a power voltage VDD, and a second terminal electrically connected to the non-inverting input terminal of the second operational amplifier OP2 and electrically connected to the compensation resistor R3. The compensation resistor R3 receives a reference voltage V0 and is electrically connected to the first current mirror 22.
And controlling the current flowing through the high power factor driving chip according to the divided voltage Vb obtained by the input voltage Vd and the reference voltage V0. The divided voltage Vb varies with the input voltage Vd, and the starting reference voltage Vref0 represents the positive terminal voltage of the second operational amplifier OP 2. When the divided voltage Vb is greater than or equal to the reference voltage V0, the second operational amplifier OP2 starts to operate, the initial reference voltage Vref0 starts to follow the variation of the divided voltage Vb (Vref ═ Vb), and the compensation current I1 starts to be generated; before the second operational amplifier OP2 starts operating, Vref0 becomes V0.
Before the second operational amplifier OP2 starts operating (Vref0 ═ V0), I1 ═ I2 ═ I3 ═ 0; at this time, the current I0 flowing through the first transistor Q1 is related to the first reference voltage Vref1 and the external sampling resistor Rcs. After the second operational amplifier OP2 starts operating, and when the divided voltage Vb is greater than the reference voltage V0(Vref0> V0), I3 ═ I2 ═ I1 (here, the first current mirror, the second current mirror, and the third current mirror are all 1:1 ratio copies, and may be set to other ratios according to actual needs); the current I0 flowing through the first transistor Q1 is related to the external sampling resistor Rcs and the internal sampling resistor R4.
Alternatively, as shown in fig. 4, the voltage dividing subunit includes two voltage dividing resistors R1, R2 connected in series; one end of the voltage dividing resistor R1 is electrically connected to the DRAIN pin DRAIN, one end of the voltage dividing resistor R2 is electrically connected to the ground pin GND, and a common end of the voltage dividing resistors R1 and R2 serves as an output end of the voltage dividing subunit and is electrically connected to a negative phase input end of the second operational amplifier OP 2. In other embodiments, the voltage divider subunit may also be disposed outside the high power factor driving chip to directly obtain power from the bus voltage Vbus.
Optionally, as shown in fig. 4, the first current mirror 22 is a current mirror formed by using an N-channel MOS transistor, and the second current mirror 23 is a current mirror formed by using a P-channel MOS transistor.
Optionally, as shown in fig. 4, the first transistor Q1 is an N-channel MOS transistor, and is turned on at a high level; the second transistor Q2 is a P-channel MOS transistor and is turned on at a low level. It should be noted that the types of the first transistor Q1, the second transistor Q2, and the transistors in the first current mirror 22 and the second current mirror 23 can be selected according to design requirements, and the connection mode of the operational amplifier is adjusted according to the type of the selected transistor.
Referring to fig. 3, specifically, the feedback pin CS of the high power factor driver chip is grounded through an external sampling resistor Rcs, so as to sample the charging current of the input electrolytic capacitor EC1 through the external sampling resistor Rcs to obtain a sampling voltage Vcs, and feed back the sampling voltage Vcs to the inverting input terminal of the first operational amplifier OP1 of the high power factor driver chip. Wherein the magnitude of the charging current can be adjusted by adjusting the magnitude of the resistance value of the external sampling resistor Rcs.
With reference to fig. 2 to fig. 4, the operating principle of the high power factor driving chip is as follows: the input voltage Vd received from the DRAIN pin DRAIN is divided by the voltage dividing resistors R1 and R2 to obtain a divided voltage Vb, and the divided voltage Vb is input to the negative input terminal of the second operational amplifier OP 2. By sampling the drain terminal of the second transistor Q2 and feeding back the drain terminal to the negative terminal of the second operational amplifier OP2, the second operational amplifier OP2 and the second transistor Q2 together form a unit negative feedback circuit, and the positive terminal of the second operational amplifier OP2 is the negative terminal of the unit negative feedback circuit. According to the principle of virtual short-break of the operational amplifier, when the second operational amplifier OP2 starts to operate, the initial reference voltage Vref0 follows the divided voltage Vb (Vref0 is Vb); the upper end of the compensation resistor R3 is a starting reference voltage Vref0, and the lower end is a reference voltage V0. When Vref0> V0 (i.e., Vb > V0), the second transistor Q2 is turned on, and a current flows through the compensation resistor R3, thereby generating a compensation current I1. Compensation (here, negative compensation) is started when the input voltage Vd is greater than the voltage threshold Vth (specifically, the divided voltage Vb is made greater than the reference voltage V0). The compensation current I1 generated by the compensation control unit 21 makes the first current mirror 22 start to operate (N-channel MOS transistor is turned on at high level), so as to generate a first mirror current I2; the first mirror current I2 makes the second current mirror 23 start to work (P-channel MOS transistor, low level conducting), thereby generating a second mirror current I3; the second mirror current I3 flows through the sampling resistor R4 to generate a first voltage V1(V1 ═ I3 × R4), and the current flowing through the first transistor Q1 generates a sampling voltage Vcs across the external sampling resistor Rcs; therefore, the feedback voltage VG fed back to the negative input terminal of the first operational amplifier OP1 is: VG is Vcs + I3 × R4. As can be seen from the principle of virtual short and virtual disconnection of the operational amplifier, the feedback voltage VG formed at the inverting input terminal of the first operational amplifier OP1 is: VG-Vref 1-Vcs + V1-Vcs + I3-R4, i.e., Vcs-Vref 1-I3-R4; when the feedback voltage VG is greater than the first reference voltage Vref1, the first operational amplifier OP1 is caused to output a low level, so that the first transistor Q1 is turned off; when the second mirror current I3 current is zero, Vcs is Vref 1. When the second mirror current I3 rises, the sampling voltage Vcs generated on the external sampling resistor Rcs by the current flowing through the first transistor Q1 decreases. When the input voltage Vd is smaller than the voltage threshold Vth, no current flows through the compensation resistor R3.
Taking the first current mirror, the second current mirror and the third current mirror as an example of 1:1 ratio replication, when Vref0> V0, I3 ═ I2 ═ I1 ═ I0-V0)/R3 ═ ((R2/(R1+ R2)) × Vd-V0)/R3 ═ K1 Vd-K2 ═ V0, where K1 ═ R2/((R1+ R2) × R3), K2 ═ R8291/R3; the current I0 ═ Vcs/Rcs ═ Vref1-I3 ═ R4)/Rcs ═ Vref1+ K2 ═ R4 × V0-K1 × R4 × Vd)/Rcs flowing through the first transistor Q1, and this formula corresponds to the saddle-shaped voltage-current waveform shown in fig. 5. Wherein I is a current flowing through the power factor boosting module 202 (i.e. I0), and Vd is a voltage input to the power factor boosting module 202 (at the initial startup stage, Vd may be represented by a bus voltage Vbus); vth is a threshold voltage, and Ith refers to a plateau current value reached before the input voltage Vd reaches the threshold voltage Vth. When the input voltage gets power from the DRAIN pin DRAIN, the saddle-shaped voltage mainly appears at the initial startup stage due to the fact that the DRAIN pin DRAIN voltage is lower in a steady state, the overshoot phenomenon can be reduced, and the system stability is improved.
With reference to fig. 3, optionally, the high power factor driver chip further includes: a reference voltage generating unit 24. The reference voltage generating unit 24 is electrically connected between the compensation control unit 21 and the first current mirror 22, generates the reference voltage V0, and supplies the reference voltage V0 to the compensation control unit 21.
Specifically, as shown in fig. 4, the reference voltage generating unit 24 includes: a third current mirror 241 and a third operational amplifier OP 3. The third current mirror 241 is electrically connected to the first current mirror 22, and is configured to receive the power supply voltage VDD to provide a bias current for the first current mirror 22. The non-inverting input terminal of the third operational amplifier OP3 is electrically connected to the third current mirror and the compensation resistor R3 of the compensation control unit 21, the inverting input terminal of the third operational amplifier OP3 is used for receiving a second reference voltage Vref2, and the output terminal thereof is electrically connected to the first current mirror 22. Accordingly, a reference voltage V0 is formed at the non-inverting input terminal of the third operational amplifier OP3 and is applied to the lower end of the compensation resistor R3. The third current mirror 241 is a current mirror formed by P-channel MOS transistors. It should be noted that, in other embodiments, the reference voltage V0 may also be provided to the compensation control unit 21 by an external component.
Specifically, the drain of the seventh transistor Q7 in the third current mirror 241 is used for receiving the power supply voltage VDD, and the source thereof is electrically connected to the drain of the third transistor Q3 in the first current mirror 22; when the second transistor Q2 is not turned on, the seventh transistor Q7 provides a bias current to the third transistor Q3, so that the two transistors Q3 and Q4 of the first current mirror 22 are always in a conductive operation state. By sampling the drain terminal of the third transistor Q3 and feeding back to the positive terminal of the third operational amplifier OP3, the third operational amplifier OP3 and the third transistor Q3 constitute a unit buffer, i.e., the reference voltage V0 is equal to the second reference voltage Vref2 (V0 — Vref 2).
Preferably, the drain of an eighth transistor Q8 of the third current mirror 241, which is common-gate with the seventh transistor Q7, is used for receiving the power supply voltage VDD, and the source thereof is electrically connected to the drain of a fourth transistor Q4 of the first current mirror 22, which is common-gate with the third transistor Q3; when the second transistor Q2 is turned off, the eighth transistor Q8 provides a bias current to the fourth transistor Q4. If the eighth transistor Q8 is not provided, the bias current of the fourth transistor Q4 is generated from the fifth transistor Q5 in the second current mirror 23; once the bias current is generated by the fifth transistor Q5, the sixth transistor Q6 of the second current mirror 23, which is co-gated with the fifth transistor Q5, also generates a corresponding bias current; this may cause the divided voltage Vb generated by the two voltage dividing resistors R1 and R2 not to be higher than the reference voltage V0, and the sampling resistor R4 already generates a voltage due to the bias current of the sixth transistor Q6, so as to start to enter into compensation, which is not needed by the chip design. The chip design requirements of the application are as follows: when the divided voltage Vb obtained by dividing the input voltage Vd received by the DRAIN pin DRAIN by the two voltage dividing resistors R1 and R2 is greater than or equal to the reference voltage V0, the compensation state is started; when the divided voltage Vb is equal to the reference voltage V0, the state jumps, and the chip starts to work. The provision of the eighth transistor Q8 prevents the chip from entering the compensation state prematurely.
In the high power factor driving chip according to this embodiment, when the input voltage Vd received from the DRAIN pin DRAIN is greater than or equal to the voltage threshold Vth (specifically, the divided voltage Vb is greater than or equal to the reference voltage V0), the compensation is started. That is, the high power factor driver chip may control the current flowing through the high power factor driver chip according to the level of the input voltage Vd received from the DRAIN pin DRAIN, and limit the magnitude of the charging current charging the input electrolytic capacitor EC1 to correct the distortion of the input current signal of the AC power supply AC, so as to adjust the current provided to the back-end load, thereby improving the power factor.
In a further embodiment, during the initial power-on phase, the waveform of the current flowing through the power factor boosting module 202 is saddle-shaped, and the current flowing through the power factor boosting module 202 at the peak of the input voltage Vd is the minimum, and the operating waveform diagram of the system during the initial power-on phase is shown in fig. 5. Since the high power factor driver chip of the power factor boost module 202 is electrically connected to the negative terminal of the input electrolytic capacitor EC1, the input electrolytic capacitor EC1 is empty during the initial power-on (cold power-on) phase, so the input voltage Vd is equal to the bus voltage Vbus. When the input voltage Vd is greater than the threshold voltage Vth, controlling the current flowing through the power factor boosting module 202 to decrease as the input voltage Vd increases; at the peak of the input voltage Vd, the current I0 flowing through the first transistor Q1 is minimal.
With reference to fig. 2, in a further embodiment, the linear constant current driving circuit 2 further includes a switching tube electrically connected between the DRAIN pin DRAIN of the high power factor driving chip of the power factor boost module 202 and the ground; the switch tube is turned off when the input electrolytic capacitor EC1 is charged and is turned on when the input electrolytic capacitor EC1 is discharged. Namely, the switch tube is used to provide a current path for the input electrolytic capacitor EC1 to discharge the load 9. Optionally, the switching tube is a diode D0, a cathode of the diode D0 is electrically connected to the DRAIN pin DRAIN, and an anode of the diode D0 is electrically connected to the ground.
In the system shown in this embodiment, during normal operation, the charging loop of the input electrolytic capacitor EC1 is: flows out from the negative electrode of the input electrolytic capacitor EC1, flows into the high power factor driving chip through the DRAIN pin DRAIN of the high power factor driving chip, and flows into the ground terminal. The discharge circuit of the input electrolytic capacitor EC1 is: flows out from the negative pole and the positive pole of the input electrolytic capacitor EC1, is provided for the load 9, and forms a loop to the negative pole of the input electrolytic capacitor EC1 through a ground terminal and a diode D0.
The system shown in the embodiment can improve the power factor value, realize output without ripples and optimize the system efficiency; in the system, the power factor improving module is an independent external circuit and is in parallel connection with the rear-stage constant current module, so that the power factor improving module is hardly influenced by the power of the constant current module and can realize higher power; the power factor promotion module can be flexibly disassembled according to the line requirements, the power factor value is promoted on the basis of not increasing the workload, meanwhile, the application line can be simplified, and the line cost is saved.
Please refer to fig. 6, which is a schematic diagram of a linear constant current system according to another embodiment of the present invention. As shown in fig. 6, the difference from the embodiment shown in fig. 2 is that in this embodiment, the linear constant current driving circuit 2 further includes a charging control resistor Rd, and the charging control resistor Rd is electrically connected between the DRAIN pin DRAIN and the feedback pin CS of the high power factor driving chip of the power factor boosting module 202; the charging control resistor Rd is used for providing a current path for charging the input electrolytic capacitor EC1 in the initial starting stage of the system.
Research shows that when the system shown in fig. 2 is in a hot state, the high-power-factor driving chip starts to work as soon as being powered on, and the LED lamp beads serving as loads are normally lightened. However, when the high-power-factor driver chip is turned on for the first time in a cold state, the input electrolytic capacitor EC1 is empty, so that the input voltage Vd received by the DRAIN pin DRAIN of the high-power-factor driver chip is too high; because the high power factor driving chip is provided with a built-in compensation circuit, the compensation circuit enables the voltage of the inverting input end of the first operational amplifier OP1 of the high power factor driving chip to be larger than the voltage of the non-inverting input end of the first operational amplifier OP1 of the high power factor driving chip, the first transistor Q1 of the high power factor driving chip is not turned on in time when the high power factor driving chip is started for the first time in a cold state; only when the input voltage Vd drops to a certain value, the first operational amplifier OP1 is inverted, and the first transistor Q1 is turned on slowly. Therefore, when the LED lamp is in a cold state with a duty ratio of 1%, and the first transistor Q1 of the high-power-factor driving chip starts to work after 2-3S of starting, the bus voltage Vbus is pulled down instantly, so that the LED lamp bead is dark and then bright. The thermal state referred to herein is: after the first power-on is completed, the second power-on is immediately carried out after the power-off; the cold state is: the system is initially started or is started again after being powered off for a certain time.
In order to solve the problem that the LED lamp bead is dark and brighter again in the cold start-up stage, in this embodiment, a charging control resistor Rd is introduced between the DRAIN pin DRAIN and the feedback pin CS of the high power factor driver chip, so as to provide a current path for charging the input electrolytic capacitor EC1 when the system is initially started. The working principle is as follows: in a cold starting stage, the high-power-factor driving chip enters voltage compensation because the input voltage Vd received by the DRAIN pin DRAIN is too high, the voltage of the inverting input end of the first operational amplifier OP1 is larger than that of the non-inverting input end thereof, the first transistor Q1 is not turned on in time and cannot pass through a current stage, a charging current loop input into the electrolytic capacitor charging EC1 is completed by the charging control resistor Rd, and the phenomenon that the LED lamp bead is dark and then bright does not occur. That is, in the cold boot stage of the system, the charging loop of the input electrolytic capacitor EC1 is: flows out from the negative electrode of the input electrolytic capacitor EC1, and flows into the ground end through the charging control resistor Rd and the external sampling resistor Rcs. In the normal working stage of the system, the current flowing through the charging control resistor Rd is small in the stable working state of 100% duty ratio or the stable working state of 1% duty ratio, and the influence on the system is small.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. A linear constant current drive circuit, the circuit comprising:
the constant current module is used for controlling the current flowing through the load;
the power factor improving circuit comprises an input electrolytic capacitor and a power factor improving module connected between the negative electrode of the input electrolytic capacitor and the ground end in series, wherein the power factor improving module is used for receiving an input voltage and controlling the current flowing through the power factor improving module to be a first current value when the input voltage is smaller than a threshold voltage; and when the input voltage is greater than the threshold voltage, controlling the current flowing through the power factor boosting module to be smaller than the first current value.
2. The circuit of claim 1, wherein when the input voltage is greater than the threshold voltage, controlling the current through the power factor boosting module to decrease as the input voltage increases.
3. The circuit of claim 1, wherein the branch in which the input electrolytic capacitor and the power factor boosting module are located is connected in parallel with the branch in which the constant current module is located.
4. The circuit of claim 1, wherein the power factor boosting module comprises a high power factor driving chip, a feedback pin and a drain pin are disposed on the high power factor driving chip, and the high power factor driving chip internally comprises:
the compensation control unit is electrically connected to the drain electrode pin and the cathode of the input electrolytic capacitor through the drain electrode pin so as to receive the input voltage, and the compensation control unit is used for generating a compensation current according to the input voltage;
the first current mirror is electrically connected with the compensation control unit and used for receiving the compensation current and generating a first mirror current;
the second current mirror is electrically connected with the first current mirror and is used for receiving the first mirror current and generating a second mirror current;
the positive phase input end of the first operational amplifier is used for receiving a first reference voltage, the negative phase input end of the first operational amplifier is electrically connected with the second current mirror and is electrically connected with the feedback pin through an internal sampling resistor, and the output end of the first operational amplifier is electrically connected with the control end of a first transistor;
the first end of the first transistor is electrically connected to the drain pin, and the second end of the first transistor is electrically connected to the feedback pin.
5. The circuit of claim 4, wherein the compensation control unit comprises: the voltage division subunit, the second operational amplifier, the second transistor and the compensation resistor;
the input end of the voltage-dividing subunit is electrically connected to the drain pin, and the output end of the voltage-dividing subunit is electrically connected to the negative-phase input end of the second operational amplifier, so that the input voltage received from the drain pin is divided and then is input to the second operational amplifier;
the positive phase input end of the second operational amplifier is used for receiving an initial reference voltage, and the output end of the second operational amplifier is electrically connected with the control end of the second transistor;
the first end of the second transistor is used for receiving a power supply voltage, and the second end of the second transistor is electrically connected with the non-inverting input end of the second operational amplifier and the first end of the compensation resistor;
the second end of the compensation resistor is used for receiving a reference voltage and is electrically connected to the first current mirror.
6. The circuit of claim 5, wherein the high power factor driver chip interior further comprises: a reference voltage generating unit;
the reference voltage generating unit is electrically connected between the compensation control unit and the first current mirror, is used for generating the reference voltage, and is provided to the compensation control unit.
7. The circuit of claim 6, wherein the reference voltage generation unit comprises:
the third current mirror is electrically connected with the first current mirror and used for receiving the power supply voltage and further providing bias current for the first current mirror;
a positive phase input end of the third operational amplifier is electrically connected to the third current mirror and the compensation resistor, an inverted phase input end of the third operational amplifier is used for receiving a second reference voltage, and an output end of the third operational amplifier is electrically connected to the first current mirror.
8. The circuit of claim 4,
the feedback pin is grounded through an external sampling resistor, so that the charging current on the input electrolytic capacitor is sampled through the external sampling resistor to obtain a sampling voltage, and the sampling voltage is fed back to the inverting input end of the first operational amplifier;
the high power factor driving chip controls the current flowing through the first transistor according to the input voltage received from the drain pin and the sampling voltage, so that the charging current on the input electrolytic capacitor is limited.
9. The circuit of claim 4, wherein the circuit further comprises a switching tube;
the switch tube is electrically connected between the drain electrode pin and the ground end, and the switch tube is cut off when the input electrolytic capacitor is charged and is switched on when the input electrolytic capacitor is discharged.
10. The circuit of claim 4, wherein the circuit further comprises a charge control resistor;
the charging control resistor is electrically connected between the drain pin and the feedback pin and used for providing a current path for charging the input electrolytic capacitor when the circuit is initially started.
11. The circuit of claim 1, wherein during an initial power-on phase, a current waveform flowing through the power factor boosting module is saddle-shaped, and a current flowing through the power factor boosting module is minimal at a peak of the input voltage.
12. A linear constant current system, the system comprising a rectifying circuit; characterized in that the system further comprises:
the linear constant current driving circuit is electrically connected with the rectifying circuit; the linear constant current driving circuit is the linear constant current driving circuit according to any one of claims 1 to 11.
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| CN202120548168.1U CN214315687U (en) | 2021-03-16 | 2021-03-16 | Linear constant current drive circuit and linear constant current system |
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| CN202120548168.1U CN214315687U (en) | 2021-03-16 | 2021-03-16 | Linear constant current drive circuit and linear constant current system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114205963A (en) * | 2021-12-21 | 2022-03-18 | 欧普照明股份有限公司 | Linear LED driving circuit and driving method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114205963A (en) * | 2021-12-21 | 2022-03-18 | 欧普照明股份有限公司 | Linear LED driving circuit and driving method |
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