CN214279942U - Semiconductor package - Google Patents

Abstract

The utility model relates to a semiconductor package. According to an embodiment of the present invention, a semiconductor package includes: a semiconductor die having a front surface, a back surface opposite the front surface, and a sidewall connecting the front surface and the back surface; and a passivation layer on the sidewall, wherein the passivation layer comprises an arc profile, a thinnest portion of the arc profile being adjacent to a middle of the sidewall.

Description

Semiconductor package

Technical Field

The present invention relates generally to semiconductor packaging technology, and more particularly to semiconductor die including sidewall passivation layer protection and formation and separation techniques thereof.

Background

With the development of semiconductor technology and the increasing integration level, the number of device units is increased sharply and the size is reduced, so that the adverse effect of particle impurities generated in the manufacturing process on the package manufacturing is increasingly highlighted. In particular, during semiconductor packaging, particles (e.g., silicon chips) generated during the die dicing step may stay in the cut regions of the dicing streets and loosen during the process of picking up individual dies (die shots) from the adhesive film during die stacking, and may further fall on the surface of a protection layer (e.g., non-conductive film (NCF), non-conductive paste (NCP), Capillary Underfill (CUF), Mold Underfill (MUF), etc.) adjacent to the dies on the package structure.

Particle contamination may occur in various Non-zero bond line structures (Non-zero bond line structures), such as package structures with NCF, MUF, NCP, etc., and may also occur in zero-zero (or Near-zero) bond line structures (Near-zero bond line structures), such as Hybrid bonding (Hybrid bonding). In particular, at the interface of the hybrid bonding, only 1 μm of particles can create a void of about 100 μm during the bonding process, which disadvantageously leads to delamination and ultimately to hybrid bonding failure. Furthermore, the particles may impact the die during semiconductor packaging to form micro-cracks, which adversely affect the internal circuit layers, which can also lead to reliability problems and reduced product yield. Furthermore, the edges of the die are not effective at preventing contaminants such as copper from diffusing through the silicon in the absence of the necessary protection. Therefore, particle contamination is becoming one of the main factors causing reliability failure of open interconnections and resulting in reduction of product yield.

In view of the above, there is a strong need in the art to provide improved solutions to the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

In view of the foregoing, the present disclosure provides a semiconductor package that provides a semiconductor die structure including sidewall passivation layer protection and methods of making and using the same.

According to an embodiment of the present invention, a semiconductor package includes: a semiconductor die having a front surface, a back surface opposite the front surface, and a sidewall connecting the front surface and the back surface; and a passivation layer on the sidewall, wherein the passivation layer comprises an arc profile, a thinnest portion of the arc profile being adjacent to a middle of the sidewall.

According to a further embodiment of the present invention, a thickness of the passivation layer in the semiconductor package adjacent to the top or bottom of the sidewall is greater than a thickness of the passivation layer adjacent to the middle portion of the sidewall.

According to another embodiment of the present invention, the passivation layer in the semiconductor package further comprises an irregular profile adjacent to the top or the bottom of the sidewall.

According to another embodiment of the present invention, the passivation layer in the semiconductor package further covers the back surface of the semiconductor die.

According to another embodiment of the present invention, the passivation layer in the semiconductor package includes a nitride, an oxide, an oxynitride, a silicate, or a combination thereof.

According to another embodiment of the present invention, the thickest part of the passivation layer in the semiconductor package is less than ten times the thickness of the semiconductor die.

According to another embodiment of the present invention, the thickness of the semiconductor die in a semiconductor package is in a range from about 10 μm to about 50 μm.

According to another embodiment of the present invention, the semiconductor package further comprises a carrier plate, the carrier plate being connected to the semiconductor die by electrical connections.

According to a further embodiment of the present invention, the front surface of the semiconductor die in a semiconductor package includes a hybrid bonding layer.

According to another embodiment of the present invention, a semiconductor package further comprises a through hole electrically connecting the front surface and the back surface of the semiconductor die.

Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the invention.

Drawings

FIG. 1 shows a schematic representation of particle contamination affecting bonding in the prior art.

Fig. 2 to 10 show a semiconductor packaging method according to an embodiment of the present invention.

Fig. 11 to 16 show a semiconductor packaging method according to another embodiment of the present invention.

Fig. 17 to 20 show an embodiment of a semiconductor package obtained according to the embodiment of fig. 10 or 16.

Fig. 21 to 23 are corresponding schematic views of the semiconductor package shown in fig. 17 to 19 after being bonded to a carrier.

Fig. 24 is a schematic diagram showing two semiconductor packages of fig. 20 after hybrid bonding.

Detailed Description

For a better understanding of the spirit of the invention, some preferred embodiments of the invention will be described in detail below.

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the invention be constructed or operated in a particular orientation.

Various embodiments of the present invention are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. One skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the invention.

FIG. 1 shows a schematic representation of particle contamination affecting bonding in the prior art. As shown in fig. 1, two semiconductor dies (100) respectively located above and below are placed opposite to each other, each semiconductor die (100) includes a plurality of Through Silicon Vias (TSVs) (101) to be respectively connected to corresponding pads (102), the pads (102) of the two semiconductor dies (100) are electrically connected through a conductive material (103), wherein a gap between the pads (102) and the conductive material (103) is filled with an insulating material (e.g., NCF) (104).

As shown in fig. 1, during the semiconductor packaging process, the die cutting step may generate particles (105), such as silicon debris, and the particles (105), once present, are prone to random movement between package interfaces, thereby scratching or cutting the conductive material (103), forming a damaged conductive material (103'), thereby causing electrical connection failure and directly affecting product yield.

Fig. 2 to 10 show a semiconductor packaging method according to an embodiment of the present invention. As shown in fig. 2, a device wafer (200) has formed therein a plurality of dies (not shown) waiting to be diced and packaged. The device wafer (200) has a front surface (200') and a back surface (200 "), the front surface (200') facing upward and the back surface (200") facing downward and opposite the front surface (200 '). The front surface (200') of the device wafer (200) is an active surface.

As shown in fig. 3, the device wafer (300) is etched using, for example, but not limited to, a dry etching process to etch scribe lines (301) between a plurality of dies (not shown) within the device wafer (300). The scribe line trench 301 may have a width 302 and a depth 303, and the ratio of the depth 303 to the width 302 may also be referred to as the aspect ratio of the scribe line trench 301. In one embodiment, the dry etch may include plasma cutting and laser cutting to etch the scribe line trenches 301. In one embodiment, the aspect ratio of the scribe line trench 301 may be between 1 and 10, which facilitates the closing or pinching off of the passivation layer on the scribe line trench 301 with conventional deposition processes.

Next, as shown in fig. 4, a deposition process is performed on the device wafer (400) to form a passivation layer (401) on the front surface of the device wafer (400) and the bottom surfaces and sidewalls of the scribe line grooves. As an example, the deposition process to form the passivation layer 401 may include, but is not limited to, low temperature chemical vapor deposition, and the passivation layer 401 may be any passivation material including SiN, SiO, silicates, such as Tetraethoxysilane (TEOS), and the like.

During the deposition process, the passivation layer material can automatically close at the top of the scribe line trench (also referred to as a pinch-off effect) as long as the aspect ratio of the scribe line trench is sufficiently large, thereby forming a bridge of passivation layer material at the top that, together with passivation layer material deposited on the bottom and both sidewalls of the scribe line trench, encloses a hole (402), the hole (402) not containing any passivation layer material therein. It should be understood that the shape of the holes 402 is not limited to the generally elliptical shape shown in fig. 4, but may take any regular or irregular shape due to variations in process conditions.

Then, as shown in fig. 5, the front surface of the device wafer (500) is polished using a Polishing process including, for example, Chemical Mechanical Polishing (CMP) to at least partially remove the passivation layer on the front surface, thereby exposing electrical connection regions (e.g., aluminum pads) on the front surface of the wafer for subsequent output terminal preparation.

As shown in fig. 6, the device wafer (600) after the front surface polishing is turned 180 ° so that its front surface faces downward and is bonded to the carrier wafer (604) via the adhesive (603), so that the carrier wafer (604) provides mechanical support for the device wafer (600) in the subsequent process. At this time, the passivation layer 601 and the hole 602, which have been formed in the device wafer 600, are in contact with the adhesive 603.

Next, as shown in fig. 7, the back surface of the device wafer 700 is polished until the passivation layer 701 is exposed, and the holes 702 are still inside the passivation layer 701. The front surface of the device wafer (700) is bonded to the carrier wafer (704) through the adhesive (703) throughout the back surface grinding process, so the device wafer (700) is always subjected to the grinding process under mechanical support of the carrier wafer (704) without damage.

After the polishing process is completed, the carrier wafer 704 and the adhesive 703 may be removed, leaving the device wafer 800 as shown in fig. 8. To this end, the device wafer (800) is composed of a plurality of cut dies and a passivation layer (801) for connecting the dies, wherein the passivation layer (801) includes holes (802). In fig. 8, the spaced die and passivation layer may also be collectively referred to as a die link (80). The die chain (80) may then be sent to an assembly line and mounted to a carrier tape for subsequent die detachment.

As shown in fig. 9, a die paddle (90) comprised of a device wafer (900) containing dies and a passivation layer (901) is disposed on an adhesive tape (903). Due to the fact that the passivation layer (901) between the dies internally comprises the holes (902), the dies are actually provided with weak mechanical connection only by the passivation materials on the top and the bottom of the passivation layer (901), and the passivation layer (901) connection between the dies can be easily broken once a proper external force is applied, so that the dies can be easily disassembled.

Meanwhile, the side wall of the detached bare chip can still be protected by the residual passivation layer (901) so as to prevent the pollutants such as copper from diffusing into the bare chip through the side wall of the bare chip. In one embodiment, the adhesive tape (903) can be forced to be deformed in a stretching way by performing stretching on the pull handles (905) at two ends of the adhesive tape (903), and tensile stress is transferred to the die chain belt (90), so that the passivation layer (901) between the dies is broken along the weak part of the hole (902), and finally the complete detachment of each die is completed. It should be understood that the pull handle (905) is not necessary or may be replaced by other means.

The die after the completion of the detachment is shown in fig. 10. In fig. 10, the individual dies in the die chain (100) are separated from each other to form a gap (1005), and the broken passivation layer (1004) can still be attached to the sidewalls of the dies to continue to provide additional protection to the die sidewalls.

Fig. 11 to 16 show a semiconductor packaging method according to another embodiment of the present invention. As shown in fig. 11, a device wafer (1101) has formed therein a plurality of dies (not shown) waiting to be diced and packaged. The device wafer (1101) has a front surface (1100') and a back surface (1100 "). The front surface (200') of the device wafer (200) is an active surface. Unlike the configuration of the embodiment of fig. 2 in which the front surface (200') faces upward, the front surface (1100') of the embodiment of fig. 11 faces downward. Correspondingly, its back surface (1100 ") is facing upwards and opposite to the front surface (1100'). Due to the back-up placement, the embodiment of fig. 11 eliminates the need to turn the device wafer 180 ° and the back-surface grinding process, thereby further simplifying the process and reducing the manufacturing cost.

Still referring to fig. 11, the device wafer (1101) may undergo a wafer thinning process from its back surface (1100 "), such as thinning the device wafer (1101) to below 100 microns, such as 80 microns or 50 microns. In some embodiments of the package structure having through-silicon vias (TSVs), chemical mechanical polishing and/or dry etching processes may be continued on the back surface (1100 ") of the device wafer (1101) to expose the through-silicon vias (not shown). The downwardly facing front surface (1100') of the device wafer (1101) is bonded to the carrier wafer (1103) via an adhesive (1102) such that the carrier wafer (1103) provides mechanical support to the device wafer (1101) during subsequent processing.

Next, as shown in fig. 12, the device wafer (1201) is etched using, for example, but not limited to, a dry etching process to etch scribe lines (1204) between a plurality of dies (not shown) within the device wafer (1201). The scribe line trench 1204 may have a width 1205 and a depth 1206, and the ratio of the depth 1206 to the width 1205 may also be referred to as the aspect ratio of the scribe line trench 1204. In one embodiment, the dry etch may include plasma dicing and laser dicing to etch the scribe trenches 1204. In this process, the device wafer (1201) is bonded to the carrier wafer (1203) via an adhesive (1202). In one embodiment, the aspect ratio of the scribe line trench 1204 may be between 1 and 10, which facilitates the closing or pinching off of the passivation layer on the scribe line trench 1204 with conventional deposition processes.

Next, as shown in fig. 13, a deposition process is performed on the device wafer (1301) to form a passivation layer (1304) on the front surface of the device wafer (1301) and the bottom surfaces and sidewalls of the scribe line trenches. As an example, the deposition process to form the passivation layer 1301 may include, but is not limited to, low temperature chemical vapor deposition, and the passivation layer 1301 may be any passivation material including SiN, SiO, silicates, such as Tetraethoxysilane (TEOS), and the like. During this process, the device wafer (1301) remains bonded to the carrier wafer (1303) via the adhesive (1302).

Similar to the embodiment of fig. 4, during the deposition process performed in the embodiment of fig. 13, as long as the aspect ratio of the scribe line trench is large enough, the passivation layer material can automatically fold at the top of the scribe line trench, forming a bridge of passivation layer material at the top, which together with the passivation layer material deposited on the bottom and both sidewalls of the scribe line trench encloses a void (1305), which void (1305) does not contain any passivation layer material. It should be appreciated that the shape of the holes 1305 are not limited to the generally elliptical shape shown in fig. 13, but may take any regular or irregular shape due to variations in process conditions.

The back surface of the device wafer 1401 is then polished using a polishing process, e.g. including a CMP process, to at least partially remove the passivation layer 1304 on the back surface, thereby exposing electrical connection areas (e.g. TSVs, etc.) for subsequent back surface process processes (e.g. Under Bump Metallization (UBM), ball mounting, etc.). However, for embodiments where the back surface of the device wafer (1401) does not have electrical connection areas (e.g., TSVs, etc.), the step of polishing from the back surface is optional. It should be appreciated that the polishing process performed on the back surface of the device wafer 1401 as described above may also remove only a portion of the passivation layer 1304 to expose the electrical connection regions (e.g., TSVs, etc.), rather than removing the passivation layer 1304 entirely, which not only simplifies the process and reduces the cost, but also provides additional protection to the back surface of the device wafer 1401.

After the polishing (or partial polishing) process is completed, the adhesive 1302 and carrier wafer 1303 may be removed, leaving the device wafer 1400 as shown in fig. 14. To this end, the device wafer (1400) is composed of a plurality of cut dies and a passivation layer (1401) for connecting the dies, wherein the passivation layer (1401) includes a hole (1402). In fig. 14, the spaced die and passivation layer can also be considered as a whole die chain (140). The die chain (140) may then be sent to an assembly line and mounted to a carrier tape for subsequent die detachment.

As shown in fig. 15, a die link (150) formed from a device wafer (1501) including a die and a passivation layer (1504) is mounted to an adhesive tape (1503). Since the passivation layer (1504) between the dies contains holes (1505) inside, the dies provide a fragile mechanical connection only by the passivation material on the top and bottom of the passivation layer (1504), and the passivation layer (1504) connection between the dies can be easily broken upon application of a proper external force, thereby realizing easy detachment of the dies.

Meanwhile, the side wall of the detached bare chip can still be protected by the residual passivation layer (1504), and the pollutants such as copper and the like are prevented from diffusing into the bare chip through the side wall of the bare chip. In one embodiment, the adhesive tape (1503) can be forced to deform in tension by performing tension on the pull handles (1506) at both ends of the adhesive tape (1503) and transmitting the tensile stress to the die chain (150), so that the passivation layer (1504) between the dies is broken along the weak points of the holes (1505), and finally the complete detachment of each die is completed. It should be appreciated that the pull handle (1506) is not necessary or can be replaced by other means.

The die after completion of the detachment is shown in fig. 16. In fig. 16, the individual dies in the die chain (160) are separated from each other to form a gap (1605), and the broken passivation layer (1604) can still be attached to the sidewalls of the dies to continue to provide additional protection to the die sidewalls.

Fig. 17 to 20 show an embodiment of a semiconductor package obtained according to the embodiment of fig. 10 or 16.

In fig. 17, a semiconductor die (1700) includes a back surface (1702), a front surface (1701), and sidewalls (1703), where the back surface (1702) is opposite the front surface (1701), and the sidewalls (1703) on both sides of the semiconductor die (1700) connect the back surface (1701) and the front surface (1702) to each other. The semiconductor die (1700) has a thickness D. For one embodiment, the thickness D of the semiconductor die 1700 may be approximately 10 μm to 50 μm.

The semiconductor die (1700) also includes a passivation layer (1706) on the sidewalls (1703), the passivation layer (1706) can include, for example and without limitation, a nitride, an oxide, an oxynitride, a silicate, such as Tetraethoxysilane (TEOS), or a combination thereof. The passivation layer (1706) includes a generally arcuate profile (1707) as shown in phantom in fig. 17, with the thinnest portion of the arcuate profile (1707) being adjacent the middle of the sidewall (1703). Although the passivation layer (1706) generally has an arcuate profile (1707), the actual edge of the passivation layer (1706) may include irregular profiles (e.g., randomly occurring irregular cracks) at the top and bottom of the sidewalls (1703) along the arcuate profile (1707) as a result of the passivation layer in the die paddle breaking due to stretching by an external force, as viewed in detail. The thinnest portion of the arc profile (1707) may be denoted as T1, while the thickness of the passivation layer (1706) adjacent to the top and bottom of the sidewall (1703) may be denoted as T2 and T3, respectively. The top thickness T2 and the bottom thickness T3 of the side wall (1703) are both greater than the thickness T1 of the middle of the side wall (1703). In an embodiment, the thickest portion of the sidewalls (1703), such as the thicker of the top thickness T2 and the bottom thickness T3, is less than one tenth of the thickness D of the semiconductor die (1700), which on the one hand can ensure that the aspect ratio of the scribe line trench is sufficiently large, and on the other hand can narrow the scribe line as much as possible (e.g., can be as narrow as 10 μm or even 3 μm, rather than the conventional 80 μm) in order to make more room for the die area. It should be appreciated that the faster and higher aspect ratio deposition process of the scribe line trench results in earlier passivation layer healing or pinch-off at the top of the scribe line trench. Conversely, a slower deposition process with a smaller aspect ratio of the scribe line trench results in a later process of passivation layer folding or pinch-off at the top of the scribe line trench.

The semiconductor die (1700) of fig. 17 may be a through-silicon via or through-silicon via-less package structure. In some embodiments, if the package structure does not have a through silicon via, the passivation layer 1706 may be disposed on the back surface 1702 as shown in fig. 18. In some embodiments, if the package structure has through-silicon vias, the passivation layer 1706 may partially remain on the back surface 1702, and only a portion of the through-silicon vias exposes the passivation layer 1706 on the back surface 1702.

In addition, a redistribution layer (RDL) (1705) and solder balls (1704) may be further formed on the front surface of the semiconductor die (1700) for making electrical connections to the outside. Embodiments of the semiconductor die (1700) making electrical connections to the outside via solder balls (1704) will be described below.

The embodiment shown in fig. 18 has a similar structure to the semiconductor package shown in fig. 17, except that the passivation layer (1801) in the embodiment of fig. 18 covers not only the sidewalls of the semiconductor die (1800) but also the back surface of the semiconductor die (1800). The embodiment of fig. 18 may provide more complete protection to the semiconductor die (1800) to prevent particulate contaminants from diffusing through the uncovered surface into the semiconductor die (1800).

The embodiment of fig. 19 has a similar structure to the semiconductor package of fig. 17, except that the embodiment of fig. 19 further employs through-silicon vias (1902) (e.g., TSVs) to electrically connect the front and back surfaces of the semiconductor die (1900). The front surface of the semiconductor die (1900) is electrically connected to the outside by forming solder balls (1903). The passivation layer (1901) covers at least the sidewalls of the semiconductor die (1900).

Fig. 20 shows a semiconductor package that can be used to implement hybrid bonding, which has a similar structure to the semiconductor package shown in fig. 17 (i.e., with a passivation layer (2001) covering the sidewalls of the semiconductor die (2000)), but differs therefrom in that the embodiment of fig. 20 has a hybrid bonding layer, including metal traces (2002) that are coplanar with a dielectric layer (2203) therebetween, so that electrical connection can be made to the outside in a hybrid bonding manner without the need for forming solder balls, thereby further saving space and achieving an electrical performance enhancement.

It should be understood that the semiconductor package structures shown in fig. 17-20 are only some of the semiconductor package embodiments obtained by the stretching method of fig. 10 or 16, and thus any other semiconductor package structure suitable for the embodiments of the present invention can be included.

Fig. 21 to 23 are corresponding schematic views of the semiconductor package shown in fig. 17 to 19 after being bonded to a carrier.

The embodiment shown in fig. 21 corresponds to the embodiment shown in fig. 17. In fig. 21, a semiconductor die (2100) includes a back surface (2102), a front surface (2101), and sidewalls (2103), where the back surface (2102) is opposite the front surface (2101), and the sidewalls (2103) on both sides of the semiconductor die (2100) connect the back surface (2102) and the front surface (2101) to each other. The semiconductor die (2100) has a thickness D. As an example, the semiconductor die (2100) may have a thickness D of about 10 μm to about 50 μm. The semiconductor die (2100) also includes a passivation layer (2106) on the sidewall (2103), the passivation layer (2106) including a substantially arcuate profile (2107), a thinnest portion of the arcuate profile (2107) being adjacent a middle of the sidewall (2103), and edges of the passivation layer (2106) including irregular profiles along the arcuate profile (2107) at top and bottom of the sidewall (2103). The thinnest portion of the arcuate profile (2107) may be denoted as T1, while the thickness of the passivation layer (2106) adjacent the top and bottom of the sidewall (2103) may be denoted as T2 and T3, respectively. Both thicknesses T2 and T3 are greater than thickness T1.

The semiconductor die (2100) in fig. 21 is electrically connected to the carrier (2108) via RDL and UBM (2104) and solder balls (2105). Wherein the semiconductor die (2100) is flip-chip bonded to the carrier plate (2108).

Fig. 22 corresponds to the embodiment shown in fig. 18. In fig. 22, the passivation layer (2201) covers not only the sidewalls of the semiconductor die (2200) but also the back surface of the semiconductor die (2200). Semiconductor die (2200) is electrically connected to carrier board (2208) via RDL and UBM (2204) and solder balls (2205). Wherein the semiconductor die (2200) is flip-chip bonded to the carrier (2208).

Fig. 23 corresponds to the embodiment shown in fig. 19. In fig. 23, the front and back surfaces of semiconductor die (2300) are electrically connected via through-holes (2302) (e.g., TSVs), and semiconductor die (2300) can be electrically connected to carrier board (2308) directly through solder balls (2303) under through-holes (2302). The passivation layer (2301) covers sidewalls of the semiconductor die (2300). Unlike fig. 21 and 22, the semiconductor die (2300) may be further bonded with other dies or package structures with the front surface facing upward.

Fig. 24 is a schematic diagram showing two semiconductor packages of fig. 20 after hybrid bonding. In fig. 24, two semiconductor dies (2400) are opposed to each other, and both the passivation layers (2401) cover the sidewalls of the semiconductor dies (2400). With the hybrid bonding layer, including the metal traces (2402) coplanar with the dielectric layer therebetween, the two semiconductor dies (2400) can be electrically connected directly through the respective metal traces (2402), thereby further reducing package thickness and achieving improved electrical performance.

The semiconductor bare chip structure and the preparation and use method thereof skillfully utilize the pinch-off effect which is generally regarded as a process defect, and automatically realize the folding of the passivation layer material at the top of the scribing groove so as to form a hole in the passivation layer in the scribing groove, thereby realizing the simple and convenient splitting of the bare chip by means of carrier tape stretching on one hand, and providing necessary protection for the edge of the split bare chip so as to prevent pollutants such as copper from diffusing through silicon and prevent the reliability fault caused by the influence of particle pollution on open interconnection, thereby improving the yield of products.

In addition, in the present invention, since the dicing (dry etching) of the device wafer is performed on the support of the carrier wafer, the present invention can make the selection of the carrier tape more extensive and flexible, since the carrier tape applicable to the present invention is not necessarily limited to support the conventional dicing method and structure.

It should be noted that reference throughout this specification to "an embodiment of the invention" or similar terms means that a particular feature, structure or characteristic described in connection with the other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Thus, respective appearances of the phrase "one embodiment of the present invention" or similar terms in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, or characteristics of any specific embodiment may be combined in any suitable manner with one or more other embodiments.

The technical content and the technical features of the present invention have been described in the above related embodiments, however, the above embodiments are only examples for implementing the present invention. Those skilled in the art may make various alterations and modifications based on the teachings and disclosure of this invention without departing from the spirit of this invention. Accordingly, the disclosed embodiments do not limit the scope of the invention. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A semiconductor package, comprising:

a semiconductor die having a front surface, a back surface opposite the front surface, and a sidewall connecting the front surface and the back surface; and

a passivation layer on the sidewall, wherein the passivation layer comprises an arcuate profile, a thinnest portion of the arcuate profile being adjacent a middle of the sidewall.

2. The semiconductor package of claim 1, wherein a thickness of the passivation layer adjacent the top or bottom of the sidewall is greater than a thickness of the passivation layer adjacent the middle of the sidewall.

3. The semiconductor package of claim 2, wherein the passivation layer further comprises an irregular profile adjacent the top or the bottom of the sidewall.

4. The semiconductor package according to any one of claims 1 to 3, wherein the passivation layer further covers the back surface of the semiconductor die.

5. The semiconductor package according to any one of claims 1 to 3, wherein a material of the passivation layer is selected from one of a nitride, an oxide, an oxynitride, or a silicate.

6. The semiconductor package according to any one of claims 1 to 3, wherein a thickest part of the passivation layer is less than one tenth of a thickness of the semiconductor die.

7. The semiconductor package of claim 6, wherein the thickness of the semiconductor die is in a range from about 10 μm to about 50 μm.

8. The semiconductor package of any one of claims 1 to 3, further comprising a carrier board connected to the semiconductor die by electrical connections.

9. The semiconductor package of any one of claims 1 to 3, wherein the front surface of the semiconductor die comprises a hybrid bonding layer.

10. The semiconductor package of any one of claims 1 to 3, further comprising a via electrically connecting the front surface and the back surface of the semiconductor die.

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