CN214203163U - Gate driving unit, gate driving circuit and display device - Google Patents
Gate driving unit, gate driving circuit and display device Download PDFInfo
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- CN214203163U CN214203163U CN202022416350.XU CN202022416350U CN214203163U CN 214203163 U CN214203163 U CN 214203163U CN 202022416350 U CN202022416350 U CN 202022416350U CN 214203163 U CN214203163 U CN 214203163U
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Abstract
The utility model provides a gate drive unit, gate drive circuit and display device. The grid driving unit comprises a pull-up node denoising circuit, a pull-down node control circuit, a pull-up node control circuit and an energy storage circuit; the pull-up node denoising circuit controls the connection or disconnection between the first pull-up node and the input end under the control of the potential of the pull-down node; the pull-up node control circuit controls the connection or disconnection between the first pull-up node and the second pull-up node under the control of the anti-creeping control voltage provided by the anti-creeping control end and is used for maintaining the potential of the second pull-up node; the energy storage circuit is electrically connected with the second pull-up node and is used for storing electric energy. The utility model provides an in the prior art the charging capacity that is the pull-up node in the input stage not enough to the time quantum between input stage and output stage can't draw down the problem of the electric potential of pull-down node.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a gate drive unit, gate drive circuit and display device.
Background
In the existing gate driving unit, a pull-up node and a pull-down node are in a competitive connection relationship, an input signal provided by an input end charges the pull-up node, the pull-up node pulls down the potential of the pull-down node through a pull-down TFT (thin film transistor), but the pull-down node pulls down the potential of the pull-up node through a denoising TFT, and when the potential of the pull-down node is higher in an input stage, the pull-up node cannot be charged, so that no gate driving signal is output. In addition, when the conventional gate driving unit operates, in a time period between an input stage and an output stage (when a duty ratio of a clock signal adopted by the gate driving unit is not equal to 0.5, a time period may be left between the input stage and the output stage), a potential of a pull-up node may be reduced due to leakage, and a situation that a potential of a pull-down node cannot be controlled to be pulled down may occur.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide a gate driving unit, a gate driving circuit and a display device, which are not sufficient in the charging capability of the pull-up node in the input stage and cannot pull down the potential of the pull-down node in the time period between the input stage and the output stage.
In order to achieve the above object, the present invention provides a gate driving unit, which includes a pull-up node denoising circuit, a pull-down node control circuit, a pull-up node control circuit and an energy storage circuit;
the pull-up node denoising circuit is respectively electrically connected with an input end, a pull-down node and a first pull-up node, and is used for controlling the connection or disconnection between the first pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit is respectively electrically connected with a second pull-up node, a pull-down node and the input end, is used for controlling the potential of the pull-down node under the control of control voltage provided by the control voltage end, and is used for controlling the connection or disconnection between the pull-down node and the input end under the control of the potential of the second pull-up node;
the pull-up node control circuit is respectively electrically connected with the anti-creeping control end, the first pull-up node and the second pull-up node, is used for controlling the connection or disconnection between the first pull-up node and the second pull-up node under the control of anti-creeping control voltage provided by the anti-creeping control end, and is used for maintaining the potential of the second pull-up node;
the energy storage circuit is electrically connected with the second pull-up node and used for storing electric energy.
The utility model also provides a grid drive circuit, including multistage foretell grid drive unit.
The utility model also provides a display device, including foretell gate drive circuit.
The gate driving unit, the gate driving circuit and the display device provided by the embodiment of the invention can avoid the problem of insufficient charging capability of the pull-up node due to competition of the pull-up node and the pull-down node, and can better charge the first pull-up node in the input stage; the embodiment of the utility model provides a gate drive unit at the during operation, time quantum between input stage and output stage (in the embodiment of the utility model provides an, when the duty cycle of the clock signal that gate drive unit adopted is not equal to 0.5, can interval a time quantum between input stage and the output stage), pull-up node control circuit can prevent to make the second pull-up potential of node reduce because the electric leakage under the control of anticreep control voltage, and lead to the condition emergence that the potential of the pull-down node is drawn down to uncontrollable.
Drawings
Fig. 1 is a structural diagram of a gate driving unit according to an embodiment of the present invention;
fig. 2 is a structural diagram of a gate driving unit according to another embodiment of the present invention;
fig. 3 is a structural diagram of a gate driving unit according to another embodiment of the present invention;
fig. 4 is a structural diagram of a gate driving unit according to still another embodiment of the present invention;
fig. 5 is a circuit diagram of an embodiment of a gate driving unit according to the present invention;
fig. 6 is a timing diagram illustrating the operation of the gate driving unit shown in fig. 5 according to the embodiment of the present invention;
fig. 7 is a simulation timing diagram of the embodiment of the gate driving unit shown in fig. 5 according to the present invention;
fig. 8 is a circuit diagram of another embodiment of a gate driving unit according to the present invention;
fig. 9 is a circuit diagram of a further embodiment of a gate driving unit according to the present invention;
fig. 10 is a simulation timing diagram of the embodiment of the gate driving unit shown in fig. 9 according to the present invention;
fig. 11 is a circuit diagram of still another embodiment of a gate driving unit according to the present invention;
fig. 12 is a simulation timing diagram of the embodiment of the gate driving unit shown in fig. 11 according to the present invention;
fig. 13 is a circuit diagram of a further embodiment of a gate driving unit according to the present invention;
fig. 14 is a simulation timing diagram of the embodiment of the gate driving unit shown in fig. 13 according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 1, the gate driving unit according to the embodiment of the present invention includes a pull-up node denoising circuit 11, a pull-down node control circuit 12, a pull-up node control circuit 13, and an energy storage circuit 14;
the pull-up node denoising circuit 11 is electrically connected with an INPUT end INPUT, a pull-down node PD and a first pull-up node PU, and is configured to control the connection or disconnection between the first pull-up node PU and the INPUT end INPUT under the control of the potential of the pull-down node PD;
the pull-down node control circuit 12 is electrically connected to a control voltage terminal VDD, a second pull-up node PU _1, a pull-down node PD, and the INPUT terminal INPUT, respectively, and is configured to control a potential of the pull-down node PD under control of a control voltage provided by the control voltage terminal VDD, and to control connection or disconnection between the pull-down node PD and the INPUT terminal INPUT under control of a potential of the second pull-up node PU _ 1;
the pull-up node control circuit 13 is electrically connected to the leakage prevention control terminal Ct, the first pull-up node PU and the second pull-up node PU _1, and is configured to control connection or disconnection between the first pull-up node PU and the second pull-up node PU _1 under control of a leakage prevention control voltage provided by the leakage prevention control terminal Ct, and to maintain a potential of the second pull-up node PU _ 1;
the energy storage circuit 14 is electrically connected to the second pull-up node PU _1 and configured to store electric energy.
The embodiment of the utility model provides a gate drive unit at the during operation, pull-up node denoising circuit 11 is under the control of the electric potential of drop-down node PD, control communicate between first pull-up node PU and the INPUT INPUT, at the INPUT stage, drop-down node control circuit 12 is under the control of the electric potential of second pull-up node PU _1, control drop-down node PD is connected with INPUT INPUT electricity, make at the INPUT stage, the electric potential of drop-down node PD keeps to high-voltage, can avoid because pull-up node and drop-down node competition lead to the problem of the not enough charging capacity to the pull-up node, better charge for first pull-up node PU at the INPUT stage; in addition, in the input stage, the pull-up node control circuit 13 controls the first pull-up node PU and the second pull-up node PU _1 to be connected under the control of the leakage prevention control voltage provided by the leakage prevention control terminal Ct, so as to charge the energy storage circuit 14 until the potential of the PU _1 rises to a certain value, and the pull-up node control circuit 13 controls the first pull-up node PU and the second pull-up node PU _1 to be disconnected, so that the charging of the second pull-up node PU _1 can be completed; and, the embodiment of the utility model provides a gate drive unit at the during operation, time quantum between input stage and output stage (in the embodiment of the utility model provides an, when the duty cycle of the clock signal that gate drive unit adopted is not equal to 0.5, can interval a time quantum between input stage and the output stage), pull-up node control circuit 13 can prevent to make the second pull-up node PU _ 1's potential reduction because of the electric leakage under the control of anticreep control voltage, and lead to the condition emergence that the potential of pull-down node is drawn down to uncontrollable.
The embodiment of the utility model provides an in, if do not set up pull-up node control circuit 13, then in the time quantum between input stage and the output stage, PU's electric potential reduces because the electric leakage to lead to can't make pull-down node's electric potential to be drawn down, can lead to unable PU's high voltage of maintaining, lead to unable normal gate drive output.
The gate driving unit according to the embodiment of the present invention is based on Oxide technology, and may also be based on a-si (Amorphous Silicon) and LTPS (Low Temperature polysilicon) technology, but not limited thereto.
Optionally, the pull-up node denoising circuit is electrically connected to a pull-down node, and the pull-up node denoising circuit includes a pull-up node denoising transistor; the control electrode of the pull-up node denoising transistor is electrically connected with the pull-down node, the first electrode of the pull-up node denoising transistor is electrically connected with the pull-up node, and the second electrode of the pull-up node denoising transistor is electrically connected with the input end; alternatively, the first and second electrodes may be,
the pull-down nodes comprise a first pull-down node and a second pull-down node; the pull-up node denoising circuit comprises a first pull-up node denoising transistor and a second pull-up node denoising transistor; a control electrode of the first pull-up node denoising transistor is electrically connected with the first pull-down node, a first electrode of the first pull-up node denoising transistor is electrically connected with the pull-up node, and a second electrode of the first pull-up node denoising transistor is electrically connected with the input end; the control electrode of the second pull-up node denoising transistor is electrically connected with the second pull-down node, the first electrode of the second pull-up node denoising transistor is electrically connected with the pull-up node, and the second electrode of the second pull-up node denoising transistor is electrically connected with the input end.
Optionally, the leakage prevention control terminal is the control voltage terminal or the pull-down node.
In a specific implementation, as shown in fig. 2, when the leakage prevention control terminal is the pull-down node PD, the gate driving unit further includes a first pull-up node reset circuit 20;
the first pull-up node Reset circuit 20 is electrically connected to the Reset terminal Reset, the second pull-up node PU _1 and the Reset voltage terminal Vr, and is configured to control connection or disconnection between the second pull-up node PU _1 and the Reset voltage terminal Vr under the control of a Reset signal provided by the Reset terminal Reset.
In specific implementation, when the anti-creeping control terminal is the pull-down node, after the gate driving signal is output, if no first pull-up node reset circuit 20 resets the second pull-up node PU _1, the potential of the second pull-up node PU _1 is still maintained at a high potential, so that the potential of the pull-down node is at a low voltage, which may cause the multi-gate driving signal to be output.
The utility model discloses a grid drive unit as shown in fig. 2 is at the phase that resets at the during operation under reset signal's control, first pull-up node reset circuit 20 control second pull-up node PU _1 with communicate between the reduction voltage end Vr, it is right second pull-up node PU _ 1's electric potential resets.
Optionally, the reset voltage terminal Vr may be a first low voltage terminal or an input terminal, but is not limited thereto.
Alternatively, the first pull-up node reset circuit 20 may include a first pull-up node reset transistor;
the control electrode of the first pull-up node reset transistor is electrically connected with the reset end, the first electrode of the first pull-up node reset transistor is electrically connected with the second pull-up node, and the second electrode of the first pull-up node reset transistor is electrically connected with the reset voltage end.
According to a specific embodiment, the pull-up node control circuit may include a pull-up control transistor, and the tank circuit may include a storage capacitor;
a grid electrode of the pull-up control transistor is electrically connected with the control voltage end or the pull-down node, a first pole of the pull-up control transistor is electrically connected with the second pull-up node, and a second pole of the pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
In practical implementation, when the gate driving unit according to the embodiment of the present invention only includes one pull-down node, the pull-up node control circuit may only include one pull-up control transistor, and at this time, the control voltage terminal may be a dc voltage terminal, but not limited thereto.
In the embodiment of the present invention, as shown in fig. 3, on the basis of the embodiment shown in fig. 1, the pull-down node includes a first pull-down node PD _ a and a second pull-down node PD _ B, and the control voltage terminal includes a first control voltage terminal VDD _ a and a second control voltage terminal VDD _ B;
the pull-down node control circuit 12 is respectively electrically connected to a first control voltage terminal VDD _ a, a second control voltage terminal VDD _ B, a second pull-up node PU _1, a first pull-down node PD _ a, a second pull-down node PD _ B and the INPUT terminal INPUT, is configured to control a potential of the first pull-down node PD _ a under control of a first control voltage provided by the first control voltage terminal VDD _ a, and to control communication or disconnection between the first pull-down node PD _ a and the INPUT terminal INPUT under control of the second pull-up node PU _1, and is configured to control a potential of the second pull-down node PD _ B under control of a second control voltage provided by the second control voltage terminal VDD _ B, and to control the second pull-down node PD _ a to be electrically connected to the INPUT terminal INPUT under control of the second pull-up node PU _ 1.
In specific implementation, when the gate driving unit according to the embodiment of the present invention includes the first pull-down node and the second pull-down node, the gate driving unit adopts the first control voltage terminal and the second control voltage terminal, and when the first control voltage provided by the first control voltage terminal is the high voltage, the second control voltage provided by the second control voltage terminal is the low voltage; when the first control voltage is a low voltage, the second control voltage is a high voltage; therefore, the transistor controlled by the first control voltage end and the transistor controlled by the second control voltage end can work alternately, and threshold voltage drift caused by long-time opening of the transistor controlled by the first control voltage end and the transistor controlled by the second control voltage end is prevented.
In the embodiment of the present invention, every predetermined time (the predetermined time may be less than a frame of image display time, and may also be greater than a frame of image display time, and the predetermined time may be selected according to actual conditions), the first control voltage terminal and the second control voltage terminal alternately provide the high voltage. That is, when the first control voltage terminal provides a high voltage, the second control voltage terminal provides a low voltage; when the first control voltage terminal provides a low voltage, the second control voltage terminal provides a high voltage.
Optionally, the pull-up node control circuit includes a first pull-up control transistor and a second pull-up control transistor; the energy storage circuit comprises a storage capacitor;
a control electrode of the first pull-up control transistor is electrically connected with the first pull-down node, a first electrode of the first pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the first pull-up control transistor is electrically connected with the first pull-up node;
a control electrode of the second pull-up control transistor is electrically connected with the second pull-down node, a first electrode of the second pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the second pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
When the control electrode of the first pull-up control transistor is electrically connected with the first pull-down node and the control electrode of the second pull-up control transistor is electrically connected with the second pull-down node, in a time period between an input stage and an output stage, because the potential of the first pull-down node and the potential of the second pull-down node are pulled down, the gate-source voltage of the first pull-up control transistor and the gate-source voltage of the second pull-up control transistor are smaller, the leakage current of the first pull-up control transistor and the leakage current of the second pull-up control transistor are smaller, and the pull-up node control circuit can well maintain the potential of the second pull-up node and prevent the potential of the second pull-up node from being lowered too low.
Optionally, the pull-up node control circuit includes a first pull-up control transistor and a second pull-up control transistor, and the energy storage circuit includes a storage capacitor;
a control electrode of the first pull-up control transistor is electrically connected with a first control voltage end, a first electrode of the first pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the first pull-up control transistor is electrically connected with the first pull-up node;
a control electrode of the second pull-up control transistor is electrically connected with the second control voltage terminal, a first electrode of the second pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the second pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
In a specific implementation, the control electrode of the first pull-up control transistor and the control electrode of the second pull-up control transistor may be electrically connected to the first control voltage terminal and the second control voltage terminal, respectively, and may also play a role in preventing the potential of the second pull-up node from decreasing too low in a time period between the input stage and the output stage.
According to a specific embodiment, the pull-down node control circuit may include a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor, wherein,
a control electrode of the first pull-down control transistor and a first electrode of the first pull-down control transistor are both electrically connected with the first control voltage terminal, and a second electrode of the first pull-down control transistor is electrically connected with the first pull-down node;
a control electrode of the second pull-down control transistor is electrically connected with the second pull-up node, a first electrode of the second pull-down control transistor is electrically connected with the first pull-down node, and a second electrode of the second pull-down control transistor is electrically connected with the input end;
a control electrode of the third pull-down control transistor and a first electrode of the third pull-down control transistor are both electrically connected with the second control voltage terminal, and a second electrode of the third pull-down control transistor is electrically connected with the second pull-down node;
and the control electrode of the fourth pull-down control transistor is electrically connected with the second pull-up node, the first electrode of the fourth pull-down control transistor is electrically connected with the second pull-down node, and the second electrode of the fourth pull-down control transistor is electrically connected with the input end.
According to another embodiment, the pull-down node control circuit may include a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor, and an eighth pull-down control transistor, wherein,
a control electrode of the fifth pull-down control transistor and a first electrode of the fifth pull-down control transistor are both electrically connected with a first control voltage terminal;
a control electrode of the first pull-down control transistor is electrically connected with a second electrode of the fifth pull-down control transistor, a first electrode of the first pull-down control transistor is electrically connected with the first control voltage terminal, and a second electrode of the first pull-down control transistor is electrically connected with the first pull-down node;
a control electrode of the sixth pull-down control transistor is electrically connected with the second pull-up node, and a first electrode of the sixth pull-down control transistor is electrically connected with a second electrode of the fifth pull-down control transistor; a second pole of the sixth pull-down control transistor is electrically connected with the input terminal;
a control electrode of the second pull-down control transistor is electrically connected with the second pull-up node, a first electrode of the second pull-down control transistor is electrically connected with the first pull-down node, and a second electrode of the second pull-down control transistor is electrically connected with the input end;
a control electrode of the seventh pull-down control transistor and a first electrode of the seventh pull-down control transistor are both electrically connected with a second control voltage terminal;
a control electrode of the third pull-down control transistor is electrically connected with a second electrode of the seventh pull-down control transistor, a first electrode of the third pull-down control transistor is electrically connected with the second control voltage terminal, and a second electrode of the third pull-down control transistor is electrically connected with the second pull-down node;
a control electrode of the eighth pull-down control transistor is electrically connected with the second pull-up node, a first electrode of the eighth pull-down control transistor is electrically connected with a second electrode of the seventh pull-down control transistor, and the second electrode of the eighth pull-down control transistor is electrically connected with the input end;
and the control electrode of the fourth pull-down control transistor is electrically connected with the second pull-up node, the first electrode of the fourth pull-down control transistor is electrically connected with the second pull-down node, and the second electrode of the fourth pull-down control transistor is electrically connected with the input end.
In practical operation, in an embodiment of the pull-down node control circuit, a control electrode of the first pull-down control transistor is electrically connected to the first pull-down control node, and a control electrode of the third pull-down control transistor is electrically connected to the second pull-down control node;
the first pull-down control node is controlled by a fifth pull-down control transistor and a sixth pull-down control transistor, and the second pull-down control node is controlled by a seventh pull-down control transistor and an eighth pull-down control transistor;
when the gate driving unit of the embodiment of the present invention is in operation, the first pull-down control transistor, the second pull-down control transistor, the third pull-down control transistor, the fourth pull-down control transistor, the fifth pull-down control transistor, the sixth pull-down control transistor, the seventh pull-down control transistor, and the eighth pull-down control transistor included in the pull-down node control circuit are all n-type transistors,
when the potential of the second pull-up node is high voltage, the fifth pull-down control transistor and the sixth pull-down control transistor control the first pull-down control node to be low voltage, the first pull-down control transistor is turned off, the second pull-down control transistor is turned on, and the potential of the first pull-down node can be ensured to be low voltage, so that the problem that when the potential of the second pull-up node is high voltage, the first pull-down control transistor and the second pull-down control transistor are both turned on, so that the potential of the first pull-down node cannot be sufficiently pulled down can be easily caused when the potential of the second pull-up node is high voltage;
when the potential of the second pull-up node is a high voltage, the seventh pull-down control transistor and the eighth pull-down control transistor control the second pull-down control node to be a low voltage, the third pull-down control transistor is turned off, and the fourth pull-down control transistor is turned on, so that the potential of the second pull-down node can be ensured to be a low voltage, and the problem that when the pull-down node control circuit only includes the first pull-down control transistor, the second pull-down control transistor, the third pull-down control transistor and the fourth pull-down control transistor, the potential of the second pull-down node cannot be sufficiently pulled down due to the fact that the third pull-down control transistor and the fourth pull-down control transistor are turned on when the potential of the second pull-up node is a high voltage can be easily caused.
In the embodiment of the present invention, the gate driving unit may further include a second pull-up node reset circuit;
the second pull-up node reset circuit is electrically connected with the first pull-up node and is used for resetting the potential of the first pull-up node in a reset stage.
Optionally, the second pull-up node reset circuit includes a second pull-up node reset transistor;
the control electrode of the second pull-up node reset transistor is electrically connected with the first clock signal end, the first electrode of the second pull-up node reset transistor is electrically connected with the first pull-up node, and the second electrode of the second pull-up node reset transistor is electrically connected with the input end.
In a specific implementation, the second pull-up node reset circuit may include a second pull-up node reset transistor, a control electrode of the second pull-up node reset transistor may be electrically connected to the first clock signal terminal, at this time, a second electrode of the second pull-up node reset transistor needs to be electrically connected to the input terminal, so that in the input stage, the first pull-up node is charged by the input signal provided by the input terminal under the control of the first clock signal provided by the first clock signal terminal, and in the reset stage, the first pull-up node is reset by the input signal under the control of the first clock signal.
Optionally, the second pull-up node reset circuit includes a second pull-up node reset transistor;
the control electrode of the second pull-up node reset transistor is electrically connected with the reset end, the first electrode of the second pull-up node reset transistor is electrically connected with the first pull-up node, and the second electrode of the second pull-up node reset transistor is electrically connected with the input end or the first low-voltage end.
In a specific implementation, the second pull-up node reset circuit may include a second pull-up node reset transistor, a control electrode of the second pull-up node reset transistor may be electrically connected to the reset terminal, and at this time, a second electrode of the second pull-up node reset transistor may be electrically connected to the input terminal or the first low voltage terminal, so that in the reset stage, the first pull-up node is reset by the input signal or the first low voltage provided by the first low voltage terminal under the control of the reset signal provided by the reset terminal.
Optionally, the gate driving unit according to the embodiment of the present invention further includes a third pull-up node reset circuit;
the third pull-up node reset circuit is respectively electrically connected with the interframe reset end, the first pull-up node and the first low-voltage end, and is used for controlling the connection or disconnection between the first pull-up node and the first low-voltage end in an interframe blank time period under the control of an interframe reset signal provided by the interframe reset end.
In specific implementation, the gate driving unit according to the embodiment of the present invention may further include a third pull-up node reset circuit; and the third pull-up node reset circuit controls the first pull-up node to be communicated with the first low-voltage end under the control of an interframe reset signal in an interframe blank time period so as to reset the potential of the first pull-up node.
Optionally, the gate driving unit according to the embodiment of the present invention further includes a carry signal output circuit and a gate driving signal output circuit, wherein,
the carry signal output circuit is respectively electrically connected with a second pull-up node, a second clock signal end, a pull-down node, a carry signal output end and a first low voltage end, is used for controlling the carry signal output end to be electrically connected with the second clock signal end under the control of the potential of the second pull-up node, and is also used for controlling the carry signal output end to be connected or disconnected with the first low voltage end under the control of the potential of the pull-down node;
the grid driving signal output circuit is respectively electrically connected with a second pull-up node, a second clock signal end, a pull-down node, a grid driving signal output end and a second low voltage end, and is used for controlling the grid driving signal output end to be electrically connected with the second clock signal end under the control of the potential of the second pull-up node and also used for controlling the grid driving signal output end to be communicated or disconnected with the second low voltage end under the control of the potential of the pull-down node.
The embodiment of the utility model provides an in, the gate drive unit can also include carry signal output circuit and gate drive signal output circuit, carry signal output circuit control carry signal output carry signal, gate drive signal output circuit control gate drive signal output gate drive signal, the carry signal output is used for providing input signal for adjacent next-level shift register unit to provide reset signal for adjacent last-level shift register unit, gate drive signal output is used for providing the gate drive signal who carries out gate drive.
In an embodiment of the present invention, the first low voltage provided by the first low voltage terminal is less than the second low voltage provided by the second low voltage terminal, so as to compensate the stress of the first gate driving output transistor for outputting the gate driving signal included in the gate driving signal output circuit in the non-output stage, thereby reducing the threshold voltage drift of the first gate driving signal output transistor.
As shown in fig. 4, on the basis of the embodiment of the gate driving unit shown in fig. 3, the gate driving unit according to the embodiment of the present invention may further include a second pull-up node reset circuit 40, a carry signal output circuit 41 and a gate driving signal output circuit 42, wherein,
the second pull-up node reset circuit 40 is electrically connected to the first pull-up node PU, and is configured to reset a potential of the first pull-up node PU in a reset phase;
the carry signal output circuit 41 is electrically connected to the second pull-up node PU _1, the second clock signal terminal, the first pull-down node PD _ a, the carry signal output terminal OUT _ C, and the first low voltage terminal, respectively, and is configured to control the carry signal output terminal OUT _ C to be electrically connected to the second clock signal terminal under the control of the potential of the second pull-up node PU _1, and further configured to control the carry signal output terminal OUT _ C to be connected to or disconnected from the first low voltage terminal under the control of the potential of the first pull-down node PD _ a and the potential of the second pull-down node PD _ B; the second clock signal terminal is used for providing a second clock signal CLK, and the first low voltage terminal is used for providing a first low voltage LVGL;
the gate driving signal output circuit 42 is respectively electrically connected to a second pull-up node PU _1, a second clock signal terminal, a first pull-down node PD _ a, a second pull-down node PD _ B, a gate driving signal output terminal OUT1 and a second low voltage terminal, and is configured to control the gate driving signal output terminal OUT1 to be electrically connected to the second clock signal terminal under the control of the potential of the second pull-up node PU _1, and further to control the gate driving signal output terminal OUT1 to be connected to or disconnected from the second low voltage terminal under the control of the potential of the first pull-down node PD _ a and the potential of the second pull-down node PD _ B;
the second low voltage terminal is used for providing a second low voltage VGL.
Optionally, the pull-down nodes may include a first pull-down node and a second pull-down node;
the carry signal output circuit comprises a first carry signal output transistor, a second carry signal output transistor and a third carry signal output transistor, and the grid drive signal output circuit comprises a first grid drive output transistor, a second grid drive output transistor and a third grid drive output transistor;
a control electrode of the first carry signal output transistor is electrically connected with the second pull-up node, a first electrode of the first carry signal output transistor is electrically connected with the second clock signal end, and a second electrode of the first carry signal output transistor is electrically connected with the carry signal output end;
a control electrode of the second carry signal output transistor is electrically connected with the first pull-down node, a first electrode of the second carry signal output transistor is electrically connected with the carry signal output end, and a second electrode of the second carry signal output transistor is electrically connected with the first low voltage end;
a control electrode of the third carry signal output transistor is electrically connected with the second pull-down node, a first electrode of the third carry signal output transistor is electrically connected with the carry signal output end, and a second electrode of the third carry signal output transistor is electrically connected with the first low-voltage end;
the control electrode of the first grid electrode driving output transistor is electrically connected with the second pull-up node, the first electrode of the first grid electrode driving output transistor is electrically connected with the second clock signal end, and the second electrode of the first grid electrode driving output transistor is electrically connected with the grid electrode driving signal output end;
a control electrode of the second gate driving output transistor is electrically connected with the first pull-down node, a first electrode of the second gate driving output transistor is electrically connected with the gate driving signal output end, and a second electrode of the second gate driving output transistor is electrically connected with the second low-voltage end;
the control electrode of the third gate drive output transistor is electrically connected with the second pull-down node, the first electrode of the third gate drive output transistor is electrically connected with the gate drive signal output end, and the second electrode of the third gate drive output transistor is electrically connected with the first low-voltage end.
As shown in fig. 5, on the basis of the embodiment of the gate driving unit shown in fig. 4,
the pull-up node denoising circuit 11 comprises a first pull-up node denoising transistor M7A and a second pull-up node denoising transistor M7B;
the gate of the first pull-up node denoising transistor M7A is electrically connected to the first pull-down node PD _ a, the drain of the first pull-up node denoising transistor M7A is electrically connected to the pull-up node PU, and the source of the first pull-up node denoising transistor M7A is electrically connected to the INPUT terminal INPUT;
the gate of the second pull-up node denoising transistor M7B is electrically connected to the second pull-down node PD _ B, the drain of the second pull-up node denoising transistor M7B is electrically connected to the pull-up node PU, and the source of the second pull-up node denoising transistor M7B is electrically connected to the INPUT terminal INPUT;
the pull-down node control circuit includes a first pull-down control transistor M5A, a second pull-down control transistor M6A, a third pull-down control transistor M5B, and a fourth pull-down control transistor M6B, wherein,
the gate of the first pull-down control transistor M5A and the drain of the first pull-down control transistor M5A are both electrically connected to the first control voltage terminal VDD _ a, and the source of the first pull-down control transistor M5A is electrically connected to the first pull-down node PD _ a;
the gate of the second pull-down control transistor M6A is electrically connected to the second pull-up node PU _1, the drain of the second pull-down control transistor M6A is electrically connected to the first pull-down node PD _ a, and the source of the second pull-down control transistor M6A is electrically connected to the INPUT terminal INPUT;
the gate of the third pull-down control transistor M5B and the drain of the third pull-down control transistor M5B are both electrically connected to the second control voltage terminal VDD _ B, and the source of the third pull-down control transistor M5B is electrically connected to the second pull-down node PD _ B;
a gate of the fourth pull-down control transistor M6B is electrically connected to the second pull-up node PU _1, a drain of the fourth pull-down control transistor M6B is electrically connected to the second pull-down node PD _ B, and a source of the fourth pull-down control transistor M6B is electrically connected to the INPUT terminal INPUT;
the pull-up node control circuit 13 includes a first pull-up control transistor M2A and a second pull-up control transistor M2B; the tank circuit 14 includes a storage capacitor C1;
the gate of the first pull-up control transistor M2A is electrically connected to the first control voltage terminal VDD _ a, the source of the first pull-up control transistor M2A is electrically connected to the first pull-up node PU, and the drain of the first pull-up control transistor M2A is electrically connected to the second pull-up node PU _ 1;
a gate of the second pull-up control transistor M2B is electrically connected to the second control voltage terminal VDD _ B, a source of the second pull-up control transistor M2B is electrically connected to the first pull-up node PU, and a drain of the second pull-up control transistor M2B is electrically connected to the second pull-up node PU _ 1;
a first end of the storage capacitor C1 is electrically connected to the second pull-up node PU _1, and a second end of the storage capacitor C1 is electrically connected to the gate driving signal output terminal OUT 1;
the second pull-up node reset circuit 40 includes a second pull-up node reset transistor M1;
the grid of the M1 is electrically connected with the first clock signal end, the drain of the M1 is electrically connected with the first pull-up node PU, and the source of the M1 is electrically connected with the INPUT end INPUT; the first clock signal terminal is used for providing a first clock signal CLKB;
the carry signal output circuit 41 includes a first carry signal output transistor M4, a second carry signal output transistor M8A and a third carry signal output transistor M8B, and the gate driving signal output circuit 42 includes a first gate driving output transistor M3, a second gate driving output transistor M9A and a third gate driving output transistor M9B;
the gate of the first carry signal output transistor M4 is electrically connected to the second pull-up node PU _1, the drain of the first carry signal output transistor M4 is electrically connected to the second clock signal terminal, and the source of the first carry signal output transistor M4 is electrically connected to the carry signal output terminal OUT _ C; the second clock signal terminal is used for providing a second clock signal CLK;
the gate of the second carry signal output transistor M8A is electrically connected to the first pull-down node PD _ a, the drain of the second carry signal output transistor M8A is electrically connected to the carry signal output terminal OUT _ C, and the source of the second carry signal output transistor M8A is electrically connected to the first low voltage terminal; the first low voltage terminal is used for providing a first low voltage LVGL;
the gate of the third carry signal output transistor M8B is electrically connected to the second pull-down node PD _ B, the drain of the third carry signal output transistor M8B is electrically connected to the carry signal output terminal OUT _ C, and the source of the third carry signal output transistor M8B is electrically connected to the first low voltage terminal;
the gate of the first gate driving output transistor M3 is electrically connected to the second pull-up node PU _1, the drain of the first gate driving output transistor M3 is electrically connected to the second clock signal terminal, and the source of the first gate driving output transistor M3 is electrically connected to the gate driving signal output terminal OUT 1;
the gate of the second gate driving output transistor M9A is electrically connected to the first pull-down node PD _ a, the drain of the second gate driving output transistor M9A is electrically connected to the gate driving signal output terminal OUT1, and the source of the second gate driving output transistor M9A is electrically connected to the second low voltage terminal; the second low voltage terminal is used for providing a second low voltage VGL;
the gate of the third gate driving output transistor M9B is electrically connected to the second pull-down node PD _ B, the drain of the third gate driving output transistor M9B is electrically connected to the gate driving signal output terminal OUT1, and the source of the third gate driving output transistor M9B is electrically connected to the second low voltage terminal.
In the embodiment shown in fig. 5, all transistors are NMOS transistors (NMOS transistors), but not limited thereto.
In the embodiment shown in fig. 5, LVGL is smaller than VGL to compensate for the stress of the first gate driving output transistor M3 included in the gate driving signal output circuit for outputting the gate driving signal during the non-output period, and to reduce the threshold voltage shift of the first gate driving signal output transistor M3.
As shown in fig. 6, when the embodiment of the gate driving unit of the present invention shown in fig. 5 is in operation,
in the INPUT stage S1, CLK is low, CLKB is high, VDD _ a provides high, VDD _ B provides low, INPUT provides high, M1 is on, PU ' S potential is high, M5A is on, M2A is on at the beginning of S1 to communicate between PU and PU _1 to boost PU _1 ' S potential for charging C1, when PU _1 ' S potential reaches a predetermined potential, M2A is off; M7A, M7B, M6A, and M6B are all on, the potential of PD _ a and the potential of PD _ B are both high voltage, and OUT1 and OUT _ C both output low voltage; the PD _ a and PD _ B function in the INPUT stage S1 not to pull down the potential of PU, but to charge PU in combination with INPUT, eliminating the risk of contention between pull-up and pull-down nodes in the prior art;
in the output stage S2, CLK is high, CLKB is low, VDD _ a provides high, VDD _ B provides low, INPUT provides low, M1 is off, M4 and M3 are on, OUT1 and OUT _ C both output high, the potential of PU _1 is bootstrapped up by C1, M6A and M6B are on, so that the potential of PD _ a and the potential of PD _ B are pulled down;
in the output stage S2, the gate potential of M2A is the high voltage provided by VDD _ a, the potential of the source of M2A is the potential of PU, the potential of the drain of M2A is the potential of PU _1 (the potential of PU _1 is higher than the potential of PU), so M2A is turned off, the potential of PU _1 can be further maintained, and M6A and M6B are fully turned on, and the potential of PD _ a and the potential of PD _ B are low voltages, so that M7A, M7B, M8A, M8B, M9A and M9B are all turned off;
in the reset phase S3, CLK is low, CLKB is high, VDD _ a provides high, VDD _ B provides low, INPUT provides low, M1 is turned on so that the potential of PU becomes low, M2A is turned on so that the potential of PU _1 becomes low, M5A is turned on, M6A and M6B are turned off, M5B is turned off, the potential of PD _ a is high, the potential of PD _ B is low, M8A and M9A are turned on, M8B and M9B are turned off, M3 and M4 are turned off, OUT _ C outputs LVGL, OUT1 outputs VGL;
before the next frame of signal comes or several frames of picture display time are passed again, the first control voltage provided by VDD _ A and the second control voltage provided by VDD _ B are subjected to high-low voltage conversion, so that the normal denoising function is maintained; and the PD _ A controlled denoising transistor and the PD _ B controlled denoising transistor can not cause the failure of a gate drive unit due to threshold voltage shift caused by long-time forward stress.
The embodiment of the gate driving unit shown in fig. 5 is operated, when the duty ratio of CLK and the duty ratio of CLKB are not 0.5, as shown in fig. 7, in the time period S0 between the input stage S1 and the output stage S2, the potential of PU _1 is not pulled too low due to the existence of M2A and M2B.
The embodiment of the utility model provides a gate drive unit at the during operation, when the duty cycle of the clock signal that gate drive unit adopted is less than 0.5, there is the time quantum between input stage and output stage, there is the time quantum between output stage and reset stage, the time quantum between input stage and output stage, and in the second time quantum between output stage and the reset stage, OUT1 output LVGL (the time quantum between input stage and output stage of the electric potential of CLK, and be LVGL in the second time quantum between output stage and the reset stage).
The embodiment of the gate driving unit shown in fig. 8 differs from the embodiment of the gate driving unit shown in fig. 5 in that: the gate of M1 is electrically connected to the Reset terminal Reset, the drain of M1 is electrically connected to the first pull-up node PU, and the source of M1 is electrically connected to the INPUT terminal INPUT;
the embodiment of the gate driving unit shown in fig. 8 of the present invention further includes a third pull-up node reset circuit 80;
the third pull-up node reset circuit 80 includes a third pull-up node reset transistor M10;
the gate of M10 is electrically connected to the frame reset terminal Total _ reset, the drain of M10 is electrically connected to the first pull-up node PU, and the source of M10 is electrically connected to the first low voltage terminal.
In the embodiment shown in fig. 8, M10 is an NMOS transistor, but not limited thereto.
In the embodiment of the gate driving unit shown in fig. 8, during the Reset phase, Reset provides high voltage, and M1 is turned on; in an inter-frame blank period (i.e., a blank period between two frame picture display times), Total _ reset supplies a high voltage, and M10 is turned on to reset the potential of PU.
The embodiment of the gate driving unit shown in fig. 9 differs from the embodiment of the gate driving unit shown in fig. 5 in that: the gate of M2A is electrically connected with PD _ A, and the gate of M2B is electrically connected with PD _ B;
furthermore, the embodiment of the gate driving unit shown in fig. 9 of the present invention further includes a first pull-up node reset circuit 20;
the first pull-up node reset circuit 20 includes a first pull-up node reset transistor M1B;
the gate of M1B is electrically connected to the Reset terminal Reset, the drain of M1B is electrically connected to the second pull-up node PU _1, and the source of M1B is connected to LVGL.
In the embodiment shown in fig. 9, M1B is an NMOS transistor, but not limited thereto.
The embodiment of the gate driving unit shown in fig. 9 of the present invention is working, when the duty ratio of CLK and the duty ratio of CLKB are not 0.5, as shown in fig. 10, in the time period S0 between the input stage S1 and the output stage S2, since the potential of PD _ a and the potential of PD _ B are low voltages (the potential of PD _ a is shown in fig. 10), the gate-source voltage of M2A and the gate-source voltage of M2B are small, so the leakage current of M2A and the leakage current of M2B are small, and the maintenance effect of the potential of PU _1 is good at S0; in addition, in the input stage, the potential of the PD _ a is higher than the voltage value of the control voltage provided by the VDD _ a, so that the charging effect on the PU _1 is better, and the potential of the PU _1 can be charged to a higher value.
The embodiment of the gate driving unit shown in fig. 11 is different from the embodiment of the gate driving unit shown in fig. 9 in that: the pull-down node control circuit includes a first pull-down control transistor M5A, a second pull-down control transistor M6A, a third pull-down control transistor M5B, a fourth pull-down control transistor M6B, a fifth pull-down control transistor M9A, a sixth pull-down control transistor M10A, a seventh pull-down control transistor M9B, and an eighth pull-down control transistor M10B, wherein,
the gate of M9A and the drain of M9A are both electrically connected to the first control voltage terminal VDD _ A;
the gate of M5A is electrically connected to the source of M9A, the drain of M5A is electrically connected to VDD _ A, and the source of M5A is electrically connected to the first pull-down node PD _ A;
the gate of M10A is electrically connected to the second pull-up node PU _1, and the drain of M10A is electrically connected to the source of M9A; the source of M10A is electrically connected to the INPUT terminal INPUT;
the gate of M6A is electrically connected to the second pull-up node PU _1, the drain of M6A is electrically connected to the first pull-down node PD _ A, and the source of M6A is electrically connected to the INPUT terminal INPUT;
the gate of M9B and the drain of M9B are both electrically connected to the second control voltage terminal VDD _ B;
the gate of M5B is electrically connected with the source of M9B, the drain of M5B is electrically connected with VDD _ B, and the source of M5B is electrically connected with the second pull-down node PD _ B;
the gate of M10B is electrically connected to the second pull-up node PU _1, the drain of M10B is electrically connected to the source of M9B, and the source of M10B is electrically connected to the INPUT terminal INPUT;
the gate of M6B is electrically connected to PU _1, the drain of M6B is electrically connected to the second pull-down node PD _ B, and the source of M6B is electrically connected to the INPUT terminal INPUT.
In the embodiment of the gate driving unit shown in fig. 11, M5A, M6A, M5B, M6B, M9A, M10A, M9B and M10B are all NMOS transistors, but not limited thereto.
The embodiment of the gate driving unit shown in fig. 11 of the present invention is operated, when the duty ratio of CLK and the duty ratio of CLKB are not 0.5, as shown in fig. 12, compared with fig. 10, in the output stage S2, the potential of PD _ a can be reduced to be low enough under the control of PU _1, so as not to affect the potential of PU _ 1.
The embodiment of the gate driving unit shown in fig. 13 is different from the embodiment of the gate driving unit shown in fig. 11 in that: the gate of M2A is electrically connected to VDD _ A, and the gate of M2B is electrically connected to VDD _ B.
The embodiment of the gate driving unit shown in fig. 13 of the present invention is operated, when the duty ratio of CLK and the duty ratio of CLKB are not 0.5, as shown in fig. 14, the potential of PU _1 does not drop too low in the time period S0 between the input stage S1 and the output stage S2.
Comparing fig. 14 and 12, with the embodiment of the gate driving unit shown in fig. 13, the potential of PU _1 is higher in the period S0, and the potential of PU _1 is higher in the output stage S2.
The embodiment of the utility model provides a gate drive circuit include multistage foretell gate drive unit.
In an embodiment of the present invention, the gate driving unit includes an input terminal and a carry signal output terminal;
and the input end of the grid driving unit is electrically connected with the carry signal output end of the adjacent upper-stage grid driving unit.
The embodiment of the utility model provides a display device include foretell gate drive circuit.
The embodiment of the utility model provides a display device can be any products or parts that have the display function such as cell-phone, panel computer, TV set, display, notebook computer, digital photo holder frame, navigator.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (14)
1. A grid driving unit is characterized by comprising a pull-up node denoising circuit, a pull-down node control circuit, a pull-up node control circuit and an energy storage circuit;
the pull-up node denoising circuit is respectively electrically connected with an input end, a pull-down node and a first pull-up node, and is used for controlling the connection or disconnection between the first pull-up node and the input end under the control of the potential of the pull-down node;
the pull-down node control circuit is respectively electrically connected with a second pull-up node, a pull-down node and the input end, is used for controlling the potential of the pull-down node under the control of control voltage provided by a control voltage end, and is used for controlling the connection or disconnection between the pull-down node and the input end under the control of the potential of the second pull-up node;
the pull-up node control circuit is respectively electrically connected with the anti-creeping control end, the first pull-up node and the second pull-up node, is used for controlling the connection or disconnection between the first pull-up node and the second pull-up node under the control of anti-creeping control voltage provided by the anti-creeping control end, and is used for maintaining the potential of the second pull-up node;
the energy storage circuit is electrically connected with the second pull-up node and used for storing electric energy.
2. The gate drive unit of claim 1, wherein the pull-up node denoising circuit is electrically connected to a pull-down node, the pull-up node denoising circuit comprising a pull-up node denoising transistor; the control electrode of the pull-up node denoising transistor is electrically connected with the pull-down node, the first electrode of the pull-up node denoising transistor is electrically connected with the pull-up node, and the second electrode of the pull-up node denoising transistor is electrically connected with the input end; alternatively, the first and second electrodes may be,
the pull-down nodes comprise a first pull-down node and a second pull-down node; the pull-up node denoising circuit comprises a first pull-up node denoising transistor and a second pull-up node denoising transistor; a control electrode of the first pull-up node denoising transistor is electrically connected with the first pull-down node, a first electrode of the first pull-up node denoising transistor is electrically connected with the pull-up node, and a second electrode of the first pull-up node denoising transistor is electrically connected with the input end; the control electrode of the second pull-up node denoising transistor is electrically connected with the second pull-down node, the first electrode of the second pull-up node denoising transistor is electrically connected with the pull-up node, and the second electrode of the second pull-up node denoising transistor is electrically connected with the input end.
3. A gate drive unit as claimed in claim 1, wherein the leakage prevention control terminal is the pull-down node;
the gate driving unit further comprises a first pull-up node reset circuit;
the first pull-up node reset circuit is respectively electrically connected with the reset end, the second pull-up node and the reset voltage end, and is used for controlling the second pull-up node to be connected or disconnected with the reset voltage end under the control of a reset signal provided by the reset end.
4. A gate drive unit as claimed in claim 1, wherein the leakage prevention control terminal is the control voltage terminal or the pull-down node;
the pull-up node control circuit comprises a pull-up control transistor, and the energy storage circuit comprises a storage capacitor;
a grid electrode of the pull-up control transistor is electrically connected with the control voltage end or the pull-down node, a first pole of the pull-up control transistor is electrically connected with the second pull-up node, and a second pole of the pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
5. The gate drive unit of claim 2, wherein the pull-down node comprises a first pull-down node and a second pull-down node, and the control voltage terminal comprises a first control voltage terminal and a second control voltage terminal;
the pull-down node control circuit is used for controlling the potential of the first pull-down node under the control of a first control voltage provided by the first control voltage end, controlling the connection or disconnection between the first pull-down node and an input end under the control of the second pull-up node, controlling the potential of the second pull-down node under the control of a second control voltage provided by the second control voltage end, and controlling the second pull-down node to be electrically connected with the input end under the control of the second pull-up node.
6. The gate drive unit of claim 5, wherein the pull-up node control circuit includes a first pull-up control transistor and a second pull-up control transistor; the energy storage circuit comprises a storage capacitor;
a control electrode of the first pull-up control transistor is electrically connected with the first pull-down node, a first electrode of the first pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the first pull-up control transistor is electrically connected with the first pull-up node;
a control electrode of the second pull-up control transistor is electrically connected with the second pull-down node, a first electrode of the second pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the second pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
7. The gate drive unit of claim 5, wherein the pull-up node control circuit comprises a first pull-up control transistor and a second pull-up control transistor, the tank circuit comprises a storage capacitor;
a control electrode of the first pull-up control transistor is electrically connected with a first control voltage end, a first electrode of the first pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the first pull-up control transistor is electrically connected with the first pull-up node;
a control electrode of the second pull-up control transistor is electrically connected with the second control voltage terminal, a first electrode of the second pull-up control transistor is electrically connected with the second pull-up node, and a second electrode of the second pull-up control transistor is electrically connected with the first pull-up node;
and the first end of the storage capacitor is electrically connected with the second pull-up node, and the second end of the storage capacitor is electrically connected with the gate drive signal output end.
8. The gate drive unit of claim 5, wherein the pull-down node control circuit comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor, and an eighth pull-down control transistor, wherein,
a control electrode of the fifth pull-down control transistor and a first electrode of the fifth pull-down control transistor are both electrically connected with a first control voltage terminal;
a control electrode of the first pull-down control transistor is electrically connected with a second electrode of the fifth pull-down control transistor, a first electrode of the first pull-down control transistor is electrically connected with the first control voltage terminal, and a second electrode of the first pull-down control transistor is electrically connected with the first pull-down node;
a control electrode of the sixth pull-down control transistor is electrically connected with the second pull-up node, and a first electrode of the sixth pull-down control transistor is electrically connected with a second electrode of the fifth pull-down control transistor; a second pole of the sixth pull-down control transistor is electrically connected with the input terminal;
a control electrode of the second pull-down control transistor is electrically connected with the second pull-up node, a first electrode of the second pull-down control transistor is electrically connected with the first pull-down node, and a second electrode of the second pull-down control transistor is electrically connected with the input end;
a control electrode of the seventh pull-down control transistor and a first electrode of the seventh pull-down control transistor are both electrically connected with a second control voltage terminal;
a control electrode of the third pull-down control transistor and a first electrode of the third pull-down control transistor are both electrically connected to a second electrode of the seventh pull-down control transistor, and the second electrode of the third pull-down control transistor is electrically connected to the second pull-down node;
a control electrode of the eighth pull-down control transistor is electrically connected with the second pull-up node, a first electrode of the eighth pull-down control transistor is electrically connected with a second electrode of the seventh pull-down control transistor, and the second electrode of the eighth pull-down control transistor is electrically connected with the input end;
and the control electrode of the fourth pull-down control transistor is electrically connected with the second pull-up node, the first electrode of the fourth pull-down control transistor is electrically connected with the second pull-down node, and the second electrode of the fourth pull-down control transistor is electrically connected with the input end.
9. The gate drive unit of any of claims 1 to 8, further comprising a second pull-up node reset circuit;
the second pull-up node reset circuit is electrically connected with the first pull-up node and is used for resetting the potential of the first pull-up node in a reset stage.
10. The gate drive unit of claim 9, wherein the second pull-up node reset circuit comprises a second pull-up node reset transistor;
a control electrode of the second pull-up node reset transistor is electrically connected with a first clock signal end, a first electrode of the second pull-up node reset transistor is electrically connected with the first pull-up node, a second electrode of the second pull-up node reset transistor is electrically connected with the input end or,
the control electrode of the second pull-up node reset transistor is electrically connected with the reset end, the first electrode of the second pull-up node reset transistor is electrically connected with the first pull-up node, and the second electrode of the second pull-up node reset transistor is electrically connected with the input end or the first low-voltage end.
11. The gate drive unit of any of claims 1 to 8, further comprising a third pull-up node reset circuit;
the third pull-up node reset circuit is respectively electrically connected with the interframe reset end, the first pull-up node and the first low-voltage end, and is used for controlling the connection or disconnection between the first pull-up node and the first low-voltage end in an interframe blank time period under the control of an interframe reset signal provided by the interframe reset end.
12. The gate drive unit of claim 1, further comprising a carry signal output circuit and a gate drive signal output circuit, wherein,
the carry signal output circuit is respectively electrically connected with a second pull-up node, a second clock signal end, a pull-down node, a carry signal output end and a first low voltage end, is used for controlling the carry signal output end to be electrically connected with the second clock signal end under the control of the potential of the second pull-up node, and is also used for controlling the carry signal output end to be connected or disconnected with the first low voltage end under the control of the potential of the pull-down node;
the grid driving signal output circuit is respectively electrically connected with a second pull-up node, a second clock signal end, a pull-down node, a grid driving signal output end and a second low voltage end, is used for controlling the grid driving signal output end to be electrically connected with the second clock signal end under the control of the potential of the second pull-up node, and is also used for controlling the grid driving signal output end to be connected with or disconnected from the second low voltage end under the control of the potential of the pull-down node;
the first low voltage provided by the first low voltage terminal is less than the second low voltage provided by the second low voltage terminal.
13. A gate drive circuit comprising a plurality of stages of gate drive units as claimed in any one of claims 1 to 12.
14. A display device comprising the gate driver circuit according to claim 13.
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| CN114495783A (en) * | 2020-10-27 | 2022-05-13 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit, gate driving method and display device |
| CN114495801A (en) * | 2022-03-10 | 2022-05-13 | 北京京东方显示技术有限公司 | Display device, grid drive circuit, shift register unit and drive method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114495783A (en) * | 2020-10-27 | 2022-05-13 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit, gate driving method and display device |
| CN114495801A (en) * | 2022-03-10 | 2022-05-13 | 北京京东方显示技术有限公司 | Display device, grid drive circuit, shift register unit and drive method thereof |
| CN114495801B (en) * | 2022-03-10 | 2023-11-28 | 北京京东方显示技术有限公司 | Display device, gate driving circuit, shift register unit and driving method thereof |
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