CN214067775U

CN214067775U - USB-to-TF card circuit

Info

Publication number: CN214067775U
Application number: CN202120385970.3U
Authority: CN
Inventors: 陈仁平; 王斌; 陈涛
Original assignee: Chengdu Lefan Information Technology Co ltd
Current assignee: Chengdu Lefan Information Technology Co ltd
Priority date: 2021-02-20
Filing date: 2021-02-20
Publication date: 2021-08-27
Anticipated expiration: 2031-02-20

Abstract

The utility model provides a USB changes TF card circuit, including USB signal input interface circuit, GL850 chip expander circuit, RTS5170 part circuit and TF card interface circuit, USB signal input interface circuit is connected with GL850 chip expander circuit, GL850 chip expander circuit and RTS5170 part circuit connection, RTS5170 part circuit and TF card interface circuit connection; the RTS5170 partial circuit comprises a chip U3, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21 and a voltage end + V3P3 SX; the GL850 chip expansion circuit comprises a chip U1, and the TF card interface circuit comprises a TF card socket J5. The utility model provides a present USB change TF card circuit's circuit structure all comparatively complicated, the device is many, leads to the bulky problem of PCB plate.

Description

USB-to-TF card circuit

Technical Field

The utility model relates to a USB technical field, TF card technical field, more specifically relate to a USB changes TF card circuit.

Background

USB, an abbreviation for Universal Serial Bus (USB), is an external Bus standard used to standardize the connection and communication between computers and external devices. Is an interface technology applied in the field of PC. The USB interface supports plug and play and hot plug functions of the device. USB was proposed by a combination of companies such as intel, compaq, IBM, Microsoft, etc. at the end of 1994.

A secure digital card, a new generation memory device based on a semiconductor flash memory, is widely used in portable devices, such as digital cameras, personal digital assistants (PDA for foreign language abbreviation), and multimedia players. An SD Card (Secure Digital Memory Card) is a Memory Card based on a semiconductor flash Memory process, and was essentially developed and completed by toshiba, a dominant concept in japan, and SanDisk corporation, a participant in toshiba, and usa in 1999. In 2000, the companies initiated and established the SD Association (SDA for short), which has a strong array capacity and attracted a large number of manufacturers. Including IBM, Microsoft, Motorola, NEC, Samsung, etc. Driven by these leaders, SD cards have become one of the most widely used memory cards in consumer digital devices today. The user can use a card reader of USB and use SD card on a personal computer. Some new computers have built-in card reading devices.

On ultra-small memory card products, the SD Association has first brought T-flash (TF card) into its family and named Micro SD, which replaces the Mini SD. Only fingernail-sized Micro SD was brought out in 2005 to surprise consumers. Such extremely small memory cards have become popular in 2008.

However, the current circuit structure of the circuit for converting the USB to the TF card is complex, and the number of devices is large, so that the volume of a PCB is large. Therefore, it is desirable to provide a circuit for converting USB to TF card to overcome the above problems.

SUMMERY OF THE UTILITY MODEL

The utility model provides a USB changes TF card circuit to the circuit structure who solves present USB and changes TF card circuit is all comparatively complicated, and the device is many, leads to the amasss big problem of PCB plate body.

In order to solve the technical problem, the utility model discloses the technical scheme who adopts is:

a USB-to-TF card circuit comprises a USB signal input interface circuit, a GL850 chip expansion circuit, an RTS5170 partial circuit and a TF card interface circuit, wherein the USB signal input interface circuit is connected with the GL850 chip expansion circuit, the GL850 chip expansion circuit is connected with the RTS5170 partial circuit, and the RTS5170 partial circuit is connected with the TF card interface circuit;

the RTS5170 partial circuit comprises a chip U3, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21 and a voltage end + V3P3 SX; the GL850 chip expansion circuit comprises a chip U1, and the TF card interface circuit comprises a TF card holder J5;

pin1 of chip U3 is connected to one end of resistor R16, the other end of resistor R16 is grounded, pin2 of chip U3 is connected to one end of resistor R17, the other end of resistor R17 is connected to pin 12 of chip U1, pin3 of chip U3 is connected to one end of resistor R18, the other end of resistor R18 is connected to pin13 of chip U1, pin 4 of chip U3 is connected to one end of capacitor 19, one end of capacitor 20 and voltage terminal + V3P3SX, the other end of capacitor 19 is connected to the other end of capacitor 20 and then grounded, pin5 of chip U3 is connected to pin 4 of TF card holder J5, pin6 of chip U3 is connected to one end of capacitor C21, the other end of capacitor C21 is grounded, pin 8 of chip U3 is connected to one end of resistor R3, the other end of resistor R3 is grounded, pin10 of chip U3 is connected to pin 8 of TF card holder J3, pin11 of chip U3 is connected to pin 369 of TF card holder J3 and pin3 is connected to chip holder J369. The 15 pins of the chip U3 are connected with the 5 pins of the TF card holder J5, the 18 pins of the chip U3 are connected with the 3 pins of the TF card holder J5, the 20 pins of the chip U3 are connected with the 2 pins of the TF card holder J5, the 21 pins of the chip U3 are connected with the 1 pin of the TF card holder J5, the 24 pins of the chip U3 are connected with one end of a capacitor C18, the other end of the capacitor C18 is grounded, and the 25 pins of the chip U3 are grounded.

Furthermore, the USB signal input interface circuit includes an FPC holder J4, a voltage terminal + V5P0A and a voltage terminal + V3P3SX, wherein pin1 and pin2 of FPC holder J4 are connected to pin + V5P0A, pin3 of FPC holder J4 is connected to pin1 of chip U1, pin 4 of FPC holder J4 is connected to pin2 of chip U1, pin5 and pin6 of FPC holder J4 are connected to ground, pin15, pin 16 and pin 17 of FPC holder J4 are connected to pin + V3P3SX, pin18, pin 19 and pin20 of FPC holder J4 are connected to ground, and pin21 and pin 22 of FPC holder J4 are connected to ground.

Further, the GL850 chip expansion circuit further includes a crystal oscillator U2, a capacitor C2, a resistor R2, a voltage terminal HUB _3V 2 and a voltage terminal HUB _5V, wherein 8 pins of the chip U2 are connected to one end of the resistor R2, the other end of the resistor R2 is grounded, 5 pins, 9 pins and 14 pins of the chip U2 are connected to one end of the capacitor C2 and one end of the voltage terminal HUB _3V 2, the other end of the capacitor C2 is grounded, 10 pins of the chip U2 are connected to pin1 of the crystal oscillator U2 and one end of the capacitor C2, 11 pins of the chip U2 are connected to one end of the 3 pin of the crystal oscillator U2 and one end of the capacitor C2, the other end of the capacitor C2, the pin2 pin of the crystal oscillator U2 and the pin 4 pin are connected to the ground, the other end of the resistor R2, the other end of the capacitor C2 is connected to one end of the capacitor C2, and the other end of the resistor R2, and the other end of the resistor R2 are connected to the capacitor C2, and the other end of the resistor R2 are connected to the other end 2, chip U1's 21 pin all with electric capacity C10 one end, resistance R6 one end, resistance R7 one end, resistance R8 one end and voltage end HUB _3V3 are connected, electric capacity C10 other end ground connection, chip U1's 22 pin and resistance R8 other end are connected, chip U1's 23 pin and resistance R7 other end are connected, chip U1's 25 pin and resistance R6 other end are connected, chip U1's 27 pin and voltage end HUB _5V are connected, chip U1's 28 pin and voltage end HUB _3V3 are connected, chip U1's 29 pin ground connection.

Furthermore, the TF card interface circuit further includes an ESD diode V5, an ESD diode V6, an ESD diode V7, an ESD diode V8, an ESD diode V9, an ESD diode V10, an ESD diode V11, an ESD diode V12, a capacitor C22 and a capacitor C23, wherein a pin1 of the TF card holder J23 is connected to one end of the ESD diode V23, the other end of the ESD diode V23 is grounded, a pin2 of the TF card holder J23 is connected to one end of the ESD diode V23, the other end of the ESD diode V23 is grounded, a pin3 of the TF card holder J23 is connected to one end of the ESD diode V23, the other end of the ESD diode V23 is grounded, a pin5 of the TF card holder J23 is connected to one end of the ESD diode V23, the other end of the ESD diode V23 is grounded, a pin 7 of the TF card holder J23 is connected to one end of the ESD diode V23, the other end of the ESD diode V23 is grounded, the pin 8 of the TF card holder J23 is connected to one end of the ESD diode V23, and the ESD diode V23 is connected to the ESD card holder 23, the ESD diode V23, the other end of the ESD diode V23 is connected to the ESD card holder 23, the other end of the ESD diode V8 is grounded, 4 pins of the TF card socket J5 are connected with one end of the ESD diode V12, one end of the capacitor 22 and one end of the capacitor C23, the other end of the ESD diode V12, the other end of the capacitor 22 and the other end of the capacitor C23 are grounded after being connected, 6 pins of the TF card socket J5 are grounded, 10 pins and 11 pins of the TF card socket J5 are grounded after being connected, and 12 pins and 13 pins of the TF card socket J5 are grounded after being connected.

Furthermore, the circuit for converting the USB to the TF card further comprises a TP interface circuit, the TP interface circuit comprises an FPC seat J3, a resistor R14, a resistor R15 and a voltage end + V3P3SX, a pin1 and a pin2 of the FPC seat J3 are connected and then connected with the voltage end + V3P3SX, a pin3 and a pin 4 of the FPC seat J3 are connected and then grounded, a pin 7 of the FPC seat J3 is connected with one end of the resistor R14, a pin 8 of the FPC seat J3 is connected with one end of a resistor R15, the other end of the resistor R14 is connected with a pin 7 of the chip U1, the other end of the resistor R15 is connected with a pin6 of the chip U1, a pin10 of the FPC seat J3 is grounded, and a pin13 and a pin 14 of the FPC seat J3 are connected and then grounded.

Furthermore, the GL850 chip expansion circuit further includes a voltage terminal + V5P0A, a capacitor C14, a capacitor C15, a capacitor C16 and a resistor R13, wherein one end of the resistor R13 is connected to the voltage terminal HUB _5V, one end of the capacitor C14 is connected to one end of the capacitor C15, the other end of the resistor R13 is connected to the voltage terminal + V5P0A and the capacitor C16, the other end of the capacitor C14 is connected to the other end of the capacitor C15 and then grounded, and the other end of the capacitor C16 is grounded.

Compared with the prior art, the utility model discloses following beneficial effect has: the utility model has the advantages that by arranging the USB signal input interface circuit, the GL850 chip expansion circuit, the RTS5170 partial circuit and the TF card interface circuit, the RTS5170 chip has a high-speed, stable and self-contained power supply adjusting circuit, and the peripheral circuit is simple and reliable during use and has good practicability; RTS5170 QFN24 packaging is adopted, so that the PCB layout and wiring space is saved; the RTS5170 peripheral circuit is optimized, the complexity is reduced in complicated peripheral circuits, and only pins meeting the TF function are used on a chip, so that the circuit is simple and comprehensive, and the material cost is greatly saved.

By applying the RTS5170 chip, the chip has the advantages of no crystal oscillator, integration of a 3.3V-to-1.8V regulator, support of high-speed USB2.0 and the like. The product using the circuit for converting the USB to the TF card is simple, and meanwhile, the transmission quality can be guaranteed. The practical requirement of the notebook expansion small plate on the daily TF card can be met. In addition, as the RTS5170 adopts a QFN24 package, the volume occupation is very small, and the PCB space is greatly saved. The USB 2.0-to-TF card conversion is realized, and the USB2.0 signal is converted into a signal identified by the TF card through a USB-to-TF card chip. □ stably reading the data in the TF card; obtaining a relatively stable reading speed through actual measurement, wherein the average speed is 37.4 MB/S; the circuit is simple and reliable, and important elements only need one USB interface, one RTS5170 chip and one TF card holder. The peripheral devices are few, and all the peripheral devices are integrated chips, so that the reliability of the circuit is greatly improved.

Drawings

Fig. 1 is a schematic circuit diagram of a part of the RTS5170 circuit of the present invention.

Fig. 2 is a schematic circuit diagram of the USB signal input interface circuit of the present invention.

Fig. 3 is a circuit diagram of the GL850 chip expansion circuit of the present invention.

Fig. 4 is a schematic circuit diagram of the TF card interface circuit of the present invention.

Fig. 5 is a schematic circuit diagram of the TP interface circuit of the present invention.

Fig. 6 is a circuit diagram of a WWAN interface circuit according to the present invention.

Detailed Description

The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description.

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined to clearly and completely describe the technical solutions of the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.

In the description of the present invention, it is to be understood that the terms indicating orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of description, and do not indicate or imply that the equipment or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present application, unless expressly stated or limited otherwise, the presence of a first feature above or below a second feature may encompass direct contact of the first and second features, and may also encompass contact of the first and second features not being in direct contact, but via additional features between them. Also, the first feature being above, on or above the second feature includes the first feature being directly above and obliquely above the second feature, or merely means that the first feature is at a higher level than the second feature. Including a first feature being directly below and obliquely below a second feature, or simply indicating that the first feature is at a lesser elevation than the second feature, if present below, under or below the second feature.

The present invention will be further described with reference to the following examples, which are only some, but not all, of the examples of the present invention. Based on the embodiments in the present invention, other embodiments used by those skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1 to 6, an embodiment of the present invention is shown for illustration purposes, and is not limited to the structure.

Example one

As shown in fig. 1, fig. 2, fig. 3 and fig. 4, a USB to TF card circuit includes a USB signal input interface circuit, a GL850 chip extension circuit, an RTS5170 circuit and a TF card interface circuit, wherein the USB signal input interface circuit is connected to the GL850 chip extension circuit, the GL850 chip extension circuit is connected to the RTS5170 circuit, and the RTS5170 circuit is connected to the TF card interface circuit;

as shown in fig. 1, the RTS5170 partial circuit includes a chip U3, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, and a voltage terminal + V3P3 SX; as shown in fig. 3, the GL850 chip extension circuit includes a chip U1, and as shown in fig. 4, the TF card interface circuit includes a TF card socket J5;

As shown in fig. 2, the USB signal input interface circuit includes FPC holder J4, voltage terminal + V5P0A and voltage terminal + V3P3SX, pin1 and pin2 of FPC holder J4 are connected to voltage terminal + V5P0A, pin3 of FPC holder J4 is connected to pin1 of chip U1, pin 4 of FPC holder J4 is connected to pin2 of chip U1, pin5 and pin6 of FPC holder J4 are connected to ground, pin15, pin 16 and pin 17 of FPC holder J4 are connected to voltage terminal + V3P3SX, pin18, pin 19 and pin20 of FPC holder J4 are connected to ground, and pin21 and pin 22 of FPC holder J4 are connected to ground.

As shown in fig. 3, the GL850 chip expansion circuit further includes a crystal oscillator U2, a capacitor C1, a capacitor C10, a capacitor C11, a resistor R11, a voltage terminal HUB _3V 11 and a voltage terminal HUB _5V, wherein pin 8 of the chip U11 is connected to one end of the resistor R11, the other end of the resistor R11 is grounded, pins 5, 9 and 14 of the chip U11 are connected to one end of the capacitor C11 and one end of the voltage terminal HUB _3V 11, the other end of the capacitor C11 is grounded, pin10 of the chip U11 is connected to pin1 of the crystal oscillator U11 and one end of the capacitor C11, pin11 of the chip U11 is connected to pin3 of the crystal oscillator U11 and one end of the capacitor C11, the other end of the capacitor C11, the pin2 of the crystal oscillator U11 and one end of the capacitor C11 are connected to ground, and one end of the capacitor C11 are connected to the other end of the capacitor C11, and one end of the other end of the capacitor C11 are connected to the other end 11, the other end of the resistor R12 is connected with a voltage end HUB _5V, the 21 pins of the chip U1 are connected with one end of a capacitor C10, one end of a resistor R6, one end of a resistor R7, one end of a resistor R8 and the voltage end HUB _3V3, the other end of the capacitor C10 is grounded, the 22 pins of the chip U1 are connected with the other end of a resistor R8, the 23 pins of the chip U1 are connected with the other end of a resistor R7, the 25 pins of the chip U1 are connected with the other end of a resistor R6, the 27 pins of the chip U1 are connected with a voltage end HUB _5V, the 28 pins of the chip U1 are connected with a voltage end HUB _3V3, and the 29 pins of the chip U1 are grounded.

As shown in fig. 4, the TF card interface circuit further includes an ESD diode V5, an ESD diode V6, an ESD diode V7, an ESD diode V8, an ESD diode V9, an ESD diode V10, an ESD diode V11, an ESD diode V12, a capacitor C22, and a capacitor C23, wherein pin1 of TF card holder J5 is connected to one end of ESD diode V5, the other end of ESD diode V5 is grounded, pin2 of TF card holder J5 is connected to one end of ESD diode V6, the other end of ESD diode V6 is grounded, pin3 of TF card holder J6 is connected to one end of ESD diode V6, the other end of ESD diode V6 is grounded, pin5 of TF card holder J6 is connected to one end of ESD diode V6, the other end of ESD diode V6 is connected to one end of ESD diode V6, the pin 7 of TF card holder J6 is connected to one end of ESD diode V6, the other end of ESD diode V6 is grounded, the 9 pin of the TF card holder J5 is connected with one end of an ESD diode V8, the other end of the ESD diode V8 is grounded, the 4 pin of the TF card holder J5 is connected with one end of an ESD diode V12, one end of a capacitor 22 and one end of a capacitor C23, the other end of the ESD diode V12, the other end of the capacitor C23 are grounded after being connected, the 6 pin of the TF card holder J5 is grounded, the 10 pin and the 11 pin of the TF card holder J5 are grounded after being connected, and the 12 pin and the 13 pin of the TF card holder J5 are grounded after being connected.

The circuit for converting the USB to the TF card further comprises a TP interface circuit, as shown in FIG. 5, the TP interface circuit comprises an FPC seat J3, a resistor R14, a resistor R15 and a voltage end + V3P3SX, wherein a pin1 and a pin2 of the FPC seat J3 are connected and then connected with the voltage end + V3P3SX, a pin3 and a pin 4 of the FPC seat J3 are connected and then grounded, a pin 7 of the FPC seat J3 is connected with one end of the resistor R14, a pin 8 of the FPC seat J3 is connected with one end of a resistor R15, the other end of the resistor R14 is connected with a pin 7 of the chip U1, the other end of the resistor R15 is connected with a pin6 of the chip U1, a pin10 of the FPC seat J3 is grounded, and a pin13 and a pin 14 of the FPC seat J3 are connected and then grounded.

As shown in fig. 3, the GL850 chip expansion circuit further includes a voltage terminal + V5P0A, a capacitor C14, a capacitor C15, a capacitor C16, and a resistor R13, wherein one end of the resistor R13 is connected to the voltage terminal HUB _5V, one end of the capacitor C14 is connected to one end of the capacitor C15, the other end of the resistor R13 is connected to the voltage terminal + V5P0A and the capacitor C16, the other end of the capacitor C14 is connected to the other end of the capacitor C15 and then grounded, and the other end of the capacitor C16 is grounded.

Example two

The second embodiment is a further optimization of the first embodiment.

The USB to TF card circuit further includes a WWAN interface circuit, as shown in fig. 6, the WWAN interface circuit includes a connector J1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R10, a resistor R11, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an LED indicator DL1, an ESD diode V1, an ESD diode V2, an ESD diode V3, an ESD diode V4, a card holder J2, a voltage terminal + V3P3_4G, a voltage terminal + VCC _ VCC, and a SIM voltage terminal + V3P3SX, a pin 7 of the connector J SX is connected to one end of the resistor R SX, the other end of the resistor R SX is connected to a pin 4 of the chip U SX, a pin of the connector J369 is connected to one end of the connector J SX, a pin of the resistor R SX is connected to one end of the FPC SX, a pin of the resistor J SX is connected to one end of the resistor J SX, and a pin of the resistor J SX is connected to one end of the connector J SX, a pin of the resistor J SX is connected to the pin of the FPC connector J SX, a pin of the FPC connector J SX, the other end of the resistor R11 is connected with a voltage terminal + V3P3_4G, the 3 pin, the 5 pin, the 11 pin, the 27 pin, the 33 pin, the 39 pin, the 45 pin, the 51 pin, the 57 pin, the 71 pin, the 73 pin, the G1 pin and the G2 pin of the connector J1 are connected and then grounded, the 2 pin and the 4 pin of the connector J1 are connected and then connected with a voltage terminal + V3P3_4G, the 6 pin of the connector J1 is connected with the 9 pin of the FPC holder J4, the 8 pin of the connector J1 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the 8 pin of the FPC holder J4, the 10 pin of the connector J1 is connected with the negative pole of the LED indicator lamp DL1, the positive pole of the LED indicator lamp DL1 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with the voltage terminal + V3P3_4G, the 30 pin of the connector J1 is connected with one end of the voltage terminal V2 pin and the ESD 8653 pin of the ESD diode holder J828653, pins 32 of a connector J1 are connected with one end of an ESD diode V1 and a pin C1 of a card socket J1, the other end of the ESD diode V1 is grounded, pins 34 of the connector J1 are connected with one end of the ESD diode V1 and a pin C1 of the card socket J1, the other end of the ESD diode V1 is grounded, pins 36 of the connector J1 are connected with a voltage terminal + VCC _ SIM, one end of a capacitor C1, one end of the ESD diode V1 and a pin C1 of the card socket J1, the other end of the capacitor C1 is connected with the other end of the ESD diode V1 and then grounded, pins 70, 72 and 74 of the connector J1 are connected with a voltage terminal + V3P 1 _4G, a pin GND1 of the card socket J1 and a pin GND1 of the card socket J1 are connected and then grounded, one end of the resistor R1 is connected with the voltage terminal + V3P 1, one end of the resistor R1, one end of the capacitor C1, and one end of the capacitor C1 and one end of, One end of a capacitor C6, one end of a capacitor C7, one end of a capacitor C8 and one end of a capacitor C9 are connected with a voltage end + V3P3_4G, and the other end of a capacitor C2, the other end of a capacitor C3, the other end of a capacitor C4, the other end of a capacitor C5, the other end of a capacitor C6, the other end of a capacitor C7, the other end of a capacitor C8 and the other end of a capacitor C9 are connected and then grounded.

The principle of the utility model is as follows:

in the USB signal input interface circuit, the utility model discloses used 3.3V power signal + V3P3SX, USB2_ P4_ WWAN _ DN _ C signal, USB2_ P4_ WWAN _ DP _ C signal and power ground GND in this circuit. These four signals are a complete set of USB signals. The DM and DP of the RTS5170 chip may be directly input. Here, the signal is expanded into four output signals due to the need of an expansion board, wherein one output signal (DM3 and DP3) is used as the input of DM and DP of the RTS5170 chip.

In the GL850 chip extension circuit, DM0 and DP0 are USB interface input signals, and here, 4 USB signals are extended through one GL850 chip, and here, the chip connected to RTS5170 uses HUB _ DN3_ TF and HUB _ DP3_ TF signals. The principle is consistent with the USB2_ P4_ WWAN _ DN _ C signal, and the USB2_ P4_ WWAN _ DP _ C signal directly connected to the RTS5170 chip.

In RTS5170, part of the circuit is the core circuit of the present invention. Pin1 is a chip reference Pin and indicates that a 6.2K resistor is required to be connected to ground according to the manual. Wherein Pin2 and Pin3 are USB signal inputs. Here, R17 and R18 are 0R resistors, which are used for impedance matching and for facilitating signal debugging later. Pin5 is the 3.3V power supply of this chip output, supplies power for the TF card on the TF cassette and uses. Pin6 is an internal regulator, and according to the manual, needs to be connected to a capacitor to ground. Pin9 is a TF card write protection Pin, active high. For normal read and write operations, a 0R resistor is connected to ground. Pin11, Pin10, Pin21, and Pin20 are TF card data pins DAT0-DAT 3. Pin13 is a TF card insertion detection Pin, Pin15 is a clock Pin, and Pin18 is a command signal Pin of the TF card. Pin24 is an internal 3.3V to 1.8V Pin, and needs to be connected with a capacitor when in use. Wherein, C19, C20 are power input filter capacitors, and can achieve the purposes of reducing ripple and stabilizing voltage.

In the TF card interface circuit, J5 is a TF card holder, and V5, V6, V7, V8, V9, V10, V11 and V12 are ESD diodes. Because the static electricity carried by human body can affect the circuit when inserting or pulling TF, the ESD protection treatment is carried out. C22 and C23 are power supply filter capacitors. The rest signal lines are correspondingly connected with the signal lines of the RTS5170 chip.

The above-mentioned embodiments are provided for illustration and not for limitation, and the changes of the examples and the replacement of equivalent elements should be understood as belonging to the scope of the present invention. From the above detailed description, it will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential attributes thereof.

While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention. The above description is only exemplary of the present invention and should not be taken as limiting, and all changes, equivalents, and improvements made within the spirit and principles of the present invention should be understood as being included in the scope of the present invention.

Claims

1. A USB-to-TF card circuit is characterized by comprising a USB signal input interface circuit, a GL850 chip expansion circuit, an RTS5170 partial circuit and a TF card interface circuit, wherein the USB signal input interface circuit is connected with the GL850 chip expansion circuit, the GL850 chip expansion circuit is connected with the RTS5170 partial circuit, and the RTS5170 partial circuit is connected with the TF card interface circuit;

2. The circuit of claim 1, wherein the USB signal input interface circuit comprises FPC holder J4, voltage terminal + V5P0A and voltage terminal + V3P3SX, wherein pin1 and pin2 of FPC holder J4 are connected to voltage terminal + V5P0A, pin3 of FPC holder J4 is connected to pin1 of chip U1, pin 4 of FPC holder J4 is connected to pin2 of chip U1, pin5 and pin6 of FPC holder J4 are connected to ground, pin15, pin 16 and pin 17 of FPC holder J4 are connected to voltage terminal + V3P3SX, pin18, pin 19 and pin20 of FPC holder J4 are connected to ground, and pin21 and pin 22 of FPC holder J4 are connected to ground.

3. The circuit of claim 2, wherein the GL850 chip expansion circuit further comprises a crystal oscillator U2, a capacitor C1, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R6, a voltage terminal HUB _3V 6 and a voltage terminal HUB _5V, wherein the pin 8 of the chip U6 is connected to one end of the resistor R6, the other end of the resistor R6 is grounded, the pins 5, 9 and 14 of the chip U6 are connected to one end of the capacitor C6 and the voltage terminal HUB _3V 6, the other end of the capacitor C6 is grounded, the pin10 of the chip U6 is connected to one end of the pin1 of the crystal oscillator U6 and one end of the capacitor C6, the pin11 of the chip U6 is connected to the pin3 of the crystal oscillator U6 and one end of the capacitor C6, the other end of the capacitor C6, the pin10 of the capacitor U6, the pin of the capacitor U6 and the pin6 are connected to one end of the capacitor C3617, and the pin of the chip U6, and the pin of the chip 3617 are connected to the other end of the capacitor C6, capacitor C13 other end ground connection, the resistance R12 other end is connected with voltage end HUB _5V, chip U1's 21 pin all with electric capacity C10 one end, resistance R6 one end, resistance R7 one end, resistance R8 one end and voltage end HUB _3V3 are connected, electric capacity C10 other end ground connection, chip U1's 22 pin and resistance R8 other end are connected, chip U1's 23 pin and resistance R7 other end are connected, chip U1's 25 pin and resistance R6 other end are connected, chip U1's 27 pin and voltage end HUB _5V are connected, chip U1's 28 pin and voltage end HUB _3V3 are connected, chip U1's 29 pin ground connection.

4. A circuit from a USB to a TF card according to claim 3, wherein the TF card interface circuit further includes ESD diode V5, ESD diode V6, ESD diode V7, ESD diode V8, ESD diode V9, ESD diode V10, ESD diode V11, ESD diode V12, capacitor C22, and capacitor C23, a pin1 of TF card holder J5 is connected to one end of ESD diode V5, the other end of ESD diode V5 is grounded, a pin2 of TF card holder J5 is connected to one end of ESD diode V6, the other end of ESD diode V6 is grounded, a pin3 of TF card holder J5 is connected to one end of ESD diode V7, the other end of ESD diode V7 is grounded, a pin5 of TF card holder J7 is connected to one end of ESD diode V7, the other end of ESD diode V7 is grounded, a pin 7 of TF card holder J7 is connected to one end of ESD diode V7, the other end of diode V7 is grounded, and a pin of TF card holder J7 is connected to one end of TF card holder V7, the other end of the ESD diode V9 is grounded, pin9 of the TF card holder J5 is connected with one end of the ESD diode V8, the other end of the ESD diode V8 is grounded, pin 4 of the TF card holder J5 is connected with one end of the ESD diode V12, one end of the capacitor 22 and one end of the capacitor C23, the other end of the ESD diode V12, the other end of the capacitor 22 and the other end of the capacitor C23 are grounded after being connected, pin6 of the TF card holder J5 is grounded, pin10 and pin11 of the TF card holder J5 are grounded after being connected, and pin 12 and pin13 of the TF card holder J5 are grounded after being connected.

5. A circuit from USB to TF card according to claim 4, wherein said circuit from USB to TF card further comprises TP interface circuit, said TP interface circuit comprises FPC holder J3, resistor R14, resistor R15 and voltage terminal + V3P3SX, pin1 and pin2 of FPC holder J3 are connected to voltage terminal + V3P3SX, pin3 and pin 4 of FPC holder J3 are connected to ground, pin 7 of FPC holder J3 is connected to one end of resistor R14, pin 8 of FPC holder J3 is connected to one end of resistor R15, the other end of resistor R14 is connected to pin 7 of chip U1, the other end of resistor R15 is connected to pin6 of chip U1, pin10 of FPC holder J3 is connected to ground, and pin13 and pin 14 of FPC holder J3 are connected to ground.

6. The circuit of claim 5, wherein the GL850 chip expansion circuit further comprises a voltage terminal + V5P0A, a capacitor C14, a capacitor C15, a capacitor C16 and a resistor R13, one end of the resistor R13 is connected with the voltage terminal HUB _5V, one end of the capacitor C14 is connected with one end of the capacitor C15, the other end of the resistor R13 is connected with the voltage terminal + V5P0A and the capacitor C16, the other end of the capacitor C14 is connected with the other end of the capacitor C15 and then grounded, and the other end of the capacitor C16 is grounded.