CN214042304U

CN214042304U - Main board circuit for remotely updating BIOS chip on line based on server

Info

Publication number: CN214042304U
Application number: CN202023135371.0U
Authority: CN
Inventors: 付迪; 陈泽鑫; 冯建东; 杨碧雁; 江志容; 黄凤翔; 张伟
Original assignee: Guangzhou Chaoyun Technology Co ltd
Current assignee: Guangzhou Chaoyun Technology Co ltd
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2021-08-24
Anticipated expiration: 2030-12-23

Abstract

A BIOS chip remote online updating mainboard circuit based on a server; the system comprises a Feiteng processor, a CPLD unit module, a BIOS chip, a BMC management chip, an RGMII PHY chip and an RJ45 kilomega management network port; the CPLD unit module and the BMC management chip flexibly switch and connect the BIOS chip to the Feiteng processor or the BMC management chip through different states of GPIO interfaces between the CPLD unit module and the BMC management chip, and the function of simultaneously remotely upgrading the two BIOS chips on line is realized. The utility model combines a single GPIO interface with the CPLD unit module through the BMC management chip on the basis of the Feiteng server, solves the problems of time and labor consumption of local off-line burning of the BIOS chip in the prior art, and overcomes the defect that the BMC management chip can not debug the whole system in real time in the remote debugging process; the utility model relates to a simply, the cost is lower, has reduced mainboard fault response time, has reduced the work load that the server was maintained, has improved the reliability and the degree of safety of server.

Description

Main board circuit for remotely updating BIOS chip on line based on server

Technical Field

The utility model relates to a computer motherboard design field especially relates to a BIOS chip remote online update's mainboard circuit based on server.

Background

In recent years, with the improvement of the information technology level, the application of servers is more and more extensive, and the problem of national information security is more and more emphasized in all countries of the world. In the current domestic server market, most market shares are mainly foreign brands, and based on the aspect of national information security, the localization of the server is accelerated, and the information security construction is strengthened. At present, a large number of domestic servers emerge under the national information security, the fault debugging technical schemes are different, and can be roughly divided into local debugging and remote debugging, and the local debugging needs technical personnel to carry out fault troubleshooting and debugging on site, so that the time and labor are consumed, and the management difficulty is large; the other method is to debug the server in a remote mode, but the existing remote debugging FT-S2500 home server has the defects that a BMC management chip cannot debug the whole server system in real time in the remote debugging process and the cost of the design of the mainboard hardware is high, so that the problem to be solved urgently in the field of home servers is solved.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a BIOS chip remote online update's mainboard circuit based on server to solve the aforementioned problem that exists among the prior art.

In order to realize the purpose, the utility model discloses a technical scheme as follows:

a mainboard circuit for remote online updating of a BIOS chip based on a server comprises a processor, a CPLD unit module, the BIOS chip, a BMC management unit, an RGMII PHY chip and a gigabit management network port; the CPLD unit module is respectively connected with the processor and the BIOS chip through an SPI bus; the CPLD unit is connected with the BMC management unit through the SPI bus and a GPIO bus; the BMC management unit mounts the RGMII PHY chip, is connected with the gigabit management network port through the RGMII PHY chip and provides high-speed network transmission for remote online updating of the BIOS chip.

Preferably, the CPLD unit module is connected with two processors and two BIOS chips; the processor includes a CPU1 and a CPU 2; the BIOS chip includes BIOS1 and BIOS 2.

Preferably, the CPLD unit module is provided with 5 SPI interfaces and a GPIO interface; the processor and the BIOS chip are both provided with the SPI interface; the BMC management unit is provided with the SPI interface and the GPIO interface.

Preferably, the BMC management chip is integrated with an RGMII serial port, and the RGMII PHY chip is mounted through an RGMII bus to provide high-speed network transmission for remote online update of the BIOS chip.

Preferably, the CPLD unit module and the BMC management unit switch the connection mode of the SPI interface in the CPLD unit module through the operating state of the GPIO interface.

The utility model has the advantages that: the utility model discloses a mainboard circuit for remote online update of a BIOS chip based on a server, which expands the performance of a BMC management chip through a CPLD unit module, solves the problem that the BMC management chip can not debug the whole system in real time in the remote debugging of the existing domestic server, and meets the use requirements of users on storage products; the utility model relates to a simply, the cost is lower, the integrated level is high.

Drawings

Fig. 1 is a motherboard line connection topology.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are given by way of illustration only.

A mainboard circuit for remote online update of a BIOS chip based on a server is shown in figure 1 and comprises two processors, a CPLD unit module, two BIOS chips, a BMC management unit, an RGMII PHY chip and a gigabit management network port; the processor comprises a CPU1 and a CPU2, the BIOS chip comprises a BIOS1 and a BIOS 2; the CPLD unit module is provided with 5 SPI interfaces and 1 GPIO interface, the BMC management unit is provided with an SPI interface, a GPIO interface and an RGMII serial port, and the processor and the BIOS chip are provided with the SPI interfaces; the SPI interface in the CPLD unit module is respectively connected with the SPI interfaces in the CPU1, the CPU2, the BIOS1, the BIOS2 and the BMC management unit through SPI buses; the GPIO interface in the BMC management unit is connected with the GPIO interface in the CPLD unit module through the GPIO bus, and the BMC management unit switches the connection mode of the SPI interface in the CPLD unit module by controlling the working state of the GPIO interface, so that the BIOS chip is controlled to be flexibly switched and connected to the corresponding processor and the BMC management unit; the BMC management unit is further integrated with an RGMII serial port, and the BMC management unit mounts the RGMII chip by using the RGMII bus through the RGMII serial port to realize a gigabit service network port and provide high-rate network transmission for remote online update of the BIOS chip; the RGMII PHY chip is connected with the kilomega management network port.

The working principle of the mainboard circuit for remotely updating the BIOS chip on line based on the server is as follows: the BMC management unit provides high-speed network transmission for remote online updating of the BIOS chip through the mounted RGMII PHY chip, so that a kilomega service network port is realized; the BMC management unit controls the working state of the GPIO interface to control and switch the connection relation of the SPI interface in the CPLD unit module; the switching truth table of the SPI is as follows:

Nu.	BMC _ GPIO State	BIOS1 chip connection	BIOS2 chip connection	Remarks for note
					1	1	CPU1	CPU2	Normal starting up
2	0	BMC	CPU2	Updating BIOS1 online
					3	Fang Bo	CPU1	BMC	Updating BIOS2 online

When the GPIO interface is 1, the BIOS1_ SPI is interconnected with the CPU1_ SPI, the BIOS2_ SPI is interconnected with the CPU2_ SPI, and the machine is normally started; when the GPIO interface is 0, the BIOS1_ SPI is interconnected with the BMC _ SPI, the BIOS2_ SPI is interconnected with the CPU2_ SPI, and the BMC management unit starts updating the BIOS1 online; when the GPIO interface is square wave, the BIOS1_ SPI is interconnected with the CPU1_ SPI, the BIOS2_ SPI is interconnected with the BMC _ SPI, and the BMC management unit starts to update the BIOS2 online; after the two BIOS chips are updated, the GPIO interface is changed into 1, and the machine can be normally started.

The CPLD is a digital integrated circuit which is used by a user to construct logic functions according to respective needs; the BMC is a substrate management controller; the RGMII is a gigabit medium independent interface, adopts a 4-bit data interface, has a working clock of 125MHz, and simultaneously transmits data on a rising edge and a falling edge, so that the transmission rate can reach 1000 Mbps; the PHY chip is a port physical layer; the BIOS is a basic input and output system; the SPI interface is a serial peripheral interface.

Examples

In the embodiment, a Feiteng S2500 processor is adopted, and RJ45 kilomega is adopted to manage a network port; the CPLD unit module adopts a MAX II CPLD EPM2210F324 chip, on one hand, level conversion is carried out, on the other hand, signals can be flexibly processed, the CPLD unit module has the characteristics of instant power-on, nonvolatile storage, I/O counting and the like, a User Flash Memory (UFM) block and an enhanced logic device of system internal programmability (ISP) are integrated inside the CPLD unit module, the cost and the power can be effectively reduced, and meanwhile, the CPLD unit module also provides a programmable solution for bus bridging, I/O expansion, sequencing control, equipment configuration control and other applications; the BMC management chip adopts AST2500A2 model, supports IPMI2.0 new characteristics and RGMII interface specification, and remotely updates BIOS on line by using simple terminal program input command; the RGMII PHY chip adopts an RTL8211E-VB-CG model, supports RGMII interface specification, has a working clock of 125MHz, adopts a 4-bit data interface, simultaneously transmits data at a rising edge and a falling edge, and realizes a network interface for outputting kilomega transmission rate; and arranging the mainboard circuit which is remotely updated on line by the constitution unit according to the BIOS chip based on the server in a printed circuit board for application.

Through adopting the utility model discloses an above-mentioned technical scheme has obtained following profitable effect:

the utility model discloses a mainboard circuit for remote online update of a BIOS chip based on a server, which expands the performance of a BMC management chip through a CPLD unit module, solves the problem that the BMC management chip can not debug the whole system in real time in the remote debugging of the existing domestic server, and meets the use requirements of users on storage products; the utility model relates to a simply, the cost is lower, the integrated level is high.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be viewed as the protection scope of the present invention.

Claims

1. A mainboard circuit for remotely updating a BIOS chip on line based on a server is characterized by comprising a processor, a CPLD unit module, the BIOS chip, a BMC management unit, an RGMII PHY chip and a kilomega management network port; the CPLD unit module is respectively connected with the processor and the BIOS chip through an SPI bus; the CPLD unit is connected with the BMC management unit through the SPI bus and a GPIO bus; the BMC management unit mounts the RGMII PHY chip, is connected with the gigabit management network port through the RGMII PHY chip and provides high-speed network transmission for remote online updating of the BIOS chip.

2. The motherboard circuit for remote online update of server-based BIOS chips of claim 1, wherein said CPLD unit module is connected with two said processors and two said BIOS chips; the processor includes a CPU1 and a CPU 2; the BIOS chip includes BIOS1 and BIOS 2.

3. The motherboard circuit for remote online update of server-based BIOS chips of claim 1, wherein said CPLD unit module is provided with 5 SPI interfaces and one GPIO interface; the processor and the BIOS chip are both provided with the SPI interface; the BMC management unit is provided with the SPI interface and the GPIO interface.

4. The motherboard line for remote online update of a server-based BIOS chip of claim 1, wherein the BMC management chip integrates an RGMII serial port, and mounts the RGMII PHY chip through an RGMII bus to provide high-speed network transmission for remote online update of the BIOS chip.

5. The motherboard circuit for remote online update of server-based BIOS chip of claim 1, wherein the CPLD unit module and the BMC management unit switch the connection mode of the SPI interface in the CPLD unit module through the operating state of the GPIO interface.