CN214041660U

CN214041660U - Signal acquisition circuit

Info

Publication number: CN214041660U
Application number: CN202023315461.8U
Authority: CN
Inventors: 刘翔宇
Original assignee: Raisecom Technology Co Ltd
Current assignee: Raisecom Technology Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-08-24
Anticipated expiration: 2030-12-31

Abstract

The embodiment of the application discloses signal acquisition circuit includes: an external terminal; a clamp circuit; the first end of the external power supply switch is connected with an external power supply, the second end of the external power supply switch is connected with the signal acquisition point and the output end of the clamping circuit, the control end of the external power supply switch is connected with the output end of the first photoelectric isolation circuit, and communication control between the first end and the second end is realized when a communication control signal is received; the judgment circuit outputs a first conduction signal to the second photoelectric isolation circuit when judging that the voltage value of the signal acquisition point is higher than a judgment set value; the first photoelectric isolation circuit is provided with an NPN type triode, and when a collector and an emitter of the NPN type triode are conducted, the first photoelectric isolation circuit triggers to send a communication control signal to a control end of the external power supply switch; and the input end of the second photoelectric isolation circuit is connected with the output end of the judgment circuit, the output end of the second photoelectric isolation circuit is used as the output end of the signal acquisition circuit, and when the first conduction signal is received, a high level signal is output, otherwise, a low level signal is output.

Description

Signal acquisition circuit

Technical Field

The embodiment of the application relates to the field of information acquisition, in particular to a signal acquisition circuit.

Background

In the field of industrial control, dry contacts (dry contacts) and wet contacts (wet contacts) are widely used. The dry contact is a passive switch, and has 2 states of closing and opening; the two contacts have no polarity and can be interchanged. Common dry contact signals are: limit switch, travel switch, foot switch, rotary switch, temperature switch, liquid level switch, water sensor, fire alarm sensor, glass breaking, vibration, smog and condensation sensor. When a dry contact output signal in an off state is collected, a digital signal "1" is usually collected; when the dry contact output signal in the closed state is collected, a digital signal "0" is usually collected. The wet contact is an active switch, has 2 states of power and no power, and has polarity between two contacts, which cannot be connected reversely. In industrial control, the output voltage range of a common wet joint is direct current DC 0-30V, and is typically DC 24V; common wet junction output signals are: the output signal of the collector of the NPN type triode, the output signal of the collector of the Darlington tube, the output signals of the infrared reflection sensor and the correlation sensor, and the like. When a wet contact output signal in a non-electricity state is collected, a digital signal '0' is usually collected; when a wet contact output signal is collected in a powered state, a digital signal "1" is typically collected. In the prior art, a signal acquisition circuit is generally used for acquiring an output signal representing the current working state of a dry contact or a wet contact, and performing logic conversion on the voltage value of the acquired output signal to determine a digital signal value. Wherein:

a typical manner for the signal acquisition circuit to acquire the current working state of the main contact is shown in fig. 1, the signal acquisition circuit outputs a predetermined voltage value (for example, 12V shown in fig. 1) to the main contact, detects the current working state of the main contact, and when the main contact is disconnected, a digital signal "1" can be acquired at the output end of the signal acquisition circuit; when the dry contact is closed, a digital signal '0' can be acquired at the output end of the signal acquisition circuit.

A typical manner for the signal acquisition circuit to acquire the current working state of the wet contact is shown in fig. 2, a preset power supply (for example, DC24V shown in fig. 2) is provided inside the wet contact, the signal acquisition circuit does not need to supply power to the wet contact, and when the wet contact is not powered, a digital signal "0" can be acquired at the output end of the signal acquisition circuit; when the wet contact is powered, there is a predetermined value (e.g., DC24V in fig. 2) output, and a digital signal "1" can be acquired at the signal acquisition circuit output.

In the prior art, the dry contact and the wet contact have different application occasions and coexist for a long time, so that the input end of the signal acquisition circuit (namely, the connecting end of the output signal of the contact) is generally required to be provided with input terminals with 3 pins, and the acquisition of the current working state of the signal acquisition circuit is realized by selecting different wiring modes to respectively correspond to the output signals of the dry contact and the wet contact. A typical signal acquisition circuit is shown in fig. 3. When the collected signal object is a dry contact, the signal collection object is passive, a switch K1 needs to be closed, power is supplied to the signal collection circuit, an input terminal pin II and a pin III are connected through a cable, when the dry contact is closed, the input terminal pin II and the pin III are in short circuit, and a digital signal 0 can be collected at the output end of the signal collection circuit; when the dry contact is disconnected, the pin II and the pin III of the input terminal are opened, and a digital signal 1 can be acquired at the output end of the signal acquisition circuit; when the collected signal object is a wet contact, the signal collection object is active and can output voltage, the cable is connected with the input terminal pin (i) and the pin (iii), and the switch K1 is disconnected, so that when the wet contact is not electrified, a digital signal '0' can be collected at the output end of the signal collection circuit, when the wet contact is electrified, and when a preset value voltage (for example, DC24V) is output, a digital signal '1' can be collected at the output end of the signal collection circuit. However, this approach clearly has the following disadvantages:

(1) for equipment to be subjected to contact output signal acquisition, the contact type of a signal acquisition object is acquired in advance, so that a connecting cable is connected to a pin corresponding to the input end of a signal acquisition circuit;

(2) in the practical application scene, no matter dry contact or wet contact, all only need 2 pins to carry out signal output usually, and signal acquisition circuit adopts the input terminal of 3 pins again for the compatibility of two kinds of contacts usually, and constructor need look up the data at both ends when the wiring, confirms the relation of connection, in case the cable connection is wrong, probably leads to signal acquisition object or signal acquisition circuit's damage even the burning of starting a fire.

SUMMERY OF THE UTILITY MODEL

In order to solve any one of the above technical problems, an embodiment of the present application provides a signal acquisition circuit.

In order to achieve the object of the embodiment of the present application, an embodiment of the present application provides a signal acquisition circuit, including: the external terminal is used for being connected with the signal to be collected, and the circuit further comprises: the circuit comprises a clamping circuit, an external power supply switch, a decision circuit, a first photoelectric isolation circuit and a second photoelectric isolation circuit, wherein:

the external terminal is provided with 2 pins, a first pin of the external terminal is connected with the input end of the clamping circuit, and a second pin of the external terminal is connected with a preset external power ground GND 1;

the output end of the clamping circuit is connected with a set signal acquisition point;

the first end of the external power supply switch is connected with a preset external power supply Vcc1, the second end of the external power supply switch is connected with a signal acquisition point and the output end of the clamping circuit, the control end of the external power supply switch is connected with the output end of the first photoelectric isolation circuit, and the communication control between the first end and the second end is realized when a communication control signal is received;

the judgment circuit outputs a first conduction signal to the second photoelectric isolation circuit when judging that the voltage value of the signal acquisition point is higher than a judgment set value;

the first photoelectric isolation circuit is provided with an NPN triode Q2, and when a collector and an emitter of the NPN triode are conducted, the connection control signal is triggered to be sent to a control end of the external power supply switch;

and the input end of the second photoelectric isolation circuit is connected with the output end of the judgment circuit, the output end of the second photoelectric isolation circuit is used as the output end of the signal acquisition circuit, and when the second photoelectric isolation circuit receives the first conduction signal, the second photoelectric isolation circuit outputs a high level signal, otherwise, the second photoelectric isolation circuit outputs a low level signal.

One of the above technical solutions has the following advantages or beneficial effects:

the contact output signal is led in through the external terminals of 2 pins, and the types of the contacts do not need to be distinguished; sampling is completely realized on the contact output signals through a hardware structure, and the type and the current state of the sampled contact can be determined; in each set signal period, the signal acquisition circuit is applied to control an external power supply switch to work in a primary pulse state, so that the judgment of the type and the working state of the contact can be realized, the acquisition of the output signal of the contact is completed, and the whole judgment process is stable and reliable.

Additional features and advantages of the embodiments of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the examples of the embodiments of the present application do not constitute a limitation of the embodiments of the present application.

FIG. 1 is a schematic diagram illustrating a prior art method for collecting a current working state of a dry contact;

FIG. 2 is a diagram illustrating a prior art method for collecting a current working state of a wet contact;

FIG. 3 is a schematic diagram of a prior art signal acquisition circuit that is compatible with acquiring current operating states of a dry contact and a wet contact;

fig. 4 is a schematic block diagram of a signal acquisition circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic block diagram of another signal acquisition circuit provided in an embodiment of the present application;

fig. 6 is a schematic diagram of a signal acquisition circuit according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments of the present application may be arbitrarily combined with each other without conflict.

To above-mentioned problem, this application embodiment provides a signal acquisition circuit, and it can utilize the input terminal access contact's of 2 pins output signal, and automatic compatible dry, wet contact type, no matter dry contact or wet contact, can both accurately gather the output signal of sign contact current operating condition, has solved the work progress and has wasted time and energy the mode of connection of distinguishing the problem, has avoided the safety problem that the misconnection leads to.

As shown in fig. 4, a signal acquisition circuit includes: external terminal, clamp circuit, external power supply switch, decision circuit, first photoelectric isolation circuit and second photoelectric isolation circuit, wherein:

the external terminal is provided with 2 pins, and a first pin of the external terminal is connected with the input end of the clamping circuit and used for transmitting an output signal of the contact to the clamping circuit; the second pin is connected with a preset external power ground GND 1; the output signal of the joint can be the output signal of a dry joint or the output signal of a wet joint; the type of the contact is not limited at all; typically, the external terminal can be a phoenix joint with 2 pins, preferably, the distance between two pins is 7.62 mm;

the output end of the clamping circuit is connected with a set signal acquisition point A;

the first end of the external power supply switch is connected with a preset external power supply Vcc1, the second end of the external power supply switch is connected with a signal acquisition point A and the output end of the clamping circuit, the control end of the external power supply switch is connected with the output end of the first photoelectric isolation circuit, and the communication control between the first end and the second end is realized when a communication control signal is received;

the judgment circuit outputs a first conduction signal to the second photoelectric isolation circuit when judging that the voltage value of the signal acquisition point A is higher than a judgment set value; the judgment set value is determined according to the output signal threshold value of the wet contact in the electrified state;

the first photoelectric isolation circuit is provided with an NPN triode Q2, and when a collector and an emitter of the NPN triode Q2 are conducted, the first photoelectric isolation circuit triggers to send a communication control signal to a control end of the external power supply switch; when the base of the NPN transistor Q2 receives an external signal (shown In fig. 4 as being input from an external signal input terminal In) as a high-level signal, the collector and the emitter are turned on;

and the input end of the second photoelectric isolation circuit is connected with the output end of the decision circuit, the output end of the second photoelectric isolation circuit is used as the output end Out of the signal acquisition circuit, and when the second photoelectric isolation circuit receives the first conduction signal, the second photoelectric isolation circuit outputs a high level signal, otherwise, the second photoelectric isolation circuit outputs a low level signal.

The following supplementary explanation is needed for the above embodiments:

(1) in the implementation scheme of the signal acquisition circuit, as known to those skilled in the art, for the first and second photoelectric isolation circuits, the input side and the output side thereof correspond to two power supplies (external power supply and internal power supply) isolated from each other, which are identified by Vcc1-GND1, Vcc2-GND2 and dotted lines as a separation schematic in fig. 4, and are not specifically described, and the implementation manner of the two power supplies may be implemented in any manner known to those skilled in the art, and will not be described herein again;

(2) in the implementation scheme of the signal acquisition circuit, the voltage value of the external power supply Vcc1 is not lower than the output signal threshold of the wet contact in the powered state, and since it may need to supply power to the dry contact in the closed state at the same time, therefore, it is also necessary to consider that the output value of the dry contact in the open state after voltage division of the internal resistor is higher than the decision setting value of the signal acquisition point a, and the actual value of the external power supply Vcc1 can be set by a person of ordinary skill in the art according to the actual circuit;

(3) in the implementation scheme of the signal acquisition circuit, the power ground at the contact side is also the external power ground GND 1;

(4) in the implementation of the signal acquisition circuit, the signal received by the base of the NPN transistor Q2 comes from the outside, for example, a special trigger circuit, or a signal generator, etc., typically, the base voltage is usually a low level signal, and when it is necessary to make the collector and emitter thereof conductive, the external signal input is a high level;

(5) in an implementation scheme of the signal acquisition circuit, the second photoelectric isolation circuit outputs a high-level signal and a low-level signal, which are acquired contact signals, and the signals can be used as input data for implementing operations of other circuits. Specifically, when the collector and the emitter of the NPN transistor Q2 are not triggered to turn on by an external signal, the second optoelectronic isolation circuit outputs a high level signal indicating that: the contact of current acquisition signal is wet contact and is in the electrified state: when the collector and the emitter of the NPN type triode Q2 are triggered to conduct by an external signal, the second optoelectronic isolation circuit outputs a high level signal indicating that: the contact of the current collected signal is a dry contact and is in an open state.

Further, as shown in fig. 5, an electrostatic protection circuit may be disposed between the external terminal and the clamping circuit for eliminating static electricity introduced through the external terminal.

The primary acquisition principle of the signal acquisition circuit is as follows:

firstly, when the base of the NPN type triode Q2 does not receive a high level signal, the collector and the emitter are not conducted, and the first terminal and the second terminal in the external power supply switch are disconnected, so that the external power supply switch operates in a disconnected state, if the signal collection object is a wet contact in an electrical state, the voltage value of the signal collection point a is higher than a decision set value, the decision circuit sends a first conduction signal to the second photoelectric isolation circuit, and the second photoelectric isolation circuit outputs a high level signal when receiving the first conduction signal, indicating that: the current signal acquisition contact is a wet contact and is in an electrified state, and one-time acquisition is completed;

if in the above process, the second optoelectronic isolation circuit outputs a low level signal, that is: the signal acquisition circuit outputs a low-level signal, a high-level signal is applied to a base electrode of an NPN triode Q2, so that a collector electrode and an emitter electrode of the NPN triode Q2 are conducted, a first photoelectric isolation circuit is triggered to send a connection control signal to a control end of the external power supply switch, a first end and a second end of the external power supply switch are communicated, at the moment, if a signal acquisition object is a dry contact point in a disconnected state, the voltage value of a signal acquisition point A is higher than a judgment set value, a judgment circuit sends a first connection signal to a second photoelectric isolation circuit, and the second photoelectric isolation circuit outputs a high-level signal when receiving the first connection signal; if the signal acquisition object is a dry contact in a closed state or a wet contact in a non-electric state, the second photoelectric isolation circuit outputs a low-level signal at the moment, and one-time acquisition is completed.

Therefore, the possible types of the contact points and the current state of the contact points can be well identified through the signal acquisition circuit. Specifically, when the signal acquisition circuit is used for acquiring a contact signal, in an acquisition period, the NPN transistor Q2 is first turned off, and at this time, if the signal acquisition circuit outputs a high level signal, it indicates that the object acquired at this time is: a wet contact in an electrically energized state. If the output of the signal acquisition circuit is a low level signal, the NPN type triode Q2 is turned on, typically, the turn-on time is 100 μ s, and the first end and the second end of the external power supply switch are controlled to be communicated, correspondingly, if the output of the signal acquisition circuit is a high level signal, it indicates that the object acquired at this time is: the dry contact in the disconnected state records the signal acquisition result at the moment; if the output of the signal acquisition circuit is still a low level signal, the types of the contacts do not need to be distinguished continuously at the moment, and the acquisition result is recorded.

The signal acquisition circuit can simply and effectively utilize the external terminals of 2 pins to realize the acquisition of the contact signals without distinguishing the types of the introduced contact signals in advance.

In the following, the signal acquisition circuit provided by the present invention is described in more detail with reference to more detailed embodiments, and as shown in fig. 6, the signal acquisition circuit includes:

an external connection terminal J1, which is a 2-pin terminal, the first pin of which is used for leading in the output signal of the joint; and a second pin connected to a predetermined external power ground GND 1; the output signal of the contact may be the output signal of the dry contact or the output signal of the wet contact, and the type of the contact is not limited;

an electrostatic protection circuit, comprising: one end of the magnetic bead LB1 is connected with a first pin of the external terminal J1, the other end of the magnetic bead LB1 is connected with a first end of a current-limiting resistor R0, and a TVS D2 is arranged between the magnetic bead LB1 and a TVS (Transient Voltage regulator) D2 and an external power ground GND 1;

a clamp circuit, comprising: a current limiting resistor R0, a third voltage regulator tube D3 and a fourth voltage regulator tube D4, wherein the second end of the current limiting resistor R0 is connected with the signal acquisition point A, and the third voltage regulator tube D3 and the fourth voltage regulator tube D4 are arranged between the signal acquisition point A and the external power ground GND 1; the signal acquisition point A is a preset contact signal acquisition position and is positioned on a transmission path of a signal introduced by a first pin of an external terminal;

a first opto-isolation circuit, comprising: the circuit comprises a first optocoupler U1, a first resistor R1, a second resistor R2, a third resistor R3 and an NPN type triode Q2, wherein a positive input end of the first optocoupler U1 is connected with an internal power supply Vcc2 through the first resistor R1, a negative input end is connected with a collector of the NPN type triode Q2, a positive output end is connected with the external power supply Vcc1 through the second resistor R2, a negative output end is connected with an external power supply ground GND1, an emitter of the NPN type triode Q2 is connected with the internal power supply ground GND2, and a base is connected with an external signal input end In through the third resistor R3;

a second optoelectronic isolation circuit, comprising: a second optocoupler U2, a fourth resistor R4 and a fifth resistor R5, wherein a positive input end of the second optocoupler U2 is connected with the external power supply Vcc1 through the fourth resistor R4, a negative input end is connected with a drain of an NMOS tube Q4, a positive output end is connected with an internal power supply Vcc2, and a negative output end is connected with an internal power supply ground GND2 through the fifth resistor R5 and serves as an output end Out of the signal acquisition circuit;

the external power supply switch comprises a first PMOS transistor Q1, wherein the source electrode of the first PMOS transistor Q1 is a first end connected with a preset external power supply Vcc1, and the drain electrode is a second end; the grid is used as a control end and is connected with the positive output end of the first optocoupler U1;

a decision circuit, comprising: a first voltage regulator tube D1, a second PMOS tube Q3, an NMOS tube Q4, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, wherein the source of the second PMOS tube Q3 is connected to the signal acquisition point a, the drain is connected to the gate of the NMOS tube Q4 and connected to an external power ground GND1 through the sixth resistor R6, the gate is connected to the external power Vcc1 through the seventh resistor R7 and connected to the cathode of the first voltage regulator tube D1, and the anode of the first voltage regulator tube D1 is connected to the external power ground GND 1; the source electrode of the NMOS tube Q4 is connected with an external power ground GND 1; one end of the eighth resistor R8 is connected with a signal acquisition point A, and the other end of the eighth resistor R8 is connected with the drain electrode of the first PMOS tube Q1.

Before the signal acquisition circuit shown in fig. 6 is used for acquiring the joint output signal, an external terminal J1 for receiving the joint output signal is connected with a port of the joint output signal, and an external electrical connection is formed through an external terminal J1; wherein, the joint may be a dry joint or a wet joint, which is not limited herein; however, it should be noted that: when implementing the technical solution of the present application, a person skilled in the art needs to connect the second pin of the external terminal with the power ground on the contact side;

further, in the electrostatic protection circuit, when the electrostatic voltage introduced through the external terminal J1 is high, the resistance of the magnetic bead LB1 increases sharply, the high-frequency energy of the electrostatic is dissipated in the form of heat, and the high voltage introduced at the same time can be discharged to the ground through the TVS D2, so that each element in a subsequent circuit is well protected; the clamping circuit is arranged in the signal acquisition circuit to further control the high voltage of the introduced signal, the current is limited through the current limiting resistor R0, and the residual high voltage is restrained to a preset value through the third voltage regulator tube D3 and the fourth voltage regulator tube D4.

The working principle of performing primary signal acquisition through the signal acquisition circuit is as follows:

when a low-level signal is input at the external signal input end, the NPN type triode Q2 is turned off, the first optocoupler U1 is not turned on, and thus, the first PMOS transistor Q1 serving as an external power supply switch is turned off, and the preset external power supply Vcc1 cannot supply power to the outside through the first PMOS transistor Q2.

At this time: (1) when the external terminal introduces an output signal of a wet joint in an electric state, the voltage of the signal acquisition point A completely comes from a preset power supply in the wet joint, and at the moment, the voltage of the source electrode (S) of the second PMOS tube Q3 is equal to the voltage of the signal acquisition point A and is the external power supply voltage value, | V_GS|>|V_GSthIf the second PMOS transistor Q3 is turned on, the sixth resistor R6 is connected to the loop, so as to trigger the NMOS transistor Q4 to be turned on, and further the second optocoupler U2 is turned on, and the negative output end of the second optocoupler outputs a high level signal as an output signal of the signal acquisition circuit;

(2) when the external terminal introduces an output signal of a wet joint in an electroless state or a dry joint in a closed state, due to the fact that no external power supply is input, the voltage of a source electrode (S) of the second PMOS tube Q3 is equal to the voltage of the signal acquisition point A, at the moment, the voltage is 0, the second PMOS tube Q3 and the NMOS tube Q4 cannot be conducted, the second optocoupler U2 is not conducted, and a negative output end of the second PMOS tube outputs a low-level signal which serves as an output signal of the signal acquisition circuit.

In summary, if the external power supply switch is turned off, a high level signal can be outputted only when the wet contact in the powered state is outputted.

Next, when a high level signal is input to the external signal input terminal, the NPN transistor Q2 is turned on, and the first optocoupler U1 is turned on, so that the gate (G) of the first PMOS transistor Q1 serving as an external power supply switch is grounded, | V_GS|>|V_GSthThe first PMOS transistor Q1 is turned on, and an external power supply Vcc1 (which may be 12V typically) supplies power to the external power supply through the first PMOS transistor Q1 and the eighth resistor R8;

at this time: (1) when the output signal of the dry contact in the off state is introduced by the external terminal, the source (S) voltage of the second PMOS transistor Q3 is equal to the voltage of the signal acquisition point A, and is the external power supply voltage value Vcc1, and for the second PMOS transistor Q3, the voltage of | V is_GS|>|V_GSthIf the second PMOS transistor Q3 is turned on, the sixth resistor R6 is connected to the loop, and the source (S) voltage V of the second PMOS transistor Q3 is_S＝[R6/(R6+R8)]X Vcc1, which is approximately the gate voltage of NMOS transistor Q4, provided that the resistance values of the respective resistors and the external power supply voltage are arranged such that: for the second PMOS transistor Q3, | V_GS|>|V_GSthThe second PMOS transistor Q3 is still turned on; for NMOS transistor Q4, | V_GS|>|V_GSthThe NMOS tube Q4 is conducted, the second optocoupler U2 is conducted, and the negative output end of the second optocoupler outputs a high-level signal as an output signal of the signal acquisition circuit;

(2) when an output signal of a dry contact in a closed state is introduced by the external terminal, the magnetic bead LB1 is grounded, the voltage of the source electrode (S) of the second PMOS tube Q3 is equal to the voltage of the signal acquisition point A, and V is_S＝[R0/(R0+R8)]× Vcc1, as long as the respective resistance values and the external power supply voltage value are arranged such that: for the second PMOS transistor Q3, | V_GS|＜|V_GSthThe second PMOS transistor Q3 is turned off, so that the NMOS transistor Q4 is turned off, the second optocoupler U2 is turned off, and the negative output end of the second optocoupler outputs a low level signal as an output signal of the signal acquisition circuit;

(3) when an output signal of a wet joint in an electroless state is introduced by the external terminal, the voltage on the external pin J1 is 0V, the magnetic bead LB1 is equivalently grounded, the source (S) voltage of the second PMOS tube Q3 is equal to the voltage of the signal acquisition point A, and V is equal to the voltage of the signal acquisition point A_S＝[R0/(R0+R8)]× Vcc1, as long as the resistance values of the respective resistors and the external power supply voltage value are arranged such that: for the second PMOS transistor Q3, | V_GS|＜|V_GSthThe second PMOS transistor Q3 is turned off, so that the NMOS transistor Q4 is turned off, the second optocoupler U2 is turned off, and the negative output end of the second optocoupler outputs a low level as an output signal of the signal acquisition circuit;

in the above specific circuit implementation process, the decision setting value of the signal acquisition point a is determined according to the voltage value of the output signal of the wet contact in the closed state, specifically: under the condition that the wet joint has an electric output, the second PMOS tube Q3 in the judgment circuit can be triggered to be conducted, namely, for the second PMOS tube Q3, under the condition that the wet joint has an electric output, | V_GS|>|V_GSthL: considering the resistance of the signal transmission line, the decision setting value should be slightly smaller than the built-in voltage value of the wet contact, and typically, when the output signal is 5V in the powered state of the wet contact, the decision setting value of the signal acquisition point a can be set to be 4.15V. To satisfy the V of the second PMOS transistor Q3 and the NMOS transistor Q4_GSAnd V_GSthThe set resistance values of the resistors can be determined by those skilled in the art according to actual conditions. For example: vcc 1-12V, R8-20K, R0-1.8K, R6-62K, and threshold V for the turn-on voltage of each of PMOS and NMOS transistors_GSthAre known parameters according to the device model selection respectively.

In summary, if the first end and the second end of the first PMOS transistor Q1 as the external power supply switch are turned on, that is, the first PMOS transistor Q1 is turned on, the high level signal can be output only when the output signal of the dry contact in the off state is collected; and the output signals of the dry contact in the dry closed state and the wet contact in the non-electricity state are collected to output low level signals. Here, one point is specifically explained: when external power supply switch switches on and makes preset external power supply Vcc1 have an output, it is not permissible to gather the output signal of the wet contact that is in the electrified state, therefore, the technical scheme of this application makes judgement and gets rid of to this kind of condition at first, confirms that outside no voltage input is external to supply power again and detect, whole process is pulsed, safe intelligence, and external power supply switch adopts pulsed operating condition according to input signal, it is fast and more reliable to switch response speed by the hardware device.

Therefore, when the contact output signal is collected based on the signal collecting circuit, in a collecting period, the NPN type triode Q2 is firstly turned off, and at this time, if the signal collecting circuit outputs a high level signal, it indicates that the collection at this time is: and (4) recording the signal acquisition result of the output signal of the wet contact in the electrified state, and finishing one acquisition process. If the signal acquisition circuit outputs a low level signal, the collector and the emitter of the NPN type triode Q2 are controlled to be turned on by an external signal (typically, the pulse width is 100 μ s), so as to control the first end and the second end of the first PMOS transistor Q1 to be communicated, and correspondingly, the signal acquisition circuit outputs a high level signal, which indicates that the signal acquired at this time is: the dry contact is in an open circuit state, and the signal acquisition result at the moment is recorded; at this moment, if the signal acquisition circuit still outputs a low level signal, the contact type does not need to be continuously distinguished, and only the acquisition result is recorded.

The technical proposal of the utility model introduces the contact output signal through the external terminals of 2 pins, and does not need to distinguish the contact types; sampling is completely realized on the contact output signals through a hardware structure, and the type and the current state of the sampled contact can be determined; in each set signal period, the signal acquisition circuit is applied to control an external power supply switch to work in a primary pulse state, so that the judgment of the type and the working state of the contact can be realized, the acquisition of the output signal of the contact is completed, and the whole judgment process is stable and reliable.

It will be appreciated by one of ordinary skill in the art that the functional modules/units in the systems, apparatuses disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

Claims

1. A signal acquisition circuit, comprising: the external terminal is used for being connected with the signal to be collected, and is characterized in that the circuit further comprises: the circuit comprises a clamping circuit, an external power supply switch, a decision circuit, a first photoelectric isolation circuit and a second photoelectric isolation circuit, wherein:

the external terminal is provided with 2 pins, a first pin of the external terminal is connected with the input end of the clamping circuit, and a second pin of the external terminal is connected with a preset external power ground (GND 1);

the first end of the external power supply switch is connected with a preset external power supply (Vcc1), the second end of the external power supply switch is connected with a signal acquisition point and the output end of the clamping circuit, the control end of the external power supply switch is connected with the output end of the first photoelectric isolation circuit, and communication control between the first end and the second end is realized when a communication control signal is received;

the first photoelectric isolation circuit is provided with an NPN type triode (Q2), and when a collector and an emitter of the NPN type triode are conducted, the connection control signal is triggered to be sent to the control end of the external power supply switch;

2. The signal acquisition circuit of claim 1 wherein the decision set point is determined based on an output signal threshold of the wet contact in a powered state.

3. The signal acquisition circuit of claim 1, wherein the signal acquisition circuit further comprises: and the electrostatic protection circuit is arranged between the external terminal and the clamping circuit.

4. The signal acquisition circuit of claim 3 wherein the electrostatic protection circuit comprises: the circuit comprises a magnetic bead (LB1) and a transient diode TVS (D2), wherein one end of the magnetic bead (LB1) is connected with a first pin of the external terminal, the other end of the magnetic bead is connected with the input end of the clamping circuit, and the transient diode TVS (D2) is arranged between the magnetic bead and the external power ground (GND 1).

5. The signal acquisition circuit of claim 1 wherein the clamp circuit comprises: the current limiting circuit comprises a current limiting resistor (R0), a third voltage regulator tube (D3) and a fourth voltage regulator tube (D4), wherein the current limiting resistor (R0) is arranged between the input end of the clamping circuit and the signal acquisition point, and the third voltage regulator tube (D3) and the fourth voltage regulator tube (D4) are arranged between the signal acquisition point and the power ground (GND 1).

6. The signal acquisition circuit of claim 5 wherein the external power switch comprises: the source electrode of the first PMOS tube (Q1) is a first end connected with the external power supply (Vcc1), the drain electrode is a second end, and the grid electrode is a control end.

7. The signal acquisition circuit of claim 6,

the first opto-electronic isolation circuit further comprises: the high-voltage circuit comprises a first optical coupler (U1), a first resistor (R1), a second resistor (R2) and a third resistor (R3), wherein a positive input end of the first optical coupler (U1) is connected with an internal power supply (Vcc2) through the first resistor (R1), a negative input end of the first optical coupler is connected with a collector of the NPN type triode (Q2), a positive output end of the first optical coupler is connected with the external power supply (Vcc1) through the second resistor (R2) and is connected with a grid of the first PMOS tube (Q1), a negative output end of the first optical coupler is connected with an external power ground (GND1), a base of the NPN type triode (Q2) is connected with an external signal input end (In) through the third resistor (R3), and an emitter of the first optical coupler is connected with an internal power ground (GND 2).

8. The signal acquisition circuit of claim 6 wherein the decision circuit comprises: a first voltage regulator tube (D1), a second PMOS tube (Q3), an NMOS tube (Q4), a sixth resistor (R6), a seventh resistor (R7) and an eighth resistor (R8), wherein the source electrode of the second PMOS tube (Q3) is connected with the signal acquisition point, the drain electrode of the second PMOS tube is connected with the grid electrode of the NMOS tube (Q4), the grid electrode of the second PMOS tube is connected with an external power ground (GND1) through the sixth resistor (R6), the grid electrode of the second PMOS tube is connected with the external power supply (Vcc1) through the seventh resistor (R7) and is connected with the cathode electrode of the first voltage regulator tube (D1), and the anode electrode of the first voltage regulator tube (D1) is connected with the external power ground (GND 1); the source electrode of the NMOS tube (Q4) is connected with an external power ground (GND 1); one end of the eighth resistor (R8) is connected with a signal acquisition point, and the other end of the eighth resistor (R8) is connected with the drain electrode of the first PMOS tube (Q1).

9. The signal acquisition circuit of claim 8 wherein:

the sizes of the sixth resistor (R6), the eighth resistor (R8) and the external power supply (Vcc1) satisfy the following conditions:

using the following calculation expression

[R6/(R6+R8)]×Vcc1

The calculated voltage is simultaneously larger than the threshold value | V of the starting voltage of the second PMOS tube (Q3)_GSthL and the threshold voltage | V of the NMOS transistor (Q4)_GSth|；

Wherein R6 and R8 respectively represent resistance values of the sixth resistor (R6) and the eighth resistor (R8), Vcc1 represents a voltage value of the external power supply (Vcc 1);

the current limiting resistor (R0), the eighth resistor (R8) and the external power supply (Vcc1) satisfy the following conditions:

using the following calculation expression

[R0/(R0+R8)]×Vcc1

The calculated voltage is less than the threshold value | V of the starting voltage of the second PMOS tube (Q3)_GSth|；

R0 represents the resistance value of the current limiting resistor (R0).

10. The signal acquisition circuit of claim 8 wherein the second opto-electronic isolation circuit comprises: second opto-coupler (U2), fourth resistance (R4) and fifth resistance (R5), the positive input end of second opto-coupler (U2) passes through fourth resistance (R4) with external power source (Vcc1) are connected, the negative input end with the drain electrode of NMOS pipe (Q4) is connected, and the positive output end is connected with internal power source (Vcc2), and the negative output end passes through fifth resistance (R5) is connected with internal power source ground (GND2), and is regarded as the output of signal acquisition circuit.