CN214041636U - Withstand voltage test leakage current acquisition circuit - Google Patents
Withstand voltage test leakage current acquisition circuit Download PDFInfo
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- CN214041636U CN214041636U CN202023065540.8U CN202023065540U CN214041636U CN 214041636 U CN214041636 U CN 214041636U CN 202023065540 U CN202023065540 U CN 202023065540U CN 214041636 U CN214041636 U CN 214041636U
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Abstract
The utility model relates to a withstand voltage test technical field, concretely relates to withstand voltage test leakage current acquisition circuit, it includes main control circuit, divides control circuit one, divides control circuit two, divides control circuit three, divides control circuit four, divides control circuit five, divides control circuit six, divides control circuit seven; the main control circuit is respectively connected with a branch control circuit I, a branch control circuit II, a branch control circuit III, a branch control circuit IV, a branch control circuit V, a branch control circuit VI and a branch control circuit VII through leads; the current and leakage current of 500-5000V sinusoidal alternating voltage can be detected, and the method can be applied to products and equipment needing voltage withstanding detection; the method has the characteristics of good stability, high response speed and the like.
Description
Technical Field
The utility model relates to a withstand voltage test technical field, concretely relates to withstand voltage test leakage current acquisition circuit.
Background
And products and equipment for voltage resistance detection need to collect leakage current of the products and the equipment. For the leakage current of 500-plus 5000V sinusoidal alternating current voltage, the existing leakage current acquisition circuit has the problems of low response speed, poor stability and the like.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to prior art's defect and not enough, provide a withstand voltage test leakage current acquisition circuit.
The utility model discloses a withstand voltage test leakage current acquisition circuit, it includes main control circuit, branch control circuit one, divides control circuit two, divides control circuit three, divides control circuit four, divides control circuit five, divides control circuit six, divides control circuit seven; the main control circuit is respectively connected with a branch control circuit I, a branch control circuit II, a branch control circuit III, a branch control circuit IV, a branch control circuit V, a branch control circuit VI and a branch control circuit VII through leads;
the main control circuit comprises a U1 unit, wherein the 1 st pin and the 2 nd pin of the U1 unit are connected in parallel at two ends of a capacitor C3, the capacitor C3 is connected in parallel with a capacitor CE5, one end of the capacitor CE5 is connected with a +5V end, and the other end of the capacitor CE5 is grounded; the 5 th to 8 th pins of the U1 unit are respectively connected with a TCK terminal, a TDIO terminal, an OUT terminal and a WINOUOT terminal; the 9 th pin of the U1 unit is connected in series with a resistor R6, and the other end of the resistor R6 is connected with the SRT end; one end of the resistor R15 is connected in parallel with one end of the resistor R16, and the other end of the resistor R15 is connected with the +5V end; one end of a capacitor C8 is connected in parallel with one end of the resistor R16, and the other end of the capacitor C8 is grounded; the 15 th to 20 th pins of the U1 unit are respectively connected with the 10mA, 5mA, 3mA, 2mA, 1mA and 0.5mA ends; the 10 th pin of the U1 unit is connected with the ADIN end, one end of a capacitor C7 is connected with the 10 th pin of the U1 unit in parallel, and the other end of the capacitor C7 is grounded;
the first sub-control circuit comprises a serial port J1, and the 3 rd end to the 8 th end of the serial port J1 are respectively connected with the 10mA end, the 5mA end, the 3mA end, the 2mA end, the 1mA end and the 0.5mA end;
the second branch control circuit comprises a connector P3, and the 1 st pin of the connector P3 is connected with the +5V end; pins 2 and 4 of the connector P3 are respectively connected with a TDIO end and a TCK end; the 2 nd pin of the connector P3 is grounded;
the third sub-control circuit comprises a boosting transformer, an HV1_ L end of the boosting transformer is connected with a high-voltage rod, and an HV1_ N end of the boosting transformer is connected with a resistor RX in series and then connected with a 3 rd pin of a serial port J2; the diode D1 is connected in parallel between the 3 rd pin and the 1 st pin of the serial port J2; the resistor R13 and the diode D2 are connected in series and then connected in parallel between the No. 3 pin and the No. 1 pin of the serial port J2; the capacitor C6 is connected in parallel across the resistor R13; the resistor R14 is connected in parallel between the resistor R13 and the capacitor CE 3; after the capacitor CE3 is connected with the resistor RW1 in series, one end of the capacitor CE3 is connected with the 1 st pin of the serial port J2 in parallel, and the other end of the resistor RW1 is grounded;
the sub-control circuit IV comprises a bidirectional diode DB1, the 1 st pin of the bidirectional diode DB1 is connected with the AC15VL terminal, and the AC15VL terminal is connected with the 3 rd pin of the serial port J3; pin 4 of the bidirectional diode DB1 is grounded; pin 3 of the bidirectional diode DB1 is connected with pin 1 of the serial port J3; a2 nd pin of the bidirectional diode DB1 is connected with a resistor R2 and an adjustable resistor VR1 in series and then is connected with a +5V end; the capacitor CE1 and the capacitor C1 are connected in parallel to the No. 2 pin of the bidirectional diode DB1 and the second lead; the resistor R1 and the light emitting diode LED1 are connected in series and then connected in parallel to the No. 2 pin and the second lead of the bidirectional diode DB 1; the GND end of the adjustable resistor VR1 is connected in parallel with the second lead; the capacitors CE2 and C2 are connected in parallel to the adjustable resistor VR1 and the second lead;
the sub-control circuit five comprises a negative electrode of an optical coupler OC2 and a resistor R7 which are connected in series, and the other end of the resistor R7 is connected with a +20V end; the anode of the optical coupler OC2 is connected in series with the light emitting diode LED2 and the resistor R6, and the light emitting diode LED2 and the resistor R6 are connected in series and then connected in parallel with the resistor R7; the base electrode of the triode Q2 is connected with the resistor R8 in series and then connected with the OUT end; the emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected in parallel with the anode of the optocoupler OC 2; an emitter of the optical coupler OC2 is connected with resistors R10 and R9 in series, and the other end of the resistor R9 is connected with the end of TRA 1; a collector of the optocoupler OC2 is connected with a control electrode of a bidirectional thyristor Q1, a first anode of the bidirectional thyristor Q1 is connected with the end of TRA2, and a second anode of the bidirectional thyristor Q1 is connected with a resistor R9 in parallel;
the sub-control circuit VI comprises an optical coupler OC1, and a collector and an emitter of the optical coupler OC1 are respectively connected with a WIN _ B end and a WIN _ A end; the positive electrode of the optocoupler OC1 is connected with the collector of the triode Q3, the remote emitter of the triode Q3 is grounded, and the base electrode of the triode Q3 is connected with the WINOUT end after being connected with the resistor R5 in series; the negative electrode of the optical coupler OC1 is connected with the +20V end after being connected with the resistor R4 in series; the resistor R3 and the light emitting diode LED3 are connected in series and then connected in parallel between the resistor R4 and the collector of the triode Q3;
the seventh sub-control circuit comprises a serial port J4, and pins 1, 3, 6, 8 and 10 of the serial port J4 are respectively connected with a TRA2 terminal, a TRA1 terminal, a WIN _ B terminal, a WIN _ A terminal and an SRT terminal; pin 12 of serial port J4 is connected to ground.
Further, the U1 unit is a single chip microcomputer with the model number SC92F7252M 20.
Further, the optical coupler OC2 is a photoelectric coupler with model number MOC 3063.
Further, the optical coupler OC1 is an optical coupler of type EL 817.
After the structure is adopted, the utility model discloses beneficial effect does: the utility model discloses a withstand voltage test leakage current acquisition circuit, it can detect 500 + 5000V sinusoidal alternating voltage's electric current and leakage current, can apply to the product and the equipment that need withstand voltage to detect; the method has the characteristics of good stability, high response speed and the like.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, do not constitute a limitation of the invention, and in which:
FIG. 1 is a topological schematic of the present invention;
FIG. 2 is a schematic diagram of the main control circuit of the present invention;
fig. 3 is a schematic diagram of a first sub-control circuit of the present invention;
FIG. 4 is a schematic diagram of a secondary control circuit II of the present invention;
FIG. 5 is a schematic diagram of a third sub-control circuit of the present invention;
fig. 6 is a schematic diagram of a sub-control circuit four of the present invention;
fig. 7 is a schematic diagram of a sub-control circuit five of the present invention;
fig. 8 is a schematic diagram of a sub-control circuit six of the present invention;
fig. 9 is a schematic diagram of a sub-control circuit seven of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1, the leakage current collecting circuit for voltage withstanding test according to this embodiment includes a main control circuit, a first sub control circuit, a second sub control circuit, a third sub control circuit, a fourth sub control circuit, a fifth sub control circuit, a sixth sub control circuit, and a seventh sub control circuit; the main control circuit is respectively connected with a branch control circuit I, a branch control circuit II, a branch control circuit III, a branch control circuit IV, a branch control circuit V, a branch control circuit VI and a branch control circuit VII through leads;
as shown in fig. 2, the main control circuit includes a U1 unit, pins 1 and 2 of the U1 unit are connected in parallel across a capacitor C3, the capacitor C3 is connected in parallel across a capacitor CE5, one end of the capacitor CE5 is connected to the +5V terminal, and the other end of the capacitor CE5 is grounded; the 5 th to 8 th pins of the U1 unit are respectively connected with a TCK terminal, a TDIO terminal, an OUT terminal and a WINOUOT terminal; the 9 th pin of the U1 unit is connected in series with a resistor R6, and the other end of the resistor R6 is connected with the SRT end; one end of the resistor R15 is connected in parallel with one end of the resistor R16, and the other end of the resistor R15 is connected with the +5V end; one end of a capacitor C8 is connected in parallel with one end of the resistor R16, and the other end of the capacitor C8 is grounded; the 15 th to 20 th pins of the U1 unit are respectively connected with the 10mA, 5mA, 3mA, 2mA, 1mA and 0.5mA ends; the 10 th pin of the U1 unit is connected with the ADIN end, one end of a capacitor C7 is connected with the 10 th pin of the U1 unit in parallel, and the other end of the capacitor C7 is grounded;
as shown in fig. 3, the first sub-control circuit includes a serial port J1, and the 3 rd to 8 th terminals of the serial port J1 are respectively connected to 10mA, 5mA, 3mA, 2mA, 1mA, and 0.5mA terminals;
as shown in fig. 4, the second sub-control circuit includes a connector P3, the 1 st pin of the connector P3 is connected to the +5V terminal; pins 2 and 4 of the connector P3 are respectively connected with a TDIO end and a TCK end; the 2 nd pin of the connector P3 is grounded;
as shown in fig. 5, the third sub-control circuit includes a step-up transformer, an HV1_ L terminal of the step-up transformer is connected to the high-voltage rod, and an HV1_ N terminal of the step-up transformer is connected in series with the resistor RX and then connected to the 3 rd pin of the serial port J2; the diode D1 is connected in parallel between the 3 rd pin and the 1 st pin of the serial port J2; the resistor R13 and the diode D2 are connected in series and then connected in parallel between the No. 3 pin and the No. 1 pin of the serial port J2; the capacitor C6 is connected in parallel across the resistor R13; the resistor R14 is connected in parallel between the resistor R13 and the capacitor CE 3; after the capacitor CE3 is connected with the resistor RW1 in series, one end of the capacitor CE3 is connected with the 1 st pin of the serial port J2 in parallel, and the other end of the resistor RW1 is grounded;
as shown in fig. 6, the sub-control circuit four includes a bidirectional diode DB1, the 1 st pin of the bidirectional diode DB1 is connected to the AC15VL terminal, and the AC15VL terminal is connected to the 3 rd pin of the serial port J3; pin 4 of the bidirectional diode DB1 is grounded; pin 3 of the bidirectional diode DB1 is connected with pin 1 of the serial port J3; a2 nd pin of the bidirectional diode DB1 is connected with a resistor R2 and an adjustable resistor VR1 in series and then is connected with a +5V end; the capacitor CE1 and the capacitor C1 are connected in parallel to the No. 2 pin of the bidirectional diode DB1 and the second lead; the resistor R1 and the light emitting diode LED1 are connected in series and then connected in parallel to the No. 2 pin and the second lead of the bidirectional diode DB 1; the GND end of the adjustable resistor VR1 is connected in parallel with the second lead; the capacitors CE2 and C2 are connected in parallel to the adjustable resistor VR1 and the second lead;
as shown in fig. 7, the sub-control circuit five includes a negative electrode of the optocoupler OC2 connected in series with the resistor R7, and the other end of the resistor R7 is connected to the +20V end; the anode of the optical coupler OC2 is connected in series with the light emitting diode LED2 and the resistor R6, and the light emitting diode LED2 and the resistor R6 are connected in series and then connected in parallel with the resistor R7; the base electrode of the triode Q2 is connected with the resistor R8 in series and then connected with the OUT end; the emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected in parallel with the anode of the optocoupler OC 2; an emitter of the optical coupler OC2 is connected with resistors R10 and R9 in series, and the other end of the resistor R9 is connected with the end of TRA 1; a collector of the optocoupler OC2 is connected with a control electrode of a bidirectional thyristor Q1, a first anode of the bidirectional thyristor Q1 is connected with the end of TRA2, and a second anode of the bidirectional thyristor Q1 is connected with a resistor R9 in parallel;
as shown in fig. 8, the sub-control circuit six includes an optical coupler OC1, and a collector and an emitter of the optical coupler OC1 are respectively connected to WIN _ B and WIN _ a ends; the positive electrode of the optocoupler OC1 is connected with the collector of the triode Q3, the remote emitter of the triode Q3 is grounded, and the base electrode of the triode Q3 is connected with the WINOUT end after being connected with the resistor R5 in series; the negative electrode of the optical coupler OC1 is connected with the +20V end after being connected with the resistor R4 in series; the resistor R3 and the light emitting diode LED3 are connected in series and then connected in parallel between the resistor R4 and the collector of the triode Q3;
as shown in fig. 9, the sub-control circuit seventh includes a serial port J4, and pins 1, 3, 6, 8, and 10 of the serial port J4 are respectively connected to a TRA2 terminal, a TRA1 terminal, a WIN _ B terminal, a WIN _ a terminal, and a SRT terminal; pin 12 of serial port J4 is connected to ground.
Further, the U1 unit is a single chip microcomputer with the model number SC92F7252M 20.
Further, the optical coupler OC2 is a photoelectric coupler with model number MOC 3063.
Further, the optical coupler OC1 is an optical coupler of type EL 817.
The utility model discloses a theory of operation:
in the design, a boosting transformer provides 0-5000V alternating-current voltage VH1_ L, a dual high-voltage wire is used for leading to a tested product or connecting a high-voltage testing rod, and VH1_ N is connected in series with a winding glazed ceramic resistor to play a role in buffering and protecting the whole high-voltage network.
In the design, D1, D2, R13 and C6 are current collecting and sampling devices, voltage division and filtering are carried out on the current through R14, CE3, CE4 and RW1, and then the current is transmitted to an acquisition port of the singlechip ADIN to monitor leakage current of a high-voltage part in real time. The J1 terminal is an external band switch and sets an alarm value for the leakage current value. U1 is an enhanced high-speed 8051 singlechip and is responsible for collecting, controlling and operating current.
In the design, DB1, CE1, C1, VR1, CE2 and C2 form 5V regulated voltage to supply power to the single chip microcomputer system. Q2, MOC3063 and Q1 form external alternating current control, and if the leakage current reaches a set value, the external power supply is immediately cut off, so that the safety of a power utilization system is protected. R15, R16 and C8 form a low-level active alarm reset circuit.
In the design, Q3 and OC1 provide an alarm signal for the next-stage equipment, and the stability and reliability of the whole system are guaranteed through electro-optical isolation.
The function of this design: the circuit can be applied to products and equipment which need withstand voltage detection, and has the characteristics of good stability, high response speed and the like. The current (leakage current) of 500-plus-5000V sinusoidal alternating current voltage can be detected, the current can be set to be 0.5-20mA, a leakage current alarm signal is transmitted to other industrial control equipment such as PLC (programmable logic controller) through a photoelectric device, and a main power supply is automatically turned off when the alarm is given.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (4)
1. The utility model provides a withstand voltage test leaks current acquisition circuit which characterized in that: the control circuit comprises a main control circuit, a branch control circuit I, a branch control circuit II, a branch control circuit III, a branch control circuit IV, a branch control circuit V, a branch control circuit VI and a branch control circuit VII; the main control circuit is respectively connected with a branch control circuit I, a branch control circuit II, a branch control circuit III, a branch control circuit IV, a branch control circuit V, a branch control circuit VI and a branch control circuit VII through leads;
the main control circuit comprises a U1 unit, wherein the 1 st pin and the 2 nd pin of the U1 unit are connected in parallel at two ends of a capacitor C3, the capacitor C3 is connected in parallel with a capacitor CE5, one end of the capacitor CE5 is connected with a +5V end, and the other end of the capacitor CE5 is grounded; the 5 th to 8 th pins of the U1 unit are respectively connected with a TCK terminal, a TDIO terminal, an OUT terminal and a WINOUOT terminal; the 9 th pin of the U1 unit is connected in series with a resistor R6, and the other end of the resistor R6 is connected with the SRT end; one end of the resistor R15 is connected in parallel with one end of the resistor R16, and the other end of the resistor R15 is connected with the +5V end; one end of a capacitor C8 is connected in parallel with one end of the resistor R16, and the other end of the capacitor C8 is grounded; the 15 th to 20 th pins of the U1 unit are respectively connected with the 10mA, 5mA, 3mA, 2mA, 1mA and 0.5mA ends; the 10 th pin of the U1 unit is connected with the ADIN end, one end of a capacitor C7 is connected with the 10 th pin of the U1 unit in parallel, and the other end of the capacitor C7 is grounded;
the first sub-control circuit comprises a serial port J1, and the 3 rd end to the 8 th end of the serial port J1 are respectively connected with the 10mA end, the 5mA end, the 3mA end, the 2mA end, the 1mA end and the 0.5mA end;
the second branch control circuit comprises a connector P3, and the 1 st pin of the connector P3 is connected with the +5V end; pins 2 and 4 of the connector P3 are respectively connected with a TDIO end and a TCK end; the 2 nd pin of the connector P3 is grounded;
the third sub-control circuit comprises a boosting transformer, an HV1_ L end of the boosting transformer is connected with a high-voltage rod, and an HV1_ N end of the boosting transformer is connected with a resistor RX in series and then connected with a 3 rd pin of a serial port J2; the diode D1 is connected in parallel between the 3 rd pin and the 1 st pin of the serial port J2; the resistor R13 and the diode D2 are connected in series and then connected in parallel between the No. 3 pin and the No. 1 pin of the serial port J2; the capacitor C6 is connected in parallel across the resistor R13; the resistor R14 is connected in parallel between the resistor R13 and the capacitor CE 3; after the capacitor CE3 is connected with the resistor RW1 in series, one end of the capacitor CE3 is connected with the 1 st pin of the serial port J2 in parallel, and the other end of the resistor RW1 is grounded;
the sub-control circuit IV comprises a bidirectional diode DB1, the 1 st pin of the bidirectional diode DB1 is connected with the AC15VL terminal, and the AC15VL terminal is connected with the 3 rd pin of the serial port J3; pin 4 of the bidirectional diode DB1 is grounded; pin 3 of the bidirectional diode DB1 is connected with pin 1 of the serial port J3; a2 nd pin of the bidirectional diode DB1 is connected with a resistor R2 and an adjustable resistor VR1 in series and then is connected with a +5V end; the capacitor CE1 and the capacitor C1 are connected in parallel to the No. 2 pin of the bidirectional diode DB1 and the second lead; the resistor R1 and the light emitting diode LED1 are connected in series and then connected in parallel to the No. 2 pin and the second lead of the bidirectional diode DB 1; the GND end of the adjustable resistor VR1 is connected in parallel with the second lead; the capacitors CE2 and C2 are connected in parallel to the adjustable resistor VR1 and the second lead;
the sub-control circuit five comprises a negative electrode of an optical coupler OC2 and a resistor R7 which are connected in series, and the other end of the resistor R7 is connected with a +20V end; the anode of the optical coupler OC2 is connected in series with the light emitting diode LED2 and the resistor R6, and the light emitting diode LED2 and the resistor R6 are connected in series and then connected in parallel with the resistor R7; the base electrode of the triode Q2 is connected with the resistor R8 in series and then connected with the OUT end; the emitter of the triode Q2 is grounded, and the collector of the triode Q2 is connected in parallel with the anode of the optocoupler OC 2; an emitter of the optical coupler OC2 is connected with resistors R10 and R9 in series, and the other end of the resistor R9 is connected with the end of TRA 1; a collector of the optocoupler OC2 is connected with a control electrode of a bidirectional thyristor Q1, a first anode of the bidirectional thyristor Q1 is connected with the end of TRA2, and a second anode of the bidirectional thyristor Q1 is connected with a resistor R9 in parallel;
the sub-control circuit VI comprises an optical coupler OC1, and a collector and an emitter of the optical coupler OC1 are respectively connected with a WIN _ B end and a WIN _ A end; the positive electrode of the optocoupler OC1 is connected with the collector of the triode Q3, the remote emitter of the triode Q3 is grounded, and the base electrode of the triode Q3 is connected with the WINOUT end after being connected with the resistor R5 in series; the negative electrode of the optical coupler OC1 is connected with the +20V end after being connected with the resistor R4 in series; the resistor R3 and the light emitting diode LED3 are connected in series and then connected in parallel between the resistor R4 and the collector of the triode Q3;
the seventh sub-control circuit comprises a serial port J4, and pins 1, 3, 6, 8 and 10 of the serial port J4 are respectively connected with a TRA2 terminal, a TRA1 terminal, a WIN _ B terminal, a WIN _ A terminal and an SRT terminal; pin 12 of serial port J4 is connected to ground.
2. A voltage withstand test leakage current collection circuit according to claim 1, wherein: the U1 unit is a single chip microcomputer with the model number SC92F7252M 20.
3. A voltage withstand test leakage current collection circuit according to claim 1, wherein: the optical coupler OC2 is a photoelectric coupler with the model number of MOC 3063.
4. A voltage withstand test leakage current collection circuit according to claim 1, wherein: the optical coupler OC1 is an optical coupler with the model number EL 817.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023065540.8U CN214041636U (en) | 2020-12-18 | 2020-12-18 | Withstand voltage test leakage current acquisition circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023065540.8U CN214041636U (en) | 2020-12-18 | 2020-12-18 | Withstand voltage test leakage current acquisition circuit |
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| Publication Number | Publication Date |
|---|---|
| CN214041636U true CN214041636U (en) | 2021-08-24 |
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|---|---|---|---|
| CN202023065540.8U Withdrawn - After Issue CN214041636U (en) | 2020-12-18 | 2020-12-18 | Withstand voltage test leakage current acquisition circuit |
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| CN (1) | CN214041636U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112505514A (en) * | 2020-12-18 | 2021-03-16 | 中山市优胜电子科技有限公司 | Withstand voltage test leakage current acquisition circuit |
-
2020
- 2020-12-18 CN CN202023065540.8U patent/CN214041636U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112505514A (en) * | 2020-12-18 | 2021-03-16 | 中山市优胜电子科技有限公司 | Withstand voltage test leakage current acquisition circuit |
| CN112505514B (en) * | 2020-12-18 | 2024-06-18 | 中山市优胜电子科技有限公司 | Withstand voltage test leakage current acquisition circuit |
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