CN213937840U - Digital power amplifier - Google Patents
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- CN213937840U CN213937840U CN202120157920.XU CN202120157920U CN213937840U CN 213937840 U CN213937840 U CN 213937840U CN 202120157920 U CN202120157920 U CN 202120157920U CN 213937840 U CN213937840 U CN 213937840U
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Abstract
The utility model provides a digital power amplifier, including digital controller, drive module, state acquisition module, the redundant module of n power amplifiers, m power amplifier, power synthesis module and filtering module, digital controller is used for gathering and buffer memory input signal to carry out pulse width modulation with input signal and produce 2n group PWM control signal, still be used for receiving state acquisition module gathers state information, and discernment behind the fault information among the state information, control the power amplifier module operation that the redundant module replacement of power amplifier broke down or control the redundant module of power amplifier with not breaking down the operation is redistributed to the power amplifier module, and to the bypass control signal is sent to power synthesis module. According to the scheme, the state acquisition module acquires the running state of each module in real time, the power redundancy module is used for replacing the power amplifier module which sends faults to run, online fault processing is carried out, and the reliability and the service life of the amplifier are greatly improved.
Description
Technical Field
The utility model relates to a power electronic technology field especially relates to a digital power amplifier.
Background
Since the 21 st century, power electronic technology has been developed at a high speed, and power amplifiers have been widely used in many fields of social life. The traditional analog power amplifier and the AB type power amplifier have low efficiency, large volume and heavy weight, while the digital power amplifier has simple structure, high transmission efficiency and easy integration, and has obvious advantages in the aspects of volume, weight, efficiency, reliability and the like.
Due to the limitations of the technology level and technology of the power switch device, the power grade and the switching frequency of the single-module digital power amplifier are limited, and the requirements of certain application occasions with medium, high and low distortion degrees are difficult to meet. In order to solve the problem, the currently known high-power digital power amplifier mostly adopts power tubes with higher power levels in series or parallel connection or power module cascade connection so as to meet the requirement of high power.
However, due to the non-ideal switching characteristic of the device, the equivalent input capacitance is increased after series-parallel combination, the actual switching frequency is further reduced, the distortion degree of the digital power amplifier is deteriorated, and the size of the filtering module is increased. In addition, since the characteristics of each device or module cannot be completely the same, the voltage and current experienced by each device or module are not uniform, the reliability of the system is deteriorated, and the service life of the device and the system is seriously affected.
Disclosure of Invention
The present invention aims to solve the above-described problems. It is an object of the present invention to provide a digital power amplifier that solves any of the above problems. Specifically, the utility model provides a can effectively improve output, reduce high reliability, the modular digital power amplifier of degree of distortion.
In order to achieve the above object, the present invention provides a digital power amplifier, which includes a digital controller, a driving module, a state collecting module, n power amplifier modules, m power amplifier redundant modules, a power synthesizing module and a filtering module, wherein n is an integer greater than 0, and m is an integer greater than or equal to 0;
the digital controller is used for collecting and caching input signals and carrying out pulse width modulation on the input signals to generate 2n groups of PWM control signals, the frequency of the 2n groups of PWM control signals is the same, the phase difference of the 2n groups of PWM control signals is pi/n in sequence, and the duty ratio of the PWM control signals is in direct proportion to the amplitude of the input signals; each set of PWM control signals comprises two PWM signals with complementary levels;
the driving module is positioned between the digital controller and the n power amplification modules and is used for amplifying 2n groups of PWM control signals;
the power amplifier module is used for amplifying the signal output by the driving module, and the power amplifier redundant module is used for replacing the power amplifier module which has a fault;
the state acquisition module is used for acquiring state information of the driving module and each power amplifier module, wherein the state information comprises normal operation state information and fault information; the digital controller is also used for receiving the state information acquired by the state acquisition module, identifying fault information in the state information, controlling the power amplifier redundant module to replace a power amplifier module with a fault to operate or controlling the power amplifier redundant module and the power amplifier module without the fault to redistribute and operate, and sending a bypass control signal to the power synthesis module;
the power synthesis module is used for receiving the bypass control signal output by the digital controller and synthesizing the power signal output by the power amplification module;
the filtering module is used for filtering the power signal output by the power synthesis module to generate an analog power signal.
The digital controller comprises a sampling/caching module, a delay/timer, a fault processing module, 2n digital PWM modulators and an output signal distribution module which run in parallel under the same clock beat;
the sampling/buffer module is used for receiving input signals, carrying out digital quantization and buffer on the input signals, and then transmitting the input signals to the 2n digital PWM modulators;
the fault processing module is used for receiving the state information acquired by the state acquisition module, identifying fault information in the state information and a power amplifier module which has a fault and corresponds to the fault information, counting the number k of the power amplifier modules which have the fault, sending the number k to the delay/timer, sending an enable control signal EN to the output signal distribution module, and sending a bypass control signal Ei to the power synthesis module;
the delay/timer is used for receiving a start-stop signal and sending out 2n paths of phase trigger signals with time intervals sequentially different by T/(2n) to the 2n digital PWM modulators, wherein T is the carrier period of the digital PWM modulators; the digital PWM modulator is also used for receiving the number k of the power amplifier modules with faults, comparing and judging the size of k and the size of m, and sending corresponding phase trigger signals to the 2n digital PWM modulators according to the judgment result;
the 2n digital PWM modulators are used for completing PWM modulation of the signals output by the sampling/caching module; the phase trigger signal is also used for controlling the carrier phase of the output PWM control signal according to the phase trigger signal after receiving the phase trigger signal;
and the output signal distribution module is used for receiving an enable control signal EN and then sending a PWM control signal to the driving module and the power amplification module corresponding to the enable control signal EN according to the enable control signal EN.
And the time delay/timer is further used for recalculating the phase triggering time interval of the digital PWM modulator to be T/(2 x (n + m-k)) when the number k of the power amplifier modules with faults is larger than the number m of the redundant power amplifier modules, and sending the 2 x (n + m-k) paths of reset phase triggering signals to the 2 x (n + m-k) digital PWM modulators.
Each digital PWM modulator comprises a counter and a comparator which are arranged in a one-to-one correspondence mode, wherein the counter is started by a corresponding phase trigger signal output by the delay/timer to generate a periodic digital triangular modulation carrier; and the comparator is used for comparing the counting value of the counter with the digital quantization value of the input signal in real time and outputting the PWM control signal.
Wherein, the pulse width modulation of the input signal generates 2n groups of PWM control signals, and the method comprises the following steps: and carrying out pulse width modulation on the input signal and 2n digital triangular modulation carriers with the same frequency and the phase difference of pi/n in sequence to generate 2n groups of PWM control signals.
The power amplifier module comprises H-bridge circuits, and two power switch devices of the same group of each H-bridge circuit receive the same group of PWM control signals output by the driving module.
The power synthesis module is a combined transformer and comprises n + m primary windings and n + m secondary windings, each primary winding is connected with the output end of the power amplification module or the power amplification redundancy module in a one-to-one correspondence mode, and the secondary windings are sequentially connected in series end to end.
When the power amplifier module fails, the digital controller controls the bypass switches corresponding to the failed power amplifier module to be closed and the bypass switches corresponding to the power amplifier redundant modules with the same number as the failed power amplifier modules to be opened.
Wherein the filtering module comprises an LC passive low-pass filter.
The digital power amplifier of the utility model realizes the adjustment of output power by adjusting the number of the power amplifier modules participating in the operation and the number of the windings of the power synthesis module, thereby meeting the requirements of different power application occasions; the digital controller is used for generating PWM control signals with the same frequency and sequentially staggered phase differences to drive the power amplifier module to operate, so that the harmonic content in a synthesized waveform is greatly reduced, the mention of a filtering module can be greatly reduced, and the distortion degree is obviously improved; meanwhile, the state acquisition module acquires the running state of each module in real time, and the power redundancy module is used for replacing the power amplifier module which sends faults to run, so that the on-line fault processing is carried out, the reliability of the amplifier is greatly improved, and the service life of the amplifier is greatly prolonged.
Other characteristic features and advantages of the invention will become apparent from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the invention. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1 schematically shows a structure of a digital power amplifier according to the present invention;
FIG. 2 is a schematic diagram illustrating an exemplary configuration of a digital controller;
FIG. 3 illustrates an operating waveform diagram of the digital PWM modulator;
fig. 4 schematically shows a circuit diagram of a power amplifier module;
fig. 5 schematically shows a structure of the power combining module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The inventor designs a high-reliability modular digital power amplifier, which mainly utilizes a plurality of power amplifier modules to amplify signals and then synthesizes the signals through a power synthesis module, and in practical application, the size of output power can be adjusted by adjusting the number of the used power amplifier modules and the number of windings of the power synthesis module so as to be suitable for various application occasions with different power requirements; and each power amplifier module only needs to amplify a group of PWM control signals, and the circuit structure of each power amplifier module is the same, so that the topological circuit structure of the digital power amplifier is simple, the modularization degree is high, and the expansion and maintenance are easy. The digital controller generates a plurality of groups of PWM control signals with the same frequency and sequentially staggered phase differences, the driving module drives the power amplifier module to operate and amplify after primary amplification, and the PWM control signals are synthesized by the power synthesis module, so that the harmonic content of the synthesized total output waveform is greatly reduced, the mention of the filtering module can be greatly reduced, the distortion of the signals is also obviously improved, and the requirements on low distortion and high power amplification factor are met. In addition, a power amplifier redundancy module is also arranged and used for replacing the power amplifier redundancy module when the active power amplifier module fails so as to ensure the normal operation of the digital power amplifier; the state acquisition module is used for acquiring the running state of each module in real time and feeding the running state back to the digital controller, the digital controller judges the number and the position of the power amplifier modules with faults, the PWM control signals are adjusted to be not output to the power amplifier modules with faults any more, the power amplifier modules with faults are replaced and run by the power amplifier redundancy module, and meanwhile, the running winding of the power synthesis module is correspondingly adjusted, so that the on-line fault processing of the power amplifier modules is realized, and the running stability and the reliability of the power amplifier are ensured.
The digital power amplifier according to the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 shows the structure diagram of a specific embodiment of the digital power amplifier of the present invention, as shown in fig. 1, the digital power amplifier of the present invention includes a digital controller 1, a driving module 2, a state acquisition module 3, n power amplifier modules 4, m power amplifier redundant modules 40, a power synthesis module 5 and a filtering module 6, wherein n is an integer greater than 0, and m is an integer greater than or equal to 0. The digital controller 1 is configured to collect and buffer an input signal, for example, sample and buffer an analog signal, and perform pulse width modulation on the input signal to generate 2n groups of PWM control signals, where the 2n groups of PWM control signals have the same frequency and sequentially have a phase difference of pi/n, and a duty ratio of the PWM control signals is proportional to an amplitude of the input signal.
The specific process of generating 2n groups of PWM control signals by performing pulse width modulation on the input signals comprises the following steps: and carrying out pulse width modulation on the input signal and 2n digital triangular modulation carriers with the same frequency and the sequential phase difference of pi/n to generate 2n groups of PWM control signals.
For example, n is 4, m is 1, that is, 4 power amplifier modules 4 and 1 power amplifier redundant module 40 are provided, and correspondingly, after the digital controller 1 completes the analog signal sampling, the digital controller performs PWM pulse width modulation on the sampled signal and 8 digital triangular modulation carriers with the same frequency and sequentially different phase by pi/4, and generates 8 sets of PWM control signals with the same frequency.
Wherein each set of PWM control signals comprises two PWM signals with complementary levels, and the duty ratio thereof is proportional to the amplitude of the collected input signal (i.e. the sampled signal, i.e. the collected analog signal).
The driving module 2 is located between the digital controller 1 and the n power amplifier modules 4, and is configured to receive and amplify 2n groups of PWM control signals sent by the digital controller 1, and complete amplification of the PWM control signals, so as to ensure that the power amplifier modules 4 and the power amplifier redundancy module 40 can be driven.
The power amplifier module 4 is used for amplifying the signal output by the driving module 2, and the power amplifier redundant module 40 is used for replacing the power amplifier module 4 with a fault to operate, so that when the power amplifier module 4 has a fault, the digital power amplifier can still operate continuously and stably, and the service life, the operation stability and the reliability of the digital power amplifier are improved.
The state acquisition module 3 is used for acquiring state information of the driving module 2, each power amplifier module 4 and the power amplifier redundancy module 40, and sending the acquired state information to the digital controller 1, wherein the state information includes normal operation state information and fault information. Correspondingly, the digital controller 1 is further configured to receive the state information acquired by the state acquisition module 3, identify fault information in the state information, determine the number and the position of the power amplifier modules 4 with faults, and then control the power amplifier redundant module 40 to replace the power amplifier modules 4 with faults or control the power amplifier redundant module 40 and the power amplifier modules 4 without faults to redistribute operation.
Specifically, after the digital controller 1 receives the state information sent by the state acquisition module 3, if the number of the power amplifier modules 4 with faults is determined to be k, the fault number k of the power amplifier modules 4 is compared with the number m of the power amplifier redundant modules 40: if k is less than or equal to m, controlling k power amplifier redundant modules 40 to replace the power amplifier module 4 with the fault one by one for operation; if k is larger than m, 2(n + m-k) groups of PWM control signals are redistributed and operated to the (n-k) power amplifier modules 4 and the m power amplifier redundant modules 40 which do not have faults; meanwhile, the bypass control information for the failed power amplifier module 4 is sent to the power synthesis module 5.
The power synthesis module 5 is configured to synthesize power signals output by the power amplifier modules 4 or the power amplifier modules 4 and the power amplifier redundancy module 40 into a signal, which is a signal obtained by performing power amplification by the digital power amplifier. Meanwhile, the power synthesis module 5 is further configured to receive a bypass control signal output by the digital controller 1, and is configured to, when the active amplifier module 4 fails, adjust, according to the bypass control signal, a winding corresponding to a signal path position of the failed power amplifier module 4 to be turned off (a bypass switch is turned on), and adjust a winding corresponding to a signal path position of the power amplifier redundant module 40 that replaces operation to operate, or control, according to the bypass control signal, a winding corresponding to a signal path of the power amplifier module 4 and the power amplifier redundant module 40 that is redistributed to operate, so as to complete fault bypass processing of the power amplifier module 4.
The filtering module 6 is configured to filter the power signal output by the power combining module 5 to generate a high-power analog power signal, where the analog power signal is an analog power signal obtained by performing power amplification on the digital power amplifier according to the present disclosure and is used to drive a terminal load.
Fig. 2 shows a schematic structural diagram of the digital controller 1 in a specific embodiment. Referring to fig. 2, the digital controller 1 includes a sampling/buffering module 11, a delay/timer 12, a fault handling module 13, 2n digital PWM modulators 14, and an output signal distribution module 15 that operate in parallel at the same clock cycle. As shown in the figure, in the present embodiment, n is 4, i.e., 2n is 8.
The sampling/buffering module 11 is configured to receive an input signal, perform digital quantization and buffering on the input signal, and then transmit the input signal to the 2n digital PWM modulators 14.
The delay/timer 12 is configured to receive an input start-stop signal, and send 8 phase trigger signals TRG 1-TRG 8 with time intervals of 8 paths sequentially different by T/8 to the 8 digital PWM modulators 14, so as to trigger the digital PWM modulators 14, thereby implementing control of the triangular modulation carrier phase of the digital PWM modulators 14. Where T is the carrier period of the digital PWM modulator 14.
The fault processing module 13 is configured to receive the state information acquired by the state acquisition module 3, identify the fault information in the state information and the power amplifier module 4 having the fault corresponding to the fault information, count the number k of the power amplifier modules 4 having the fault, send the count to the delay/timer 12, send an enable control signal EN (shown as EN 1-ENn) to the output signal distribution module 15, and send a bypass control signal Ei to the power synthesis module 5. Correspondingly, the delay/timer 12 is further configured to receive the number k of the power amplifier modules 4 with faults sent by the fault processing module 13, compare and judge the number k of the faults with the number m of the power amplifier redundant modules 40, and send corresponding phase trigger signals to the 8 digital PWM modulators 14 according to the judgment result.
8 digital PWM modulators 14 are used for completing PWM modulation of the signals output by the adoption/buffer module 11; and is further configured to control the carrier phase of the output PWM control signal according to the phase trigger signal after receiving the phase trigger signal sent by the delay/timer 12.
The output signal distribution module 15 is configured to, after receiving the enable control signal EN sent by the fault processing module 13, distribute the PWM control signal to the power amplifier module 4 and the power amplifier redundancy module 40 corresponding to the PWM control signal sent to the 2n digital PWM modulators according to the enable control signal, so as to drive the power amplifier module 4 that does not fail and select the power amplifier redundancy module 40 to operate instead of the power amplifier module 4 that fails, avoid the power amplifier module 4 that fails, and ensure normal operation and power amplification effect of the amplifier.
In an optional embodiment, the delay/timer 12 is further configured to determine whether the number k of the failed power amplifier modules 4 is greater than the number m of the power amplifier redundant modules 40, and specifically includes: when the number k of the power amplifier modules 4 with faults is judged to be larger than the number m of the power amplifier redundant modules 40, the phase triggering time interval of the 2n digital PWM modulators 14 is recalculated to be T/(2 x (n + m-k)), and the 2 x (n + m-k) paths of reset phase triggering signals are sent to the 2 x (n + m-k) digital PWM modulators 14. The reset phase trigger signal is a restart signal for (n-k) power amplifier modules 4 which do not have faults and m power amplifier redundant modules 40, and the acquired input signal is redistributed according to the signal paths of the (n + m-k) power amplifier modules 4 which do not have faults and the power amplifier redundant modules 40 and then is sent. In the present embodiment, the reset phase trigger signal is sent to 2 × (4+ m-k) digital PWM modulators 14. And 2 x (4+ m-k) digital PWM modulators 14 modulate the PWM carrier according to the reset phase trigger signal and then output PWM control signals corresponding to the reset signal, so as to drive (n-k) power amplifier modules 4 without faults and m power amplifier redundant modules 40 to operate according to the reset rules in the reset signal.
Fig. 3 shows an operation waveform diagram of the digital PWM modulator in this embodiment, and in combination with fig. 2 and 3, each digital PWM modulator 14 includes a counter 141 and a comparator 142 arranged in a one-to-one correspondence. Wherein, the counter 141 is started by the corresponding phase trigger signal output by the delay/timer 12, and continuously counts up, down and up to generate a periodic digital triangular modulation carrier; the comparator 142 is configured to compare the count value of the counter 141 with the digital quantization value of the input signal in real time at a clock beat to output a modulated PWM control signal, which is a PWM signal with two complementary levels and a duty ratio proportional to the input signal amplitude value.
For example, the counter 141 of the first digital PWM modulator 14 is started by the phase trigger TRG1 output from the delay/timer 12, and starts counting up from zero at the clock time of the clock CLK, and starts counting down to zero when the count reaches the period count value, and thus the cycle is repeated to generate the digital triangular modulated carrier with the period T. The corresponding comparator 142 compares the count value of the counter 141 with the value of the acquired input signal in real time, and when the value of the acquired input signal is greater than or equal to the value of the counter 141, the PWM1 output end of the comparator 142 outputs a high level and/or the PWM1 output end outputs a low level; when the value of the input signal is smaller than the value of the counter 141, the PWM1 output terminal of the comparator 142 outputs a low level, and the/PWM 1 output terminal outputs a high level, so as to generate two PWM control signals with complementary levels and the duty ratio being linearly proportional to the amplitude value of the input signal. The PWM control signal is input into a power amplification module 4 through a driving module 2 for power amplification, then is synthesized by a power synthesis module 5, and is filtered by a filtering module 6, namely the input signal is the signal after power amplification.
S in FIG. 3aIs the waveform of the input signal (i.e., the sampled analog signal); the PWM1, the PWM2, the PWM3 and the PWM 4-PWM 8 are sequentially PWM signals output by 8 comparators 142; cc1、Cc2、Cc3、Cc4The triangular modulation carriers generated by the 4 counters 141 corresponding to the PWM 1-PWM 4 signals one by one are sequentially, and the triangular modulation carriers generated by the other 4 counters 141 are not shown in the figure; so1The power synthesis module 5 synthesizes the power of the signal output by the power amplification module 4 in operation to obtain the waveform of the output signal; soIs the waveform of the output signal filtered by the filtering module 6, i.e. the methodThe digital power amplifier amplifies the power and outputs the amplified signal to the signal waveform of the load.
In this scheme, the power amplifier redundant module 40 is set for replacing the failed power amplifier module 4, so the structure of the power amplifier redundant module 40 is the same as that of the power amplifier module 4, that is, it can be considered that n + m power amplifier modules 4 are set in one digital power amplifier, where n power amplifier modules 4 are used as normal operation, and m are used as standby power amplifier modules.
It should be noted that, in the actual implementation process, the adjacent power amplifier modules 4 may be electrically isolated from each other, so as to reduce the electrical interference and insulation requirements between the power amplifier modules 4, and improve the electrical fault isolation capability of the power amplifier modules 4 and the reliability of the entire power amplifier.
In an alternative embodiment, the power amplifier module 4 includes H-bridge circuits, and two power switches in the same group of each H-bridge circuit receive the same group of PWM control signals output by the driving module 2.
Fig. 4 shows a schematic structural diagram of a specific embodiment of the power amplifier module 4, in this embodiment, the power amplifier module 4 is formed by connecting four sets of power switch modules with the same circuit structure in an H-bridge manner, and each set of power switch module includes a power switch device Q with a freewheeling diode. The power switch device Q may be an insulated gate bipolar transistor IGBT or a semiconductor field effect transistor MOSFET or a silicon carbide MOSFET.
Referring to fig. 4, the gate of the igbt Q1 in the first power switch module is connected to the PWM1 signal preliminarily amplified by the driver module 2, the emitter of the igbt Q1 in the first power switch module is connected to the collector of the igbt Q2 in the second power switch module and the output terminal OUT1+ of the H-bridge power amplifier module, and the collector of the igbt Q1 in the second power switch module is connected to the positive electrode of the DC power supply DC; the grid electrode of an insulated gate bipolar transistor Q2 in the second power switch module is connected with a/PWM 1 signal preliminarily amplified by the driving module 2, and the emitter electrode of the insulated gate bipolar transistor Q2 is connected with the negative electrode of the direct-current power supply DC; the grid electrode of an insulated gate bipolar transistor Q3 in the third power switch module is connected with a PWMn +1 signal preliminarily amplified by the driving module 2, the emitter electrode of the insulated gate bipolar transistor Q4 in the fourth power switch module is respectively connected with the collector electrode of an insulated gate bipolar transistor Q4 in the fourth power switch module and the output end OUT 1-of the H-bridge power amplifier module, and the collector electrode of the insulated gate bipolar transistor Q3 in the third power switch module is connected with the positive electrode of a direct-current power supply DC; the grid electrode of an insulated gate bipolar transistor Q4 in the fourth power switch module is connected with a/PWMn +1 signal preliminarily amplified by the driving module 2, and the emitter electrode of the insulated gate bipolar transistor Q4 is connected with the negative electrode of the direct-current power supply DC.
Fig. 5 shows a schematic diagram of a specific embodiment of the power combining module 5, and as shown in fig. 5, in this scheme, the power combining module 5 is a combined transformer and includes n + m primary windings and n + m secondary windings, each primary winding is connected to the output ends of the power amplifier modules 4 or the power amplifier redundancy modules 40 in a one-to-one correspondence manner, and the secondary windings are sequentially connected in series end to end for performing power combining on the power signals output by each operating power amplifier module 4 or each operating power amplifier module 4 and the power amplifier redundancy module 40, so as to form a combined digital signal.
When the power amplifier module 4 fails, the digital controller 1 controls the bypass switch corresponding to the failed power amplifier module 4 to be closed and controls the bypass switches corresponding to the power amplifier redundant modules 40 with the same number as the failed power amplifier module to be opened, so that the bypass processing of the failed power amplifier module 4 is realized, and the normal and stable operation of the digital power amplifier is ensured.
The power synthesis module 5 synthesizes the amplified signals output by each operating power amplifier module 4 and/or power amplifier redundancy module 40 to form a path of amplified digital power signal, the output end OUT +/-transmits the synthesized digital power signal to the filtering module 6, and the filtering module 6 filters the digital power signal to form a path of high-power analog power signal for output.
In an alternative embodiment, the filtering module 6 may employ an LC ladder filter network formed by an LC passive low-pass filter, and is configured to filter the power signal output by the power combining module 5 to generate the high-power analog power signal.
The above-described embodiments can be implemented individually or in various combinations, and such variations are within the scope of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (9)
1. A digital power amplifier is characterized by comprising a digital controller (1), a driving module (2), a state acquisition module (3), n power amplifier modules (4), m power amplifier redundant modules (40), a power synthesis module (5) and a filtering module (6), wherein n is an integer greater than 0, and m is an integer greater than or equal to 0;
the digital controller (1) is used for acquiring and buffering input signals and carrying out pulse width modulation on the input signals to generate 2n groups of PWM control signals, the frequency of the 2n groups of PWM control signals is the same, the phase difference of the 2n groups of PWM control signals is pi/n in sequence, and the duty ratio of the PWM control signals is in direct proportion to the amplitude of the input signals; each set of PWM control signals comprises two PWM signals with complementary levels;
the driving module (2) is positioned between the digital controller (1) and the n power amplifier modules (4) and is used for amplifying 2n groups of PWM control signals;
the power amplifier module (4) is used for amplifying the signal output by the driving module (2), and the power amplifier redundant module (40) is used for replacing the power amplifier module (4) which fails;
the state acquisition module (3) is used for acquiring state information of the driving module (2) and each power amplifier module (4), and the state information comprises normal operation state information and fault information; the digital controller (1) is further configured to receive the state information acquired by the state acquisition module (3), identify fault information in the state information, control the power amplifier redundant module (40) to replace the power amplifier module (4) with the fault to operate or control the power amplifier redundant module (40) and the power amplifier module (4) without the fault to redistribute operation, and send a bypass control signal to the power synthesis module (5);
the power synthesis module (5) is used for receiving the bypass control signal output by the digital controller (1) and synthesizing the power signal output by the power amplification module (4);
the filtering module (6) is used for filtering the power signal output by the power synthesis module (5) to generate an analog power signal.
2. Digital power amplifier according to claim 1, characterized in that the digital controller (1) comprises a sample/buffer module (11), a delay/timer (12), a fault handling module (13), 2n digital PWM modulators (14) and an output signal distribution module (15) running in parallel at the same clock beat;
the sampling/buffering module (11) is used for receiving an input signal, performing digital quantization and buffering on the input signal, and then transmitting the input signal to the 2n digital PWM modulators (14);
the fault processing module (13) is configured to receive the state information acquired by the state acquisition module (3), identify fault information in the state information and a power amplifier module (4) with a fault corresponding to the fault information, count the number k of the power amplifier modules (4) with the fault, send the count to the delay/timer (12), send an enable control signal EN to the output signal distribution module (15), and send a bypass control signal Ei to the power synthesis module (5);
the delay/timer (12) is configured to receive a start-stop signal, and send out 2n phase trigger signals with sequential phase difference of T/(2n) at time intervals to the 2n digital PWM modulators (14), where T is a carrier period of the digital PWM modulator (14); the digital PWM modulator is also used for receiving the number k of the power amplification modules (4) with faults, comparing and judging the size of k and m, and sending corresponding phase trigger signals to the 2n digital PWM modulators (14) according to the judgment result;
the 2n digital PWM modulators (14) are used for completing PWM modulation of the signals output by the sampling/buffer module (11); the phase trigger signal is also used for controlling the carrier phase of the output PWM control signal according to the phase trigger signal after receiving the phase trigger signal;
and the output signal distribution module (15) is used for sending a PWM control signal to the corresponding power amplification module (4) according to the enable control signal EN after receiving the enable control signal EN.
3. The digital power amplifier of claim 2, wherein the delay/timer (12) is further configured to recalculate the phase trigger time interval of the digital PWM modulator (14) to be T/(2 x (n + m-k)) when the number k of failed power amplifier modules (4) is greater than the number m of the power amplifier redundancy modules (40), and send the 2 x (n + m-k) reset phase trigger signals to the 2 x (n + m-k) digital PWM modulators (14).
4. The digital power amplifier of claim 2, wherein each of the digital PWM modulators (14) comprises a counter (141) and a comparator (142) arranged in a one-to-one correspondence, wherein the counter (141) is activated by a corresponding phase trigger signal output by the delay/timer (12) to generate a periodic digital triangular modulated carrier; the comparator (142) is used for comparing the count value of the counter (141) with the digital quantization value of the input signal in real time and outputting the PWM control signal.
5. The digital power amplifier of claim 1, wherein pulse width modulating the input signal to generate 2n sets of PWM control signals comprises:
and carrying out pulse width modulation on the input signal and 2n digital triangular modulation carriers with the same frequency and the phase difference of pi/n in sequence to generate 2n groups of PWM control signals.
6. The digital power amplifier of claim 1, wherein the power amplifier module (4) comprises H-bridge circuits, and a same set of two power switches of each H-bridge circuit receives a same set of PWM control signals output by the driver module (2).
7. The digital power amplifier of claim 1, wherein the power combining module (5) is a combined transformer, and comprises n + m primary windings and n + m secondary windings, each primary winding is connected to the output end of the power amplifier module (4) or the power amplifier redundancy module (40) in a one-to-one correspondence manner, and each secondary winding is connected in series end to end in sequence.
8. The digital power amplifier according to claim 7, wherein each output terminal of the secondary winding is connected in parallel with a bypass switch, and when there is a failure of the power amplifier module (4), the digital controller (1) controls the bypass switches corresponding to the failed power amplifier module (4) to be closed and the bypass switches corresponding to the power amplifier redundancy modules (40) having the same number as the failed power amplifier module (4) to be opened.
9. Digital power amplifier according to claim 1, characterized in that the filtering module (6) comprises an LC passive low-pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120157920.XU CN213937840U (en) | 2021-01-20 | 2021-01-20 | Digital power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120157920.XU CN213937840U (en) | 2021-01-20 | 2021-01-20 | Digital power amplifier |
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|---|---|
| CN213937840U true CN213937840U (en) | 2021-08-10 |
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| CN202120157920.XU Active CN213937840U (en) | 2021-01-20 | 2021-01-20 | Digital power amplifier |
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| CN (1) | CN213937840U (en) |
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