CN213934702U

CN213934702U - VPX integrated circuit board

Info

Publication number: CN213934702U
Application number: CN202023333713.XU
Authority: CN
Inventors: 李国超; 田成
Original assignee: Hunan Bojiang Information Technology Co Ltd
Current assignee: Hunan Bojiang Information Technology Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-08-10
Anticipated expiration: 2030-12-30

Abstract

The utility model discloses a VPX board card, which comprises a bottom plate, a CPU control unit arranged on the bottom plate, a bridge plate, a storage disc, an MAC controller and a video interface; the CPU control unit adopts an LS3A4000-I processor chip and is connected with the bridge chip through an HT bus; the CPU control unit comprises 2 DDR4 controllers, and the memory of each DDR4 controller is 8 GB; the bridge chip is a Loongson 7A1000 bridge chip and is provided with 16-bit HT3.0 interfaces and 5 PCIE2.0 interfaces; the 5 PCIE2.0 interfaces are 3 x8PCIE2.0 interfaces and 2 x4PCIE2.0 interfaces; the x4PCIE2.0 interface can be split into at least 1 SATA2.0 interface; the storage disk is connected with the SATA2.0 interface and is connected with the bottom plate in a stacking way through a connector; the MAC controller is connected with the PHY chip through an RGMII interface; the video interface adopts LTX8618 switching bridge. The utility model discloses a VPX integrated circuit board can adapt to the latest generation treater of godson, improves the operational capability, and better being applicable to the occasion that requires high to the computing power.

Description

VPX integrated circuit board

Technical Field

The utility model relates to an electronic equipment technical field, more specifically say, in particular to VPX integrated circuit board.

Background

The VPX bus is a new generation of high-speed serial bus standard developed by the vta (VME International Trade Association ) organization on the basis of its VME bus in 2007. The VME bus comes from the VME bus, and since the VME bus was born 30 years ago, as the requirement of the industry on the bus technology transmission bandwidth is continuously increased, the VME bus gradually shows disadvantages. Therefore, the situation that the requirement of the industry on the transmission bandwidth of the bus technology is continuously improved and the defects of the VME bus are gradually revealed is completely turned over when the VITA pushes the VPX bus.

The VPX bus adopts a high-speed serial bus technology to replace a parallel bus technology of a VME bus, and supports higher backboard bandwidth. And the exchange structure is adopted to replace the master control structure of the VME, so that the overall performance of the system is not limited by the master control board, and the overall performance of the system is improved. Meanwhile, under the switching structure, the processor can send data at any time without waiting for the bus to initiate transmission, and the method is particularly suitable for a multiprocessor system.

Therefore, the VPX board corresponding to the VPX bus is also rapidly developed, the home-made VPX board is mainly a loongson CPU 3U VPX board, but most processors on the loongson CPU 3U VPX board are LS3a3000, the loongson VPX board is a previous-generation processor of loongson companies, the memory of the loongson processor is generally lower than 8GB, and the master frequency and the performance cannot meet the requirements of the computing capacity of a complex system.

Therefore, it is an urgent need to solve the problem of designing a VPX board that can adapt to the latest generation of loongson processors.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to provide a VPX integrated circuit board, can adapt to the latest generation treater of godson, improve the operational capability, the better occasion that is applicable to the computing power requirement height solves current VPX integrated circuit board because the memory is generally lower, dominant frequency and performance can not keep up with the problem of complex system computing power.

In order to achieve the above purpose, the technical scheme of the utility model is as follows:

a VPX board card comprises a bottom plate, a CPU control unit, a bridge plate, a storage disc, an MAC controller and a video interface, wherein the CPU control unit, the bridge plate, the storage disc, the MAC controller and the video interface are arranged on the bottom plate;

the CPU control unit adopts an LS3A4000-I processor chip and is connected with the bridge chip through an HT bus;

the CPU control unit comprises 2 DDR4 controllers, and the memory of each DDR4 controller is 8 GB;

the bridge chip is a Loongson 7A1000 bridge chip and is provided with 16-bit HT3.0 interfaces and 5 PCIE2.0 interfaces;

the 5 PCIE2.0 interfaces are 3 x8PCIE2.0 interfaces and 2 x4PCIE2.0 interfaces;

the x4PCIE2.0 interface can be split into at least 1 SATA2.0 interface;

the storage disk is connected with the SATA2.0 interface and is connected with the bottom plate in a stacking way through a connector;

the MAC controller is connected with the PHY chip through an RGMII interface;

the video interface adopts an LTX8618 switching bridge chip.

Preferably, the x8PCIE2.0 interface can be split into 2 independent x4PCIE2.0 interfaces.

Preferably, the x4PCIE2.0 interface can be split into 6 independent x1PCIE2.0 interfaces and 3 SATA2.0 interfaces.

Preferably, the MAC controller is 2 adaptive gigabit ethernet interfaces, and all of them are in 1000BASE-X mode.

Preferably, the video interface is used for converting the RGB888 format video signal into DVI video output.

Preferably, the bridge chip is connected with the VPX bus through 2 paths of 1000BASE-X led out of the PHY chip.

Preferably, the PHY chip is specifically a GMAC PHY chip.

Preferably, the video memory terminal of the bridge piece is connected with the impedance network.

The utility model provides a VPX integrated circuit board, adopt LS3A4000 as the CPU control unit, through godson 7A1000 bridge plate, connector formula memory disc and its cooperation, and pass through RGMII interface connection PHY chip with the MAC controller, video interface adopts LTX8618 switching bridge plate, the effectual 16G memory capacity who matches LS3A4000, can adapt to the newest generation treater of godson, improve the operational capability, better be applicable to the occasion that requires high to the computational capability, solve current VPX integrated circuit board because the memory is generally lower, dominant frequency and performance can not follow up the problem of complex system computational capability.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a VPX board card provided in an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, a VPX board card provided by an embodiment of the present invention includes a bottom board, and a CPU control unit 1, a bridge chip 2, a storage disk 3, an MAC controller 4, and a video interface 5 that are arranged on the bottom board;

the CPU control unit 1 adopts an LS3A4000-I processor chip and is connected with the bridge chip 2 through an HT bus;

the CPU control unit 1 comprises 2 DDR4 controllers, and the memory of each DDR4 controller is 8 GB;

the bridge chip 2 adopts a Loongson 7A1000 bridge chip and is provided with 16-bit HT3.0 interfaces and 5 PCIE2.0 interfaces;

the 5 PCIE2.0 interfaces are 3 x8PCIE2.0 interfaces and 2 x4PCIE2.0 interfaces;

the x4PCIE2.0 interface can be split into at least 1 SATA2.0 interface;

the storage disk 3 is connected with the SATA2.0 interface and is connected with the bottom plate in a stacking way through a connector;

the MAC controller 4 is connected with the PHY chip through an RGMII interface;

the video interface 5 employs LTX8618 to interface with the bridge piece 2.

The LS3A4000-I processor core of the board card of the embodiment is a Loongson 3A 4000-I. The LS3A4000-I processor chip is a microstructure upgrading version of A3A 3000/3B3000 quad-core processor, the same 28nmFD-SOI technology is adopted, and a packaging pin is newly defined. The Loongson 3A4000 is a processor configured as a single-node 4-core, the working main frequency is 1.5 GHz-2.0 GHz, 4 64-bit four-emission superscalar GS464v high-performance processor cores are integrated in a chip, and the peak floating point operation capacity is 128GFlops @2.0 GHz. The chip is integrated with 8MB of split shared three-level Cache, 2 72-bit DDR4 controllers (supporting DDR4-2400), 2 16-bit HT controllers, 2I 2C, 2 UARTs, 1 SPI and 16 GPIO interfaces, and the power consumption of the chip is 35W.

Compared with the LS3A3000 adopted by the existing board card, the board card of the embodiment adopts LS3A4000, and the memory capacity is improved to 16GB besides the improvement of the operational capability. In addition, the connector of the storage disk 3 adopts a connector assembly mode and is structurally connected with the bottom plate in a stacking mode, so that the expandability of the system is ensured, and the heat dissipation performance and the reliability of the system are improved.

In practical use, besides the processing chip and the bridge chip 2, the specific model and type of each component or module may be selected according to the requirement, for example, the video interface 5 in this embodiment uses a rong switching bridge chip 2LTX8618 (the specific model is LT8618SXB), while the MAC controller 4 uses a half-duplex/full-duplex adaptive ethernet MAC controller 4, and the PHY chip uses JM88E 1111.

The VPX board card provided by the embodiment adopts LS3A4000 as a CPU control unit 1, an LS3A 1000 bridge plate 2 is adopted, a connector type storage disk 3 is matched with the CPU, an MAC controller 4 is connected with a PHY chip through an RGMII interface, a video interface 5 adopts an LTX8618 switching bridge plate 2, the 16G memory capacity of the LS3A4000 is effectively matched, the VPX board card can adapt to a latest generation processor of the Loongson, the computing capability is improved, the VPX board card is better suitable for occasions with high requirements on computing capability, and the problem that the existing VPX board card cannot keep up with the computing capability of a complex system due to the fact that the memory is generally low is solved.

The x4PCIE2.0 interface can be matched with the conventional specification function plug-in cards such as the existing solid state disk and the video card of various types, provides enough performance, can support the required transmission speed, and increases the applicability of the VPX board card.

Different from the x4PCIE2.0 interface, the x1PCIE2.0 interface can be adapted to various functional plug cards with very different specifications, such as a sound card, a network card, and a video card with short interfaces, and the bandwidth used for 1PCIE channel can meet the requirements of these devices, thereby adapting to devices and environments that cannot use PCI, or providing the device to users who do not want to use PCI. And SATA2.0 can effectively meet the matching requirement of conventional mechanical hard disks, and the diversity of storage equipment selection is improved.

Preferably, the MAC controller 4 is 2 adaptive gigabit ethernet interfaces, and all of them are in 1000BASE-X mode.

Compared with the SGMII, the compatibility is better, and the 1000BASE-X mode is adopted for meeting various requirements of other equipment, and the 1000BASE-X mode is adopted in the embodiment.

Preferably, the video interface 5 is configured to convert the RGB888 format video signal into a DVI video signal for output, that is, the board card of this embodiment uses a 16-mega true-color video signal and performs video output through the DVI, so as to meet the requirements on the definition and the reduction of the video output.

Preferably, the bridge chip 2 is connected with the VPX bus through a PHY chip leading-out 2 lines 1000 BASE-X. .

The board card of the embodiment removes a copper medium interface of RJ45, and a PHY chip is used for leading out 2 paths of 1000BASE-X to a VPX bus, so that an external environment cannot easily steal network information of the board card through a network interface, and the safety is effectively improved.

Preferably, the PHY chip is specifically a GMAC PHY chip, that is, the behavior of multiple PHYs can be managed simultaneously by 1 GMAC, so as to improve the processing efficiency.

Preferably, the video memory terminals of the bridge piece 2 are terminated with an impedance network.

In specific use, the bridge 27a1000 video memory of the embodiment adds a termination impedance network through impedance analysis, and increases the stability of the video memory, so that the image output is stable.

In the several embodiments provided in the present application, it should be understood that the disclosed devices and apparatuses may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and other division manners may be implemented in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other.

In addition, each functional module in each embodiment of the present invention may be integrated into one processor, or each module may be separately used as one device, or two or more modules may be integrated into one device; the utility model discloses each functional module in each embodiment both can adopt the form of hardware to realize, also can adopt the form of hardware with software functional unit to realize.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by program instructions and related hardware, where the program instructions may be stored in a computer-readable storage medium, and when executed, the program instructions perform the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A VPX board card is characterized by comprising a bottom plate, a CPU control unit, a bridge chip, a storage disc, an MAC controller and a video interface, wherein the CPU control unit, the bridge chip, the storage disc, the MAC controller and the video interface are arranged on the bottom plate;

the 5 PCIE2.0 interfaces are 3 x8PCIE2.0 interfaces and 2 x4PCIE2.0 interfaces;

the x4PCIE2.0 interface can be split into at least 1 SATA2.0 interface;

the MAC controller is connected with the PHY chip through an RGMII interface;

the video interface adopts an LTX8618 switching bridge chip.

2. The VPX board of claim 1, wherein the x8PCIE2.0 interface is separable into 2 separate x4PCIE2.0 interfaces.

3. The VPX board of claim 1, wherein the x4PCIE2.0 interface is separable into 6 independent x1PCIE2.0 interfaces and 3 SATA2.0 interfaces.

4. The VPX board of claim 1, wherein the MAC controller is 2 adaptive gigabit ethernet interfaces and is in 1000BASE-X mode.

5. The VPX board of claim 1, wherein the video interface is configured to convert RGB888 format video signals to DVI video output.

6. The VPX board of claim 1, wherein the bridge is in communication with a VPX bus via the PHY chip out 2 lanes 1000 BASE-X.

7. The VPX board of claim 1, wherein the PHY chip is specifically a GMAC PHY chip.

8. The VPX board of claim 1, wherein a video memory terminal of the bridge pad is terminated with an impedance network.