CN213934003U - Current measuring circuit - Google Patents
Current measuring circuit Download PDFInfo
- Publication number
- CN213934003U CN213934003U CN202022676012.XU CN202022676012U CN213934003U CN 213934003 U CN213934003 U CN 213934003U CN 202022676012 U CN202022676012 U CN 202022676012U CN 213934003 U CN213934003 U CN 213934003U
- Authority
- CN
- China
- Prior art keywords
- resistor
- channel
- operational amplifier
- terminal
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The application discloses current measurement circuit includes: the sampling resistor is connected with an input power supply and the first resistor, the other end of the sampling resistor is connected with a chip to be tested and a positive input end of the first operational amplifier, a negative input end of the first operational amplifier is connected with an output end of the first operational amplifier and a second resistor, the second resistor is connected with a negative input end of the second operational amplifier and a first end of a second channel, the first resistor is connected with a positive input end of the second operational amplifier and the first end of the first channel, an output end of the second operational amplifier is connected with a positive input end of the third operational amplifier, a fifth resistor and a sixth resistor, a negative input end of the third operational amplifier is connected with an output end of the third operational amplifier and the filter, and the filter is connected with the digital-to-analog converter; the third resistor is connected with the third end of the first channel, and the fourth resistor is connected with the second end of the first channel; the fifth resistor is connected with the third end of the second channel, and the sixth resistor is connected with the second end of the second channel.
Description
Technical Field
The utility model relates to a current measurement technical field especially relates to a variable high accuracy current measurement circuit of gain.
Background
At present, with the development of consumer electronics and wearable device technologies toward miniaturization and long endurance, strict requirements are imposed on the working current and the deep sleep current (standby current) of various chips and sensors applied to the devices, so that the current (or power consumption) measurement technology of the chips or the sensors is more and more widely applied. For example, during the mass production of chips such as fingerprint identification, touch screen control, bluetooth and the like, the current test is required. The traditional current measuring methods mainly comprise the following methods:
1. resistors are connected in series between a chip power supply pin and a power supply, and the current is calculated by dividing the voltage difference between two ends of the resistor measured by an analog-to-digital converter (ADC) by a resistance value. When the working current is measured, the current is large, the resistor with the small resistance value needs to be connected in series, so that the power supply of the chip is not influenced, and the chip cannot work normally.
2. A dedicated current measurement scheme is employed. The scheme adopts the sampling resistor with fixed resistance and small resistance, provides programmable gain, has wide measuring current range and high precision, but has higher price, high power supply voltage and is not suitable for low power supply voltage measuring environment.
SUMMERY OF THE UTILITY MODEL
The purpose of the embodiments of the present specification is to provide a current measuring circuit, and aims to provide a chip current measuring circuit which has a simple method, high precision, a wide measuring range, a variable gain, a low cost, and is suitable for a low supply voltage environment, wherein the measuring range can be from a minimum of 5 μ a to a maximum of 40mA, and the chip current measuring circuit can measure both the chip operating current and the chip deep sleep current.
An embodiment of the present application provides a current measurement circuit, including a sampling resistor, first to sixth resistors, first to third operational amplifiers, a filter, an analog-to-digital converter, and a dual-channel analog switch, the dual-channel analog switch includes a first channel and a second channel, wherein:
one end of the sampling resistor is connected with an input power supply and one end of the first resistor, the other end of the sampling resistor is connected with a chip to be tested and the positive input end of the first operational amplifier, the negative input end of the first operational amplifier is connected with the output end of the first operational amplifier and one end of the second resistor, the other end of the second resistor is connected with the negative input end of the second operational amplifier and the first end of the second channel, the other end of the first resistor is connected with the positive input end of the second operational amplifier and the first end of the first channel, the output end of the second operational amplifier is connected with the positive input end of the third operational amplifier, the fifth resistor and the sixth resistor, the negative input end of the third operational amplifier is connected with the output end of the third operational amplifier and the filter, and the filter is connected with the digital-to-analog converter;
the third resistor is connected with a third end of the first channel, and the fourth resistor is connected with a second end of the first channel;
the fifth resistor is connected with the third end of the second channel, and the sixth resistor is connected with the second end of the second channel;
and the fourth end of the first channel is connected with a first selection signal, and the fourth end of the second channel is connected with a second selection signal.
Preferably, the value range of the resistance value of the sampling resistor is 10 Ω to 100 Ω.
Preferably, the first resistor and the second resistor have the same resistance value, and the value range of the resistance value is 1K Ω to 5K Ω.
Preferably, the third resistor and the fifth resistor have the same resistance value, and the value range of the resistance value is 10K Ω to 50K Ω.
Preferably, the fourth resistor and the sixth resistor have the same resistance value, and the value range of the resistance value is 300K Ω to 500K Ω.
Preferably, the filter includes a seventh resistor and a capacitor, one end of the seventh resistor is connected to the output end of the third operational amplifier, the other end of the seventh resistor is connected to the analog-to-digital converter and the capacitor, the other end of the capacitor is connected to the ground, the value range of the seventh resistor is 1K Ω to 5K Ω, and the value range of the capacitor is 1 μ F to 10 μ F.
Preferably, the first channel further includes a fifth terminal and a sixth terminal, the fifth terminal is a power supply terminal, and the sixth terminal is a ground terminal.
Preferably, the second channel further includes a fifth terminal and a sixth terminal, the fifth terminal is a power supply terminal, and the sixth terminal is a ground terminal.
Compared with the prior art, the utility model discloses following beneficial effect has at least:
1. the utility model provides an operational amplifier is accurate rail-to-rail fortune put, adopts 2.2V to 5.5V low supply voltage's ADA4528, adapts to the low supply voltage environment, and the precision is high, small in noise.
2. The utility model discloses use first operational amplifier's voltage follower to keep apart between sampling resistor output and second resistance, the electric current flows from the sampling resistor output toward second operational amplifier output when preventing that current sampling resistor output voltage is higher than the second operational amplifier output, and the electric current flows from the second operational amplifier output toward current sampling resistor output and causes current measurement error when being higher than the sampling resistor output voltage with second operational amplifier output voltage, guarantees current measurement accuracy.
3. The utility model discloses a TMUX1136 binary channels precision analog switch switches the size of feedback resistance and realizes that the gain (the magnification) is variable is put to the fortune.
4. The utility model discloses use 16 bit analog-to-digital converter ADS1113 acquisition measurement data that the price is low, the precision is high to a small amount of components and parts have realized the test of 5 mu A to 40mA wide range electric current.
Drawings
Fig. 1 is a schematic diagram of a current sampling circuit according to an embodiment of the present invention.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
In the following, several different embodiments are given according to different features of the invention. The specific elements and arrangements of the present invention are for simplicity and are not intended to limit the invention to these embodiments. For the sake of brevity, the present invention is provided in the context of repeated reference numerals and/or letters in the various examples, which do not necessarily represent a particular relationship between the various embodiments and/or structures described.
Fig. 1 is a schematic diagram of a current measurement circuit in an embodiment of the present application, the circuit includes a sampling resistor Rsense, first to sixth resistors R1 to R6, first to third operational amplifiers OPA1 to OPA3, a filter, an analog-to-digital converter ADC1, and a dual-channel analog switch MUX1, where the dual-channel analog switch MUX1 includes a first channel MUX1_ channel 1 and a second channel MUX1_ channel 2.
One end of the sampling resistor Rsense is connected with an input POWER supply POWER _ IN and one end of the first resistor R1, the other end of the sampling resistor Rsense is connected with a chip under test DUT1 and the positive input end of the first operational amplifier OPA1, the negative input end of the first operational amplifier OPA1 is connected with the output end thereof and one end of the second resistor R2, the other end of the second resistor R2 is connected with the negative input end of the second operational amplifier OPA2 and the first end D1 of the second channel MUX1_ chanel2, the other end of the first resistor R1 is connected with the positive input end of the second operational amplifier OPA2 and the first end D2 of the first channel MUX1_ chanel1, the output end of the second operational amplifier OPA2 is connected with the positive input end of the third operational amplifier OPA3, one end of the fifth resistor R5 and one end of the sixth resistor R6, the negative input end of the third operational amplifier OPA3 is connected with the negative input end of the operational amplifier OPA3, the filter is connected to the digital-to-analog converter ADC 1. In one embodiment, the filter includes a seventh resistor R7 and a capacitor C1, one end of the seventh resistor R7 is connected to the output terminal of the third operational amplifier OPA3, the other end of the seventh resistor R7 is connected to the analog-to-digital converter ADC1 and the capacitor C1, and the other end of the capacitor C1 is connected to the ground GND. In one embodiment, the seventh resistor R7 has a value ranging from 1K Ω to 5K Ω, preferably 1K Ω, and the capacitor C1 has a value ranging from 1 μ F to 10 μ F, preferably 1 μ F.
One end of the third resistor R3 is connected to the third terminal S1B of the first channel MUX1_ chanel1, and the other end is connected to the ground GND. One end of the fourth resistor R4 is connected to the second end S1A of the first channel MUX1_ chanel1, and the other end is connected to the ground GND.
The other end of the fifth resistor R5 is connected to the third end S2B of the second channel MUX1_ chanel2, and the other end of the sixth resistor R6 is connected to the second end S2A of the second channel MUX1_ chanel 2.
The fourth terminal SEL1 of the first channel MUX1_ chanel1 is connected to a first selection signal for implementing GAIN control (GAIN CTRL), and the fourth terminal SEL2 of the second channel MUX1_ chanel1 is connected to a second selection signal for implementing GAIN control (GAIN CTRL).
In one embodiment, the first channel MUX1_ chanel1 further includes a fifth terminal and a sixth terminal, the fifth terminal is a power terminal VDD, and the sixth terminal is a ground terminal GND.
In one embodiment, the second channel MUX1_ chanel2 further includes a fifth terminal and a sixth terminal, the fifth terminal is a power terminal VDD, and the sixth terminal is a ground terminal GND.
In one embodiment, the resistance value of the sampling resistor Rsense ranges from 10 Ω to 100 Ω. Preferably, the value of the sampling resistor Rsense is 10 Ω.
In one embodiment, the first resistor R1 and the second resistor R2 have equal resistance values, and the resistance values range from 1K Ω to 5K Ω. Preferably, the first resistor R1 and the second resistor R2 are 1K Ω.
In one embodiment, the third resistor R3 and the fifth resistor R5 have equal resistance values, and the resistance values range from 10K Ω to 50K Ω. Preferably, the third resistor R3 and the fifth resistor R5 are 10K Ω.
In one embodiment, the fourth resistor R4 and the sixth resistor R6 have equal resistance values, and the resistance values range from 300K Ω to 500K Ω. Preferably, the fourth resistor R4 and the sixth resistor R6 are 300K Ω in resistance.
In the application, the feedback resistor can be switched by controlling the levels of SEL1 pins and SEL2 pins of the dual-channel analog switch MUX1, the amplification factor is selected, and the variable gain is realized.
The process of current sampling is illustrated in fig. 1. It is to be understood that the following description is intended to illustrate and not limit the application.
In this embodiment, the precision of the precision sampling resistor Rsense is 0.1%, the resistance value is 10 Ω, the precision of the precision resistors R1 and R2 is 0.1%, the resistance value is 1K Ω, the operational amplifiers OPA1, OPA2 and OPA3 are precision rail-to-rail operational amplifiers OPA1, OPA2 and OPA3, the precision of the precision resistors R3 and R5 is 0.1%, the resistance value is 10K Ω, the precision of the precision resistors R4 and R6 is 0.1%, the resistance value is 300K Ω, the resistance value of the precision resistor R7 is 1K Ω, and the capacitance value of the capacitor C1 is 1 μ F.
In one embodiment, the precision rail-to-rail operational amplifiers OPA1, OPA2, and OPA3 may be model ADA 4528. The precision analog switch MUX1 may be model number TMUX 1136. The analog-to-digital converter ADC1 may be model ADS 1113.
The input end of the sampling resistor Rsense is connected with a power supply, the output end of the sampling resistor Rsense is connected with a VDD pin of a tested chip DUT1, the resistor R1 is connected with the input end of the Rsense and used for collecting the voltage of the input end of the Rsense, and the other end of the sampling resistor Rsense is connected with the same-phase end of the precision operational amplifier OPA2 and a D1 pin of a channel MUX1_ chanel1 of the precision analog switch. By setting the SEL1 pin of MUX1_ chanel1 high, the selectable D1 pin is conductive with the S1A pin and grounded through resistor R4, and by setting the SEL1 pin of MUX1_ chanel1 low, the selectable D1 pin is conductive with the S1B pin and grounded through resistor R3. The in-phase end of the precision operational amplifier OPA1 is connected with the output end of the Rsense for collecting the voltage of the output end of the Rsense, the inverting end of the OPA1 is directly connected with the output end of the OPA1 to be used as a voltage follower, the output end of the OPA1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with the inverting end of the precision operational amplifier OPA2 and the D2 pin of the precision analog two-channel MUX1_ chanel2, the SEL2 pin of the MUX1_ chanel2 is set to be at a high level, the D2 pin can be selected to be conducted with the S2A pin and connected with the output end of the OPA2 through the resistor R6, the SEL2 pin of the MUX1_ chanel2 is set to be at a low level, the D2 pin can be selected to be conducted with the S2B pin, and the output end of the OPA2 through the resistor R5 is connected with the output end of the OPA2 to form a differential amplifier circuit with the selectable feedback resistor and used for amplifying the voltage difference between the two ends of the Rsense. The output end of the operational amplifier OPA2 is connected with the non-inverting input end of the precision operational amplifier OPA2, and the inverting input end of the OPA3 is in short circuit with the output end thereof and is used as a voltage follower.
The resistor R7 and the resistor C1 form an RC filter circuit, the output end of the OPA3 is connected with the input end of the analog-to-digital converter ADC1 through the RC filter circuit, and the measurement result is sampled by the ADC 1.
5V power is adopted for the operational amplifiers OPA1, OPA2 and OPA3, the dual-channel analog switch MUX1 and the analog-to-digital converter ADC 1. The analog-to-digital converter ADC1 has 16 bits, and has an internal reference voltage of 4.096V, a measurable range of-4.096V to +4.096V, and a resolution of (4.096V- (-4.096V))/(216) 125 μ V, Iload is the current consumed by the chip during normal operation or deep sleep.
The voltage at the input end of the sampling resistor Rsense is V1, the voltage at the output end of Rsense is V2, the voltage at the output end of the operational amplifier OPA2 is Vout1, the voltage at the output end of the operational amplifier OPA3 is Vout2, the operational amplifier OPA2 is used for amplifying the voltage difference between the two collected ends of Rsense, namely (V1-V2) is amplified, the amplified output result is Vout1, Vout1 is output as Vout2 after passing through the operational amplifier OPA3, and Vout2 is Vout 1.
If the current in milliampere (mA) level is measured, SEL1 and SEL2 are simultaneously set to be low level, and resistors R3 and R5 are selected as feedback resistors according to a differential operational amplifier formula
Vout1＝V1*(R3/(R1+R3))*((R5+R2)/R2)-V2*(R5/R2)
It can be seen that since the resistance values of the operational amplifiers R3 and R5 are equal to 10K, the formula can be simplified to
Vout1＝(V1-V2)*(R5/R2)，
At this time, the amplification factor is R5/R2-10/1-10, and the output result Vout 1-V1-V2-10.
If microampere (muA) level current is measured, SEL1 and SEL2 are simultaneously set to high level, and resistors R4 and R6 are selected as feedback resistors according to a differential operational amplifier formula
Vout1＝V1*(R4/(R1+R4))*((R6+R2)/R2)-V2*(R6/R2)
It can be seen that since the resistances of R4 and R6 are equal to 300K, the formula can be simplified to
Vout1＝(V1-V2)*(R6/R2)，
The amplification factor is R6/R2-300/1-300, and the output result Vout 1-V1-2-300.
Then, Vout1 is output as Vout2 after passing through the operational amplifier OPA3, and is output to the input terminal of the ADC1 after being filtered by the RC filter circuit.
Taking the lower limit of the measuring current range of 5 muA and the upper limit of 40mA as an example: according to ohm's law, the current Iload on the sampling resistor Rsense is equal to the voltage difference (V1-V2) between two ends of Rsense/Rsense resistance, and the magnitude of the Iload current value can be reversely deduced according to the Vout2 value sampled by the ADC 1. When the current on the sampling resistor Rsense is 10 μ a, the voltage difference across the sampling resistor Rsense (V1-V2) is 5 μ a × 10 Ω as 50 μ V, and the SEL1 and SEL2 are simultaneously amplified by 300 times at high level, so that Vout1 outputs 15 mV. If the current on the sampling resistor Rsense is 40mA, the voltage difference (V1-V2) between two ends of the sampling resistor Rsense is 40mA × 10 Ω ═ 400mV, the low level is simultaneously set by SEL1 and SEL2 to amplify by 10 times, Vout1 outputs 4V, and the two conditions are within the measurement range of the ADC1, and an appropriate amplification factor can be selected according to the size of the measured current.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A current measurement circuit comprising a sampling resistor, first to sixth resistors, first to third operational amplifiers, a filter, an analog-to-digital converter, and a dual-channel analog switch, the dual-channel analog switch comprising a first channel and a second channel, wherein:
one end of the sampling resistor is connected with an input power supply and one end of the first resistor, the other end of the sampling resistor is connected with a chip to be tested and the positive input end of the first operational amplifier, the negative input end of the first operational amplifier is connected with the output end of the first operational amplifier and one end of the second resistor, the other end of the second resistor is connected with the negative input end of the second operational amplifier and the first end of the second channel, the other end of the first resistor is connected with the positive input end of the second operational amplifier and the first end of the first channel, the output end of the second operational amplifier is connected with the positive input end of the third operational amplifier, the fifth resistor and the sixth resistor, the negative input end of the third operational amplifier is connected with the output end of the third operational amplifier and the filter, and the filter is connected with the digital-to-analog converter;
the third resistor is connected with a third end of the first channel, and the fourth resistor is connected with a second end of the first channel;
the fifth resistor is connected with the third end of the second channel, and the sixth resistor is connected with the second end of the second channel;
and the fourth end of the first channel is connected with a first selection signal, and the fourth end of the second channel is connected with a second selection signal.
2. The current measurement circuit of claim 1, wherein the sampling resistor has a resistance value in a range of 10 Ω to 100 Ω.
3. The current measurement circuit of claim 1, wherein the first resistor and the second resistor have equal resistance values, and the resistance values range from 1K Ω to 5K Ω.
4. The current measurement circuit of claim 1, wherein the third resistor and the fifth resistor have equal resistance values, and the resistance values range from 10K Ω to 50K Ω.
5. The current measurement circuit of claim 1, wherein the fourth resistor and the sixth resistor have equal resistance values, and the resistance values range from 300K Ω to 500K Ω.
6. The current measurement circuit according to claim 1, wherein the filter includes a seventh resistor and a capacitor, one end of the seventh resistor is connected to the output end of the third operational amplifier, the other end of the seventh resistor is connected to the analog-to-digital converter and the capacitor, the other end of the capacitor is connected to ground, the seventh resistor has a value ranging from 1K Ω to 5K Ω, and the capacitor has a value ranging from 1 μ F to 10 μ F.
7. The current measurement circuit of claim 1, wherein the first channel further comprises a fifth terminal and a sixth terminal, the fifth terminal being a power terminal and the sixth terminal being a ground terminal.
8. The current measurement circuit of claim 1, wherein the second channel further comprises a fifth terminal and a sixth terminal, the fifth terminal being a power terminal and the sixth terminal being a ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022676012.XU CN213934003U (en) | 2020-11-18 | 2020-11-18 | Current measuring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022676012.XU CN213934003U (en) | 2020-11-18 | 2020-11-18 | Current measuring circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213934003U true CN213934003U (en) | 2021-08-10 |
Family
ID=77170788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022676012.XU Active CN213934003U (en) | 2020-11-18 | 2020-11-18 | Current measuring circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213934003U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114487582A (en) * | 2022-01-30 | 2022-05-13 | 北京思凌科半导体技术有限公司 | Current detection device and current detection system |
-
2020
- 2020-11-18 CN CN202022676012.XU patent/CN213934003U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114487582A (en) * | 2022-01-30 | 2022-05-13 | 北京思凌科半导体技术有限公司 | Current detection device and current detection system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8845870B2 (en) | Digital potentiostat circuit and system | |
| CN103560760B (en) | Amplifying circuit and measuring device | |
| US7423480B2 (en) | AC amplifier for precision measurement | |
| CN213934003U (en) | Current measuring circuit | |
| GB2451314A (en) | An input amplifier for a digital multimeter | |
| CN212875747U (en) | Adjustable amplifying circuit of each sensitivity range of pressure sensor | |
| CN114460875B (en) | Power supply circuit and camera testing device | |
| CN111175559A (en) | Multi-stage current measurement architecture | |
| CN115453609A (en) | Pt 100-based high-purity germanium detector protection system | |
| CN207515923U (en) | A kind of programmable high precision temperature compensation system | |
| CN205302071U (en) | Adjustable accurate reference voltage's output circuit | |
| CN113155159B (en) | Bridge detector | |
| CN210626547U (en) | Measuring device | |
| CN111190047B (en) | Current acquisition diagnosis circuit and failure diagnosis method thereof | |
| CN203642941U (en) | Multipath sensing single-channel constant current measuring device | |
| CN113108814A (en) | Multi-channel resistance circuit and device | |
| CN113219316A (en) | Triode amplification factor test circuit based on negative feedback | |
| CN112187050A (en) | Precise low-cost programmable power supply module for test equipment | |
| CN109343645B (en) | Program-controlled power signal source output voltage multiplication circuit | |
| CN113820029A (en) | PT100 temperature acquisition circuit for acquisition terminal | |
| CN216904829U (en) | T omega grade 100V instrument amplifier | |
| CN113341213B (en) | Portable friction nano generator sensor powered by single power supply | |
| Ma et al. | Differential difference amplifier based parametric measurement unit with digital calibration | |
| CN213585713U (en) | Operational amplifier | |
| CN220625545U (en) | Temperature sampling circuit, temperature sampling device and processing equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |