CN213906347U

CN213906347U - Shutdown charging circuit of battery products

Info

Publication number: CN213906347U
Application number: CN202022764661.5U
Authority: CN
Inventors: 潘红章; 魏志勇
Original assignee: Shenzhen Bolian Communication Technology Co ltd
Current assignee: Shenzhen Bolian Communication Technology Co ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-08-06
Anticipated expiration: 2030-11-26

Abstract

The utility model discloses a shutdown charging circuit of battery class product. The USB power supply protection circuit comprises a USB power supply signal access circuit, an OVP protection circuit, a USB line insertion detection circuit and a USB insertion starting circuit, wherein the USB power supply signal access circuit is used for oppositely inserting a USB charging line and is connected with the OVP protection circuit, the USB line insertion detection circuit is connected with the OVP protection circuit and outputs a power supply and a feedback insertion signal, and the USB insertion starting circuit is connected with the OVP protection circuit and outputs a PWRON signal for controlling starting. The utility model discloses by USB power signal access circuit butt joint charging wire, utilize OVP protection circuit protection rear end circuit not to receive the voltage fluctuation damage, utilize the USB circuit to insert detection circuitry and detect whether insert and export the charging source who corresponds, simultaneously, utilize USB to insert the power circuit and let the product under the shutdown state, after inserting the charging wire, give the start instruction, realize the automatic start of product.

Description

Shutdown charging circuit of battery products

Technical Field

The utility model belongs to the technical field of the electronic circuit technique and specifically relates to a shutdown charging circuit of battery class product.

Background

Along with the continuous development of science and technology, various electronic products appear in people's daily life, wherein for convenient use, can select inside collection dress battery to avoid the use of power cord under the user state, avoid the power cord to bring the hindrance to the product use. It should be noted that the battery can be used conveniently to a great extent, but the internal battery needs to be ensured to have sufficient electric energy.

At present, when a battery is charged, the battery is charged in time mostly when a product is in short power failure, and the power failure shutdown of the product is avoided. However, in the process of daily use, the charging is often too late to be done, so that the product is shut down. Although the existing charging circuit can charge the product after shutdown, most of the charging circuits still need to be operated by users if the product is started, and the overall structure of the circuit is complex and is not beneficial to application on the product.

Disclosure of Invention

To the not enough of existence among the above-mentioned prior art, the utility model aims to provide a shutdown charging circuit of battery class product.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a shutdown charging circuit of a battery product comprises a USB power signal access circuit, an OVP protection circuit, a USB line insertion detection circuit and a USB insertion startup circuit, wherein the USB power signal access circuit is used for plugging a USB charging line in a plug-in mode and is connected with the OVP protection circuit;

the USB plug-in starting circuit comprises a RESET chip, a first triode and a second triode, wherein a VCC (voltage holding) terminal pin of the RESET chip is grounded through a first capacitor and connected with an output end of an OVP (over voltage protection) protection circuit, an STR terminal pin of the RESET chip is grounded through a second capacitor, a RESET # terminal pin of the RESET chip is connected with a base electrode of the first triode through a first resistor, a base electrode of the first triode is grounded through a second resistor, a collector electrode of the first triode and a base electrode of the second triode are both connected with an output end of the OVP protection circuit through a third resistor, and a collector electrode of the second triode outputs PWRON signals.

Preferably, the reset chip is an SGM804 chip.

Preferably, USB power signal access circuit includes the USB socket, the end D + foot and the D-end foot of USB socket are respectively through first TVS pipe and second TVS pipe ground connection, the VCC end foot output power of USB socket and through third TVS pipe, fourth electric capacity and the fourth resistance and the third electric capacity ground connection that connect gradually.

Preferably, the OVP protection circuit includes an OVP chip, a VIN terminal pin of the OVP chip is connected to a power output terminal of the USB power signal access circuit and grounded through a fifth capacitor, and a VOUT terminal pin of the OVP chip outputs a power supply and is grounded through a sixth capacitor.

Preferably, the USB line insertion detection circuit includes a third triode, a base of the third triode is grounded through a sixth resistor and is connected to the power supply output by the OVP protection circuit through a seventh resistor, and a collector of the third triode is connected to the main control of the product and outputs the power supply for charging the product through an eighth resistor.

Since the technical scheme is used, the utility model discloses by USB power signal access circuit butt joint charging wire, utilize OVP protection circuit protection rear end circuit not to receive the voltage fluctuation damage, utilize the USB circuit to insert detection circuitry and detect whether insert and export the charging source who corresponds of charging wire, simultaneously, utilize USB to insert the power circuit and let the product under the shutdown state, after inserting the charging wire, give the start instruction, realize the automatic start of product.

Drawings

Fig. 1 is a schematic diagram of the structural principle of the embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a USB power signal access circuit according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an OVP protection circuit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of the OVP protection circuit according to the embodiment of the present invention, wherein the voltage input at VBUS exceeds OVP trip level.

Fig. 5 is a schematic structural diagram of a USB line insertion detection circuit according to an embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a USB plug-in power-on circuit according to an embodiment of the present invention.

Detailed Description

The embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways as defined and covered by the claims.

As shown in fig. 1 to fig. 6, the shutdown charging circuit for battery products provided in this embodiment includes a USB power signal access circuit 1, an OVP protection circuit 2, a USB line insertion detection circuit 3, and a USB insertion startup circuit 4, where the USB power signal access circuit 1 is used to plug a USB charging line and is connected to the OVP protection circuit 2, the USB line insertion detection circuit 3 is connected to the OVP protection circuit 2 and outputs a power supply and a feedback insertion signal, and the USB insertion startup circuit 4 is connected to the OVP protection circuit 2 and outputs a PWRON signal for controlling startup.

Further, the USB power signal access circuit 1 of the present embodiment may adopt a circuit structure as shown in fig. 2, that is, the USB power signal access circuit includes a USB socket U1, a terminal D + pin and a terminal D-pin of the USB socket U1 are grounded through a first TVS transistor D1 and a second TVS transistor D2, respectively, a VCC terminal pin of the USB socket U1 outputs power and is grounded through a third TVS transistor D3, a fourth capacitor C4, and a fourth resistor R4 and a third capacitor C3 which are connected in sequence. When the circuit works specifically, when a USB charging wire is plugged in from the USB socket U1, current flows into the OVP protection circuit 2 through the third TVS tube D3 and the fourth capacitor C4. The first TVS transistor D1 and the second TVS transistor D2 are for preventing ESD or overshoot voltage on the signal lines D-and D +, and the first TVS transistor D1 and the second TVS transistor D2 can effectively protect the rear chip from ESD or overshoot voltage. The fourth capacitor C4 is used to stabilize the power supply and provide a stable power supply for the back end.

Further, the OVP protection circuit 2 of this embodiment is shown in fig. 3, and includes an OVP chip U2, a VIN terminal pin of the OVP chip U2 is connected to the power output terminal of the USB power signal access circuit 1 and is grounded through a fifth capacitor C5, and a VOUT terminal pin of the OVP chip U2 outputs power and is grounded through a sixth capacitor C6. The circuit mainly comprises an OVP chip U2 with model AW33901 and two capacitors. When power supply flows into the OVP protection circuit 2 from the USB power signal access circuit 1, when the voltage input at VBUS in the circuit exceeds OVP trip level (as shown in FIG. 4), the output of the OVP chip U2 is cut off, the output voltage of VBUS _5V is reduced to 0V until the input voltage returns to a normal input value, when the input voltage is below the OVP trip level, the output of the OVP chip U2 is opened, and the VBUS _5V voltage is normally output for the normal work of a rear-end circuit. This protects the back-end circuitry from voltage fluctuations.

Further, the USB line insertion detection circuit 3 of the present embodiment is as shown in fig. 5, that is, includes a third transistor Q3, a base of the third transistor Q3 is grounded through a sixth resistor R6 and is connected to the power supply output by the OVP protection circuit 2 through a seventh resistor R7, and a collector of the third transistor Q3 is connected to the product main control and outputs the power supply for charging the product through an eighth resistor R8. The circuit is mainly composed of a third transistor Q3, when the USB charging wire is plugged in, if there is no problem in front end detection, VBUS _5V will generate a voltage of about 2.5V at the base of the third transistor Q3, then there is a voltage drop between the base and emitter of the third transistor Q3, the collector and emitter of the third transistor Q3 will be turned on, and the network charge _ DCIN will be pulled low. When no USB charging wire is inserted, VBUS _5V is no voltage, there is no voltage drop between the base and emitter of the third transistor Q3, and there is no conduction between the collector and emitter of the third transistor Q3, so the charge _ DCIN network is pulled high, and the charge _ DCIN network is connected to the master control (referring to the master control unit on the product internal motherboard), and the master control can detect the level of the charge _ DCIN until no USB wire is inserted, so as to perform corresponding actions.

Further, the USB plug-in power-on circuit 4 of this embodiment is as shown in fig. 6, that is, includes a RESET chip U3, a first triode Q1 and a second triode Q2, the RESET chip U3 is an SGM804 chip, a VCC terminal pin of the RESET chip U3 is grounded through a first capacitor C1 and connected to the output terminal of the OVP protection circuit 2, an STR terminal pin of the RESET chip U3 is grounded through a second capacitor C2, a RESET # terminal pin of the RESET chip U3 is connected to the base of the first triode Q1 through a first resistor R1, the base of the first triode Q1 is grounded through a second resistor R2, the collector of the first triode Q1 and the base of the second triode Q2 are both connected to the output terminal of the OVP protection circuit 2 through a third resistor R3, and the collector of the second triode Q2 outputs a PWRON signal. The circuit is mainly formed by a RESET chip U3 and two triodes, the working principle is that when VBUS _5V has input, namely when a USB charging wire is inserted, after the voltage of a VCC pin of the RESET chip U3 is input, a high-level signal can be correspondingly generated at a RESET # terminal pin, but the output of the high-level signal and the input of VCC can generate a time difference, and the power-on of the circuit is realized by utilizing the time difference. The specific realization principle is as follows:

when the RESET # of the RESET chip U3 outputs a high level signal, a voltage drop is generated between the base and the emitter of the first transistor Q1, which causes the first transistor Q1 to be in a saturation state, the collector and the emitter of the first transistor Q1 are turned on, which is equivalent to the collector of the first transistor Q1, the base of the second transistor Q2 is grounded, the second transistor Q2 is in an off state, the level of the PWRON signal is determined by the main control terminal, which is originally high, and is kept high, and the pwn is turned on only when the low level pulse is applied, so that if the RESET # outputs a high level, the PWRON side is not low, and the power cannot be turned on.

When the RESET # terminal of the RESET chip U3 outputs a low level signal, the base of the first transistor Q1 is also low, so the first transistor Q1 is not turned on, and is in an off state, so the collector of the first transistor Q1 is pulled up to 5V by the third resistor R3, which means that the base of the second transistor Q2 is also pulled up to 5V, so a voltage drop occurs between the base and the emitter of the second transistor Q2, which causes the second transistor Q2 to be in a saturation state, so the collector and the emitter of the second transistor Q2 are turned on, and the collector is pulled down, which pulls down PWRON, and the turn-on signal is triggered by controlling the pull-down time.

The time is completely realized by a RESET # signal, and a time difference between the VCC input voltage at the pin and the output voltage at the RESET # pin can be realized by adjusting the second capacitor C2, so that the time of PWRON low level is realized, and the starting action is triggered.

The above is only the preferred embodiment of the present invention, and not the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or the direct or indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A shutdown charging circuit of battery class product which characterized in that: the USB power supply circuit is used for oppositely plugging a USB charging wire and is connected with the OVP protection circuit, the USB line insertion detection circuit is connected with the OVP protection circuit and outputs a power supply and a feedback insertion signal, and the USB insertion startup circuit is connected with the OVP protection circuit and outputs a PWRON signal for controlling startup;

2. The shutdown charging circuit of a battery-type product according to claim 1, wherein: the reset chip is an SGM804 chip.

3. The shutdown charging circuit of a battery-type product according to claim 1, wherein: USB power signal inserts the circuit and includes the USB socket, the end D + foot and the D-end foot of USB socket are respectively through first TVS pipe and second TVS pipe ground connection, the VCC end foot output power of USB socket and through third TVS pipe, fourth electric capacity and the fourth resistance and the third electric capacity ground connection that connect gradually.

4. The shutdown charging circuit of a battery-type product according to claim 1, wherein: the OVP protection circuit comprises an OVP chip, a VIN terminal pin of the OVP chip is connected with a power output end of the USB power signal access circuit and is grounded through a fifth capacitor, and a VOUT terminal pin of the OVP chip outputs power and is grounded through a sixth capacitor.

5. The shutdown charging circuit of a battery-type product according to claim 1, wherein: the USB line insertion detection circuit comprises a third triode, the base of the third triode is grounded through a sixth resistor and is connected with a power supply output by the OVP protection circuit through a seventh resistor, and the collector of the third triode is connected with the main control of a product and outputs the power supply for charging the product through an eighth resistor.