CN213877409U - Display module assembly and display box - Google Patents

Abstract

The embodiment of the utility model discloses display module assembly and display box body. The display module, for example, includes: the display control chip is provided with a first differential signal pin group and a second differential signal pin group; the display driving circuit is provided with a third differential signal pin group and a driving current output pin group; the display unit array is electrically connected with the driving current output pin group; the display control chip receives the first LVDS data packet through the first differential signal pin group, analyzes and processes the first LVDS data packet to obtain image data and control information, repacks the image data and the control information to obtain a second LVDS data packet, outputs the second LVDS data packet to the display driving circuit through the second differential signal pin group, and the display driving circuit analyzes the second LVDS data packet to generate driving current and outputs the driving current to the display unit array for driving display. The utility model discloses can reduce the communication line of display module assembly and preceding stage equipment, reduce the design complexity of display module assembly, improve the transmission stability of signal.

Description

Display module assembly and display box

Technical Field

The utility model relates to a show technical field, especially relate to a display module assembly and a display box body.

Background

With the market demand updating and the technical progress, the LED display screen is always developed towards a smaller distance, the continuous innovation of the whole industry chain is brought, and higher requirements are provided for the performance, the volume, the power consumption, the usability and the like of the LED display screen control system.

At present, LED display screen control system mainly comprises video source, transmission card, receiving card and LED display screen, and an LED display screen generally forms by the concatenation of a plurality of LED boxes, and single LED box contains a plurality of cascaded LED modules, and LED display screen control system's general working process as follows: the FPGA in the receiving card receives the image data packet from the sending card through the network port, performs image analysis processing to generate an LED driving signal, and transmits the LED driving signal to the LED module through a multi-core flat cable, wherein the receiving card and the LED module both comprise multi-pin interfaces required by flat cable connection, TTL signals are transmitted on the flat cable, and cascaded LED modules are also interconnected through the multi-core flat cable.

However, the conventional multi-core flat cable connection method has various disadvantages, for example, the number of signals transmitted between the receiving card and the LED module is large, including RGB data signals, CLK clock control signals, LAT latch control signals, OE enable signals and other control signals, which results in too many communication lines between the receiving card and the LED module, resulting in complicated connection lines inside the LED module, and abnormal display of the LED display screen due to a problem of a single communication line; for another example, a single bus can provide only 30Mbps of data bandwidth, so the frequency of the CLK clock control signal is not more than 30Mhz, and if the data bandwidth is increased, more buses are required, so the bandwidth is a bottleneck in the design of the large-resolution LED module; for another example, because the related multi-pin interface is not a standard interface, the requirement is provided for the number of wire cores of the multi-core flat cable of an LED module manufacturer, and the standardized design of the LED module is not facilitated; for another example, the transmission distance of the TTL signal is limited, and when the transmission distance is long, the anti-interference capability of the circuit of the TTL signal is poor, and electromagnetic interference (EMI) is easily generated, which makes it difficult for the LED display to pass EMC tests.

SUMMERY OF THE UTILITY MODEL

Therefore, for solving the not enough of current correlation technique, the embodiment of the utility model discloses a display module assembly and a display box body.

In order to achieve the above object, an embodiment of the utility model discloses a display module assembly, include: a first printed circuit board; a second printed circuit board; display control chip is provided with: a first differential signal pin group and a second differential signal pin group; a display drive circuit provided with: the driving circuit comprises a third differential signal pin group and a driving current output pin group, wherein the third differential signal pin group is electrically connected with the second differential signal pin group; the display unit array is electrically connected with the driving current output pin group; the display control chip is arranged on the first printed circuit board, the display driving circuit is arranged on the second printed circuit board, the display control chip is used for receiving a first LVDS data packet through the first differential signal pin group, analyzing and processing the first LVDS data packet to obtain image data and control information, and packaging the image data and the control information to obtain a second LVDS data packet which is output to the display driving circuit through the second differential signal pin group, and the display driving circuit is used for analyzing the second LVDS data packet to generate driving current and outputting the driving current to the display unit array through the driving current output pin group to drive and display.

The display module disclosed by the embodiment of the utility model is provided with a display control chip, the display control chip is provided with a first differential signal pin group and a second differential signal pin group, the second differential signal pin group is connected with a third differential signal pin group of a display driving circuit, the display control chip is used for receiving a first LVDS data packet through the first differential signal pin group, analyzing and processing the first LVDS data packet to obtain image data and control information, and packaging the image data and the control information to obtain a second LVDS data packet which is output to the display driving circuit through the second differential signal pin group, the internal structure of the display module can be simplified and reduced, the connection relation between the display control chip and the display driving circuit in the display module is simplified, the communication circuit of the display module and a preceding stage device can be reduced, and the abnormal display condition of a display screen is reduced, the standard differential signal pins can be used for realizing that the display module directly samples and transmits signals with specific frequency according to transmission bandwidth after receiving a first LVDS data packet output by preceding-stage equipment, complicated sampling and oversampling processes are not needed, the standardized design of the display module is easy, the compatibility is good, the expansibility is strong, the design complexity of the display module is reduced, the data transmission bandwidth is greatly improved, the integrated design of the display module is facilitated, the transmission stability of input signals is improved, and the remote transmission is realized.

In an embodiment of the present invention, the display module further includes: the sensor circuit is connected with the display unit array and the display control chip and is used for monitoring the display unit array to obtain first monitoring information and outputting the first monitoring information to the display control chip; the display driving circuit is further configured to provide second monitoring information, and output the second monitoring information to the second differential signal pin group of the display control chip via the third differential signal pin group; and the display control chip is used for generating return information according to the first monitoring information and the second monitoring information and outputting the return information through the first differential signal pin group.

Through set up the sensor circuit in the display module assembly, the first monitoring information of sensor circuit output is to the display control chip, the display drive circuit can also provide the second monitoring information and export the second difference signal pin group to the display control chip via the third difference signal pin group, the display control chip produces passback information and exports via first difference signal pin group based on first monitoring information and second monitoring information, further reduce the communication line with preceding stage equipment, reduce the design complexity of display module assembly, improve output signal's transmission stability.

In an embodiment of the present invention, the first differential signal pin group includes: at least one pair of first differential data signal pins is used as a signal input pin, or the at least one pair of first differential data signal pins and one pair of first differential clock signal pins are used as the signal input pin.

Through set up at least a pair of first differential data signal pin in first differential signal pin group, perhaps at least a pair of first differential data signal pin and a pair of first differential clock signal pin are as signal input pin, can realize freely setting up the logarithm of differential data signal input pin based on data transmission bandwidth, greatly improve the transmission bandwidth of input data, be favorable to the equipment that integrates of display module assembly, in addition still reduced the communication line between display module assembly and the preceding stage equipment, realize the stable transmission of signal, reduce the unusual risk of display screen display, can realize long-distance transmission.

In an embodiment of the present invention, the first differential signal pin group includes: at least one pair of first differential data signal pins are used as signal input pins, or the at least one pair of first differential data signal pins and one pair of first differential clock signal pins are used as the signal input pins; and at least one pair of second differential data signal pins as signal output pins, or the at least one pair of second differential data signal output pins and the pair of second differential clock signal output pins as the signal output pins.

Through set up at least a pair of second difference data signal pin in first difference signal pin group, perhaps set up at least a pair of second difference data signal pin and a pair of second difference clock signal pin and regard as signal output pin, can realize freely setting up the logarithm of second difference data signal pin based on data transmission bandwidth, greatly improve the transmission bandwidth of output data, be favorable to the equipment of integrating of display module assembly, in addition can also reduce and preceding stage equipment between the communication line, realize the steady transmission of signal, reduce the unusual risk of display screen display, can realize long-distance transmission.

In an embodiment of the present invention, the display driving circuit further includes: a fourth differential signal pin group; the display module assembly includes: the display driving circuits are cascaded, the display driving circuit of the first stage and the display driving circuit of the last stage are both connected to the second differential signal pin group, and the fourth differential signal pin group of one display driving circuit in two adjacent display driving circuits is connected to the third differential signal pin group of the other display driving circuit.

The fourth differential signal pin group is arranged in the display driving circuit, and the display driving circuits are cascaded through the respective differential signal pin groups, so that the cascade connection of the display driving circuits is realized, and the internal structure and the connection relation of the display module are simplified.

In an embodiment of the present invention, the display driving circuit further includes: a fourth differential signal pin group; the display module assembly includes: a plurality of display driving circuit groups connected in parallel to the second differential signal pin group; wherein each of the display driving circuit groups includes a plurality of the display driving circuits connected in series, and the fourth differential signal pin group of one of the display driving circuits in two adjacent display driving circuits is connected to the third differential signal pin group of the other display driving circuit.

Through set up fourth differential signal pin group in the display drive circuit to a plurality of display drive circuit group parallel connection to second differential signal pin group, realized the parallel connection of a plurality of display drive circuit groups, increased the display drive circuit's that the display control chip can connect quantity, simplified the inner structure and the line relation of display module assembly.

In an embodiment of the present invention, the first differential signal pin group transmits signals using an LVDS level protocol or a mini LVDS level protocol.

By arranging the first differential signal pin group to transmit signals by adopting an LVDS level protocol or a mini LVDS level protocol, interface standardization equipment of the display module is realized, and the compatibility and the expansibility of the display module are improved.

In an embodiment of the present invention, the display control chip includes: a memory; a processor connecting the memory and the first set of differential signal pins; the data analysis module is connected with the first differential signal pin group, the processor and the memory; the image processing module is connected with the data analysis module, the processor and the memory; the display driving module is connected with the image processing module, the second differential signal pin group, the processor and the memory; the monitoring processing module is connected with the second differential signal pin group and the first differential signal pin group; the data analysis module is used for receiving and analyzing the first LVDS data packet transmitted by the first differential signal pin group to obtain initial image data and the control information; the image processing module is used for receiving the initial image data and carrying out image processing on the initial image data to obtain the image data; the display driving module is used for receiving the image data, packaging the control information and the image data to obtain a second LVDS data packet, and outputting the second LVDS data packet to the display driving circuit through the second differential signal pin group; the monitoring processing module is used for generating the return information according to the first monitoring information and the second monitoring information and outputting the return information through the first differential signal pin group; the data analysis module is further used for receiving and analyzing the command data packet transmitted by the first differential signal pin to obtain command data and outputting the command data to the processor, so that the processor executes related command operation based on the command data.

Furthermore, the embodiment of the utility model provides a display box body is disclosed, include: a data forwarding card comprising: a target differential signal pin group; any one of the foregoing display modules, wherein the display module is directly connected to the target differential signal pin set through the first differential signal pin set.

In an embodiment of the present invention, the data forwarding card includes: the programmable logic device is used for receiving an input original data packet through the first data input interface, and performing format conversion on the original data packet to obtain a first LVDS data packet and outputting the first LVDS data packet through the target differential signal pin group; or the data forwarding card comprises: the LVDS chip comprises the target differential signal pin set, and is used for receiving the input first LVDS data packet through the second data input interface and forwarding the input first LVDS data packet to be output through the target differential signal pin set.

The technical scheme can have the following advantages or beneficial effects: the display control chip is provided with a first differential signal pin group and a second differential signal pin group, the second differential signal pin group is connected with a third differential signal pin group of the display driving circuit, the display control chip is used for receiving the first LVDS data packet through the first differential signal pin group, analyzing and processing the first LVDS data packet to obtain image data and control information, and packaging the image data and the control information to obtain a second LVDS data packet which is output to the display driving circuit through the second differential signal pin group, the internal structure of the display module can be simplified, the connection relation between the display control chip and the display driving circuit in the display module is simplified, the communication lines between the display module and preceding-stage equipment are reduced, the abnormal display condition of the display screen is reduced, and the display module can receive the first LVDS data packet output by the preceding-stage equipment by adopting standard differential signal pins only according to the transmission bandwidth The method has the advantages that the specific frequency is used for directly sampling and transmitting signals, complex sampling and oversampling processes are not needed, the standardized design of the display module is easy, the compatibility is good, the expansibility is strong, the design complexity of the display module is reduced, the data transmission bandwidth is greatly improved, the integrated design of the display module is facilitated, the transmission stability of the signals is improved, and the long-distance transmission is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display module according to an embodiment of the present invention.

Fig. 2 is another schematic structural diagram of a display module according to an embodiment of the present invention.

Fig. 3a is a schematic diagram of a first differential signal pin set of the display control chip in the display module shown in fig. 1.

Fig. 3b is a schematic diagram of another pin of the first differential signal pin set of the display control chip in the display module shown in fig. 1.

Fig. 4a is a schematic diagram of another pin of the first differential signal pin of the display control chip in the display module shown in fig. 2.

Fig. 4b is a schematic diagram of another pin of the first differential signal pin of the display control chip in the display module shown in fig. 2.

Fig. 5 is a schematic structural diagram of a display control chip in the display module shown in fig. 2.

Fig. 6a is another schematic structural diagram of a display box disclosed in an embodiment of the present invention.

Fig. 6b is a schematic diagram of an embodiment of the display box shown in fig. 6 a.

Fig. 7a is a schematic structural diagram of a display box according to an embodiment of the present invention.

Fig. 7b is a schematic diagram of an embodiment of the display box shown in fig. 7 a.

Fig. 8 is a schematic structural diagram of a display box according to an embodiment of the present invention.

Fig. 9 is another schematic structural diagram of a display box disclosed in an embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a display box according to an embodiment of the present invention.

Fig. 11 is a schematic structural diagram of an LED box according to an embodiment of the present invention.

Fig. 12a is a schematic diagram of a connection between the data forwarding card and the LED module in the LED box shown in fig. 11.

Fig. 12b is another connection diagram of the data forwarding card and the LED module in the LED box shown in fig. 11.

Fig. 13 is a schematic structural diagram of an LED box according to another specific embodiment of the LED box disclosed in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention. It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the division of the embodiments in the present invention is only for convenience of description and should not be construed as a limitation, and features in various embodiments may be combined and referred to each other without contradiction.

Referring to fig. 1, one embodiment of the present invention discloses a display module. As shown in fig. 1, the display module 10 includes: a display control chip 11, a display driving circuit 12 and a display cell array 13.

The display control chip 11 is provided with, for example: a first differential signal pin group 111 and a second differential signal pin group 112. The display drive circuit 12 is provided with, for example: a third differential signal pin group 121 and a driving current output pin group 122, wherein the third differential signal pin group 121 is electrically connected to the second differential signal pin group 112. The display unit array 13 is electrically connected to the driving current output pin group 122. The display control chip 11 is configured to receive a first LVDS data packet through a first differential signaling pin group 111, analyze the first LVDS data packet to obtain image data and control information, and package the image data and the control information to obtain a second LVDS data packet, and output the second LVDS data packet to the display driving circuit 12 through a second differential signaling pin group 112, where the display driving circuit 12 is configured to analyze the second LVDS data packet to generate a driving current, and output the driving current to the display unit array 13 through a driving current output pin group 122 to drive and display the second LVDS data packet.

Specifically, the display module 10 is, for example, an LED module. The display control chip 11 is, for example, a programmable logic device chip or an ASIC (Application Specific Integrated circuit) chip, for example, the display control chip 11 is, for example, an ASIC chip. The first differential signal pin group 111 includes, for example, a plurality of pairs of differential signal pins, i.e., LVDS pins. The second differential signal pin group 112 includes, for example, a plurality of pairs of differential signal pins, i.e., LVDS pins. It is understood herein that each pair of LVDS pins mentioned may implement an input-output function of LVDS signals, and the LVDS pins mentioned are standard LVDS interfaces, for example, data transmission using a standard LVDS level protocol or a standard mini LVDS level protocol. The display driving circuit 12 includes, for example, a display driving chip, or a display driving chip and a scanning control chip. The display driver chips mentioned can be display driver chips integrated with column decoding, or column driver chips, for example, 74HC595 chips, SMT5026 chips. The scan control chip is a column decoding chip, for example, a column decoding chip such as a 3-8 decoder. The third differential signaling pin group 121 includes a plurality of differential signaling pins, i.e., LVDS pins, where the LVDS pins mentioned here are the same as the aforementioned LVDS pins, for example, implement the input and output functions of the LVDS signals, and are a standard LVDS interface that performs data transmission using a standard LVDS level protocol or a standard mini LVDS level protocol. The driving current output pin group 122 includes, for example, a plurality of driving current output pins. The display unit array 13 is, for example, an LED array including a plurality of LED light points. The first LVDS data packet mentioned includes, for example, initial image data such as RGB initial image data and control information. The control information mentioned includes, for example: configuration information of the display driving circuit 12, such as a current operation mode, a scan number, and the like of the display driving circuit 12. The mentioned second LVDS data packet includes, for example, image data, that is, data after image processing and control information, where it is understood that a data transmission protocol corresponding to the first LVDS data packet is a data transmission protocol between the display module and the front-end device, for example, a first data transmission protocol, after the display module receives the first LVDS data packet, the display module parses the first LVDS data packet based on the built-in first data transmission protocol, a data transmission protocol corresponding to the second LVDS data packet is a data transmission protocol between the display control chip and the display driving circuit, for example, a second data transmission protocol, and the display module packages the image data and the control information based on the second data transmission protocol to form a second LVDS data packet.

By arranging the display control chip 11 in the display module, the display control chip 11 is provided with a first differential signal pin group 111 and a second differential signal pin group 112, the second differential signal pin group 112 is connected with a third differential signal pin group 121 of the display driving circuit 12, the display control chip 11 is used for receiving the first LVDS data packet through the first differential signal pin group 111, analyzing the first LVDS data packet to obtain image data and control information, and packing the image data and the control information to obtain a second LVDS data packet which is output to the display driving circuit 12 through the second differential signal pin group 112, on one hand, the internal structure of the display module is simplified, the connection relationship between the display control chip and the display driving circuit in the display module is simplified, the communication lines between the display module and the preceding stage equipment are reduced, and the abnormal condition of display screen is reduced, the standard differential signal pins are adopted, so that the standardized design of the display module is easy, the compatibility is good, the expansibility is strong, the design complexity of the display module is reduced, the data transmission bandwidth is greatly improved, the integrated design of the display module is facilitated, the transmission stability of input signals is improved, and the long-distance transmission is realized; on the other hand, because the standard differential signal pin group is adopted to receive data, the sampling clock has no strict requirement, the display module only needs to directly sample the transmission signal with a specific frequency according to the transmission bandwidth after receiving the first LVDS data packet, and does not need complicated sampling and oversampling processes, thereby avoiding the condition that the clock and data phases have deviation, even the data is lost, and not limiting the transmission bandwidth of the display module and the preceding-stage equipment.

Further, the display module 10 further includes, for example, a first printed circuit board and a second printed circuit board, the display control chip 11 is disposed on the first printed circuit board, for example, and the display driving circuit 12 is disposed on the second printed circuit board, for example, where the first printed circuit board and the second printed circuit board are different printed circuit boards, that is, the display control chip 11 and the display driving circuit 12 are disposed on different printed circuit boards. By disposing the display control chip 11 and the display driving circuit 12 on different printed circuit boards, separate maintenance of the display control chip 11 and the display driving circuit 12 is facilitated.

In other embodiments of the present invention, the aforementioned first printed circuit board and the aforementioned second printed circuit board are, for example, the same printed circuit board, i.e., the display control chip 11 and the display driving circuit 12 are disposed on the same printed circuit board. By arranging the display control chip 11 and the display driving circuit 12 on the same printed circuit board, the manufacturing cost of the display module can be saved.

It is worth mentioning that the aforementioned first printed circuit board and second printed circuit board are, for example, PCB circuit boards.

In other embodiments of the present invention, as shown in fig. 2, the display module further includes: and the sensor circuit 14 is connected with the display unit array 13 and the display control chip 11 and is used for monitoring the display unit array 13 to obtain first monitoring information and outputting the first monitoring information to the display control chip 11. The display driving circuit 12 is also used to provide second monitoring information, for example, and output to the second differential signal pin group 112 of the display control chip 11 via the third differential signal pin group 121. The display control chip 11 is configured to generate backhaul information according to the first monitoring information and the second monitoring information, and output the backhaul information through the first differential signal pin group 111.

Specifically, the display control chip 11 includes, for example, a monitoring processing module 120, the monitoring processing module 120 is connected to the display driving circuit 12 via the second differential signal pin set 112, and is connected to the sensor circuit 14 via, for example, a serial bus, and is configured to generate the backhaul information according to the first monitoring information and the second monitoring information, and output the backhaul information via the first differential signal pin set 111. The sensor circuit 14 includes, for example, a temperature sensor, a humidity sensor, a smoke sensor, and/or a voltage sensor among other types of sensors. The monitoring processing module 120 may directly output the second monitoring information input by the display driving circuit 12 through the first differential signal pin group 111, and process the first monitoring information input by the sensor circuit 14 to output, that is, the mentioned feedback information includes, for example: the second monitoring information and the processed first monitoring information. The first monitoring information mentioned therein includes, for example, information of temperature value, humidity value, smoke concentration, and/or voltage value. The second monitoring information mentioned includes, for example: the information of the lamp point, such as dead point information, open circuit information, short circuit information, and on-state voltage value, and the second monitoring information is generated by the existing internal module of the display driving circuit 12. It should be understood that the monitoring processing module of the display control chip 11 processes the first monitoring information after receiving the first monitoring information, for example, format conversion is performed on the first monitoring information, that is, the first monitoring information is converted into an LVDS format for output, or the first monitoring information and the reference information are compared to obtain a comparison result, and then the comparison result is converted into an LVDS format for output. To take the open circuit detection as an example to briefly describe, the voltage sensor in the sensor circuit 14 will obtain the read-back voltage value of the display unit array 13 and output the read-back voltage value to the monitoring processing module 120 of the display control chip 11, the monitoring processing module 120 compares the read-back voltage value with the stored reference voltage value to obtain the detection result that the detection is passed or not passed, and then converts the detection result into the LVDS format to output, which is not limited by the present invention. It should be mentioned that, in other embodiments of the present invention, the display control chip 11 may only generate the return information output based on the second monitoring information output by the display driving circuit 12, or the display control chip 11 may only generate the return information output based on the first monitoring information input by the sensor circuit 14, or the display module 10 may not be provided with the sensor circuit 14.

Through setting up sensor circuit 14 in display module assembly 10, sensor circuit 14 outputs first monitoring information to display control chip 11, display drive circuit 12 can also provide second monitoring information and export second differential signal pin group 112 to display control chip 11 via third differential signal pin group 121, display control chip 11 produces return information and exports via first differential signal pin group 111 based on first control information and second monitoring information, further reduce the communication line with preceding stage equipment, reduce the design complexity of display module assembly, improve output signal's transmission stability.

In other embodiments of the present invention, the first differential signal pin group 111 includes, for example: at least one pair of first differential data signal pins serves as signal input pins, or at least one pair of first differential data signal pins and one pair of first differential clock signal pins serve as the signal input pins. Specifically, as shown in fig. 3a, the first differential signal pin group 111 includes, for example: a pair of first differential data signal pins 1111a and a pair of first differential data signal pins 1111 b. Alternatively, as shown in fig. 3b, the first differential signal pin group 111 includes, for example: a pair of first differential data signal pins 1111a, a pair of first differential data signal pins 1111b, and a pair of first differential clock signal pins 1112. Of course, the utility model discloses do not use this as the limit, the logarithm of first difference data signal pin can set up according to actual need. The aforementioned signal input pin may be understood as a pin that receives an input signal from the outside, such as a first LVDS packet or the like.

Through set up at least a pair of first differential data signal pin in first differential signal pin group 111, or at least a pair of first differential data signal pin and a pair of first differential clock signal pin, can realize freely setting up the logarithm of first differential data signal pin based on data transmission bandwidth, greatly improve the transmission bandwidth of input data, be favorable to the equipment of integrating of display module assembly, communication line between display module assembly and the preceding stage equipment has still been reduced in addition, realize the steady transmission of signal, reduce the unusual risk of display screen display, can realize long distance transmission, and reduce cost.

Further, the first differential signal pin group 112 further includes, for example: at least one pair of second differential data signal pins is used as a signal output pin, or at least one pair of second differential data signal pins and one pair of second differential clock signal pins are used as the signal output pin. Reference to a signal output pin is to be understood as a pin that outputs a signal to an external device, such as outputting return information. Specifically, as shown in fig. 4a, the first differential signal pin group 112 includes, for example: a pair of first differential data signal pins 1111a and a pair of second differential data signal pins 1113 a. Alternatively, as shown in fig. 4b, the first differential signal pin group 112 includes, for example: a pair of first differential data signal pins 1111a, a pair of first differential clock signal pins 1112, a pair of second differential data signal pins 1113a, a pair of second differential data signal pins 1113b, and a pair of second differential clock signal pins 1114. Of course, the utility model discloses do not use this as the limit, the logarithm of first difference data signal pin and second difference data signal pin can set up according to actual need.

Through set up at least a pair of second differential data signal pin in first differential signal pin group, or set up at least a pair of second differential data signal pin and a pair of second differential clock signal pin as signal output pin, can realize freely setting up the logarithm of second differential data signal pin based on data transmission bandwidth, greatly improve the transmission bandwidth of output data, be favorable to the equipment that integrates of display module assembly, in addition can also reduce and preceding stage equipment between the communication line, realize the steady transmission of signal, reduce the unusual risk of display screen display, can realize long distance transmission, and reduce cost.

In other embodiments of the present invention, the first differential signal pin group 111 transmits signals using, for example, an LVDS level protocol or a mini LVDS level protocol.

The LVDS level protocol and the mini LVDS level protocol are existing LVDS level protocols, and a detailed description of the LVDS level protocol and the mini LVDS level protocol is omitted here. It should be mentioned that, in order to avoid the disadvantage of using multi-core flat cable connection in the related art, another existing method for connecting a display module with a front-end device is to use an LVDS transmitter and an LVDS receiver to establish connection to implement data transmission, but the adopted method is not a standard LVDS level protocol or a mini LVDS level protocol, and the LVDS transmitter and the LVDS receiver must be used in pair, wherein the LVDS transmitter and the LVDS receiver need to implement parallel-to-serial and serial-to-parallel conversion of data through oversampling, which has a strict requirement on a sampling clock, if the sampling clock cannot meet the phase requirement of oversampling, a recovered clock and a data phase may deviate, even data may be lost, and if the oversampling requires that the sampling frequency is more than twice of a signal frequency, the transmission bandwidth between the display module and the front-end device may be limited; in this embodiment, the first differential signal pin group 111 is configured to perform data transmission by using an LVDS level protocol or a mini LVDS level protocol, so that the disadvantage of pairing the LVDS transmitter and the LVDS receiver is avoided, and as long as the data output by the front-end device uses the LVDS level protocol or the mini LVDS level protocol, the connection between the data and the first differential signal pin group of the display module of this embodiment can be established, so that the interface standardization design of the display module is implemented, and the compatibility and the expansibility of the display module are improved.

In another embodiment of the present invention, as shown in fig. 5, the display control chip 11 includes: a memory 115, a processor 116, a data parsing module 117, an image processing module 118, a display driving module 119, and a monitor processing module 120. The processor 116 is connected to the memory 115 and the first differential signal pin group 111. The data parsing module 117 is connected to the first differential signal pin group 111, the processor 116, and the memory 115. The image processing module 118 is connected to the data parsing module 117, the processor 116 and the memory 115. The display driving module 119 is connected to the image processing module 118, the second differential signal pin group 112, the processor 116, and the memory 115. The monitoring processing module 120 connects the second differential signal pin group 112 and the first differential signal pin group 111.

Wherein, the data analyzing module 117 is configured to receive and analyze the first LVDS data packet transmitted by the first differential signaling pin set 111 to obtain initial image data and the control information, the image processing module 118 is configured to receive the initial image data and perform image processing on the initial image data to obtain the image data, the display driving module 119 is configured to receive the image data and perform grouping on the control information and the image data to obtain the second LVDS data packet, the second LVDS data packet is output to the display driving circuit 12 via the second differential signaling pin set 112, so that the display driving circuit 12 generates a driving current based on the second LVDS data packet and outputs the driving current to the display unit array 13 via the driving current output pin set 122, and the monitor processing module 120 is configured to generate the backhaul information according to the first monitor information and the second monitor information, and outputs the backhaul information via the first differential signal pin set 111, wherein the data parsing module 117 is further configured to receive and parse the command data packet transmitted by the first differential signal pin set 111 to obtain command data, and output the command data to the processor 116, so that the processor 116 executes a related command operation based on the command data.

In particular, the memory 115 mentioned is for example a RAM memory. The mentioned processor 116 is for example an MCU, or an ARM processor, etc. The mentioned data parsing module 117 includes, for example, a dedicated chip or FPGA, etc., which supports therein a first data transmission protocol for data transmission with the front-end device, so that the received data can be parsed based on the first data transmission protocol. The image processing module 118 includes, for example, an image processing chip or FPGA or the like, which mainly performs image processing operations, for example, processing operations including correction processing, gray-scale separation, and data rearrangement on image data. The correction processing here is, for example, inverse Gamma (Gamma) correction, luminance correction, and/or other correction such as chromaticity correction; the gradation separation is, for example, an operation such as a Bit separation after the correction processing, that is, the gradation separation is typically a manner in which gradation data after the correction processing is subjected to a separation operation per Bit to convert the gradation data into a manner of realizing weights differently for different bits; the data rearrangement typically includes an operation of rearranging gray data positions of the data after gray separation according to a data format required by a column driving chip (e.g., a general-purpose driving chip or a PWM driving chip) of the display driving circuit and LED panel routing information, and performing a splicing combination. The display driving module 119 includes, for example, a dedicated chip or FPGA, which supports a second data transmission protocol for data transmission with the display driving circuit, and may package the image data and the control information based on the second data transmission protocol to generate a second LVDS data packet. The monitoring processing module 120 includes, for example, a dedicated chip or FPGA. It should be noted here that the data parsing module 117, the image processing module 118, the display driving module 119, and the monitoring processing module 120 include, for example, the same special chip or FPGA, that is, the same FPGA or special chip implements the corresponding functions of the data parsing module 117, the image processing module 118, the display driving module 119, and the monitoring processing module 120, and of course, the present invention is not limited thereto, and the data parsing module 117, the image processing module 118, the display driving module 119, and the monitoring processing module 120 may further include different devices and circuit structures.

The display control chip is internally provided with the memory, the processor, the data analysis module, the image processing module, the display driving module and the monitoring processing module, so that the display module receives a first LVDS data packet output by a preceding stage device, the first differential signal pin group only needs to directly sample a transmission signal with a specific frequency according to a transmission bandwidth, a complex sampling and over-sampling process is not needed, the condition that a clock phase and a data phase have deviation and even cause data loss is avoided, and the transmission bandwidth of the display module and the preceding stage device is not limited.

In another embodiment of the present invention, as shown in fig. 6a and 6b, the display driving circuit 12 further includes: and a fourth set of differential signal pins 123. The display module 10 includes: and a plurality of display driving circuits 12, wherein the plurality of display driving circuits 12 are cascaded, and the first stage display driving circuit 12 and the last stage display driving circuit 12 are both connected to the second differential signal pin group 112, wherein the fourth differential signal pin group 123 of one display driving circuit 12 in two adjacent display driving circuits 12 is connected to the third differential signal pin group 121 of the other display driving circuit 12. Fig. 6a and 6b illustrate four display driving circuits 12, but the present invention is not limited thereto. Specifically, as shown in fig. 6a and 6b, the four display driving circuits 12 shown in fig. 6a correspond to the four driving chips shown in fig. 6b, and four driving levels are cascade-connected to form a loop for transmitting LVDS signals, i.e. as shown in fig. 6a, the third differential signal pin group 121 of the first stage display driving circuit 12 is connected to the second differential signal pin group 112, the fourth differential signal pin group of the first stage display driving circuit 12 is connected to the third differential signal pin group 121 of the second stage display driving circuit 12, the fourth differential signal pin group 123 of the second stage display driving circuit 12 is connected to the third differential signal pin group 121 of the third stage display driving circuit 12, the fourth differential signal pin group 123 of the third stage display driving circuit 12 is connected to the third differential signal pin group 121 of the fourth stage display driving circuit 12, and the fourth differential signal pin group 123 of the fourth stage display driving circuit 12 is connected to the second differential signal pin group 112, thereby realizing the cascade connection.

The fourth differential signal pin group 123 is arranged in the display driving circuit 12, and the plurality of display driving circuits 12 are cascaded through the respective differential signal pin groups, so that the cascade connection of the plurality of display driving circuits is realized, and the internal structure and the connection relation of the display module are simplified.

In another embodiment of the present invention, as shown in fig. 7a and 7b, the display driving circuit 12 further includes: and a fourth set of differential signal pins 123. The display module 10 includes: and a plurality of display driving circuit groups connected in parallel to the second differential signal pin group 112, wherein each display driving circuit group includes, for example, a plurality of display driving circuits 12 connected in series, and the fourth differential signal pin group 123 of one display driving circuit 12 of two adjacent display driving circuits 12 is connected to the third differential signal pin group 121 of the other display driving circuit 12. Fig. 7a and 7b illustrate two display driving circuit groups, one display driving circuit group includes three display driving circuits 12, and the other display driving circuit group includes two display driving circuits 12, but the present invention is not limited thereto. Specifically, as shown in fig. 7a and 7b, the five display driving circuits 12 shown in fig. 7a correspond to the five driving chips shown in fig. 7b, and as shown in fig. 7b, three driving chips are connected in series to form a display driving circuit group, and two other driving chips are connected in series to form another display driving circuit group, wherein the first driving chip of the two display driving circuit groups is connected to the second LVDS pin group (second differential signaling pin group), that is, as shown in fig. 7a, the third differential signaling pin group 121 of the first display driving circuit 12 in the first display driving circuit group is connected to the second differential signaling pin group 112, the fourth differential signaling pin group 123 of the first display driving circuit 12 in the first display driving circuit group is connected to the third differential signaling pin group 121 of the second display driving circuit 12, and the fourth differential signaling pin group 123 of the second display driving circuit 12 is connected to the third differential signaling pin group 121 of the third display driving circuit 12 121, a carrier; and the third differential signal pin group 121 of the first display driving circuit 12 in the second display driving circuit group is connected to the second differential signal pin group 112, and the fourth differential signal pin group 123 of the first display driving circuit 12 is connected to the third differential signal pin group 121 of the second display driving circuit 12.

By arranging the fourth differential signal pin group 123 in the display driving circuit 12 and arranging the plurality of display driving circuit groups in parallel to the second differential signal pin group 112, parallel connection of the plurality of display driving circuit groups is realized, the number of display driving circuits which can be connected by the display control chip is increased, and the internal structure and the connection relationship of the display module are simplified.

Furthermore, as shown in fig. 8, an embodiment of the present invention discloses a display box 30, including: the data forwarding card 20 and the display module 10 disclosed in the foregoing embodiments, wherein the data forwarding card 20 includes, for example: the target differential signal pin group 211, the display module 10 is directly connected to the target differential signal pin group 211 of the data forwarding card 20 through the first differential signal pin group 111. It can be understood here that the data forwarding card 20 has a plurality of differential signal pin groups, wherein the differential signal pin group directly connected to the first differential signal pin group 111 of the display module 10 is a target differential signal pin group 211.

In other embodiments of the present invention, as shown in fig. 9, the data forwarding card 20 includes, for example: the device comprises a first data input interface 21 and a programmable logic device 22 connected to the first data input interface 21, wherein the programmable logic device 22 comprises a target differential signal pin group 211, and the programmable logic device 22 is configured to receive an input original data packet through the first data input interface 21, perform format conversion on the original data packet to obtain the first LVDS data packet, and output the first LVDS data packet through the target differential signal pin group 211.

The first data input interface 21 is an ethernet interface such as RJ45 interface, or a video source input interface such as HDMI interface, DVI interface, SDI interface, or the like. The Programmable logic device 22 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device. For example, the model number of the FPGA is 410TFFG900, for example. The original data packet mentioned may be understood as a data packet received by the data forwarding card 20, and the data forwarding card does not perform operations such as parsing and image processing on the original data packet.

Of course, the data forwarding card of the present invention is not limited to the foregoing structure, and when format conversion is not required, the programmable logic device may not be disposed in the data forwarding card. Specifically, as shown in fig. 10, the data forwarding card 20 includes, for example: the second data input interface 23 and the LVDS chip 24 connected to the second data input interface 23, the LVDS chip 24 includes a target differential signaling pin set 211, and the LVDS chip 24 is configured to receive the first LVDS data packet input through the second data input interface 23 and forward and output the first LVDS data packet through the target differential signaling pin set 211.

The second data input interface 23 is, for example, an LVDS interface, and the LVDS chip 24 is a conventional chip capable of implementing LVDS data input and output.

Wherein, when the first differential signal pin set 111 of the display module 10 includes: when at least one pair of first differential data signal pins corresponds to the target differential signal pin group 211, for example, it includes: and the at least one pair of third differential data signal pins are correspondingly connected with the at least one pair of first differential data signal pins. Or

When the first differential signal pin set 111 of the display module 10 includes: when the at least one pair of first differential data signal pins and the pair of first differential clock signal pins correspond to each other, the target differential signal pin group 211 includes: the at least one pair of third differential data signal pins and the pair of third differential clock signal pins are respectively and correspondingly connected with the at least one pair of first differential data signal pins and the pair of first differential clock signal pins. Or

When the first differential signal pin set 111 of the display module comprises: at least one pair of first differential data signal pins and at least one pair of second differential data signal pins, the corresponding target differential signal pin group 211 includes, for example: and the at least one pair of third differential data signal pins and the at least one pair of fourth differential data signal pins are correspondingly connected with the at least one pair of first differential data signal pins and the at least one pair of second differential data signal pins respectively.

In short, the pins provided by the target differential signal pin group 211 are correspondingly connected to the pins provided by the first differential signal pin group 111.

For better understanding of the present embodiment, the display module assembly 10 and the display box 30 disclosed in the previous embodiments of the present invention are illustrated in the following embodiments with reference to fig. 11 to 13. In the present embodiment, the display module 10 is, for example, an LED module, and the display housing 30 is, for example, an LED housing. The data forwarding card 20 is connected to the sending card through a network port, for example. The LED box body is formed by the LED modules and the data forwarding card, the data forwarding card in the LED box body can be connected with the plurality of LED modules, and the LED modules connected with the data forwarding card can be cascaded with other LED modules.

Fig. 11 illustrates an LED box including a data forwarding card, which may be understood as a simplified receiving card, and an LED module, which includes, for example, a display control chip, a plurality of driving chips (display driving circuits) connected to the display control chip, and an LED array (display unit array, not shown in fig. 11) connected to the plurality of driving chips, and is connected to a front-end device, that is, the data forwarding card. Fig. 11 is only for better understanding of the embodiment, and the present invention is not limited thereto.

The FPGA in the data forwarding card related to the embodiment only realizes conversion of a data protocol after receiving the original data packet, converts the original data packet into a first LVDS data packet, and then sends the first LVDS data packet to a first LVDS pin group, namely a first differential signal pin group, of a display control chip of the LED module through an LVDS pin of the FPGA, namely a target differential signal pin group.

The first LVDS pin set samples the transmission signal according to the LVDS transmission standard to obtain a first LVDS data packet and then transmits the first LVDS data packet to the data analysis module, the data analysis module converts the first LVDS data packet based on a first data transmission protocol for data transmission with the data forwarding card to obtain an original data packet, analyzes the original data packet to obtain original image data and control information, sends the original image data to the image processing module for image processing, and sending the control information to a memory for storage, processing the image data by the image processing module after correcting, position recombining and the like to obtain image data, outputting the image data to the display driving module, packaging the image data and the control information by the display driving module based on a second data transmission protocol for data transmission with the driving chip to obtain a second LVDS data packet, and outputting the second LVDS data packet to the driving chip through a second LVDS pin group, namely a second differential signal pin group. And after receiving the second LVDS data packet, the driving chip analyzes the second LVDS data packet based on a second data transmission protocol to obtain image data and control information, and then generates driving current based on the image data after finishing the content of work mode configuration and the like based on the control information and outputs the driving current to the LED array to control the LED lamp point.

In addition, the data transfer card still can issue the command data package to the LED module with the form of LVDS signal, and the data analysis module of LED module sends the treater after analyzing the command data package and obtaining command data, and the treater carries out corresponding operation according to command data, and for example command data is read the voltage value this moment, then the treater reads the voltage value from the memory and transmits the card of retransmitting to the data via first LVDS pin group, certainly the utility model discloses do not use this as the limit.

In addition, the LED module further has a monitoring function, for example, the LED module is provided with a sensor circuit (not shown in fig. 11), a monitoring processing module connecting the LED array and the display control chip, the sensor circuit monitors the monitoring processing module that the LED array outputs first monitoring information to the display control chip, and the driving chip outputs second monitoring information to the monitoring processing module, the monitoring processing module generates return information based on the first monitoring information and the second monitoring information and outputs the return information through the first LVDS pin group, and specific examples of the monitoring function may refer to the foregoing related descriptions, which are not repeated herein.

It is worth mentioning that what is transmitted between the data forwarding card and the LED module is that the first LVDS data packet includes original image data, and the first LVDS pin set in the LED module only needs to directly sample a transmission signal with a specific frequency according to a transmission bandwidth, and does not need a complicated sampling and oversampling process, thereby avoiding a situation that a clock and a data phase are deviated or even data is lost.

Further, as shown in fig. 12a, the data forwarding card and the LED module are connected through, for example, a pair of differential clock signal lines (for sending differential clock pairs in LVDS) and a plurality of pairs of differential data signal lines (for sending differential data pairs in LVDS), so that a better transmission bandwidth can be satisfied, and it is worth mentioning that, on the premise that the transmission bandwidth is sufficient, the data forwarding card and the LED module can also use only one pair of differential clock signal lines and one pair of differential data signal lines, that is, stable transmission of image data can be achieved through 4 signal lines. Furthermore, only one pair of differential data signal lines can be used, and clock signals are generated by the LED module, namely, stable data transmission is realized through 2 signal lines.

Further, as shown in fig. 12b, when the LVDS data is transmitted back between the data forwarding card and the LED module, for example, a pair of differential data signal lines (a differential data pair in the transmission LVDS) is used, that is, two signal lines are used to transmit back the transmitted information or the command response. At this time, the data forwarding card may use its local clock as a receiving clock, or may use a special encoding method as a protocol to analyze the returned information, but is not limited to these two methods. In order to facilitate the design of the data forwarding card, a pair of differential clock signal lines can be added to return LVDS data as a return clock for returning information, and meanwhile, in order to increase the transmission bandwidth, a plurality of pairs of differential data signal lines can be added.

In another exemplary embodiment of this embodiment, as shown in fig. 13, a data forwarding card may include a plurality of LVDS pin sets (target differential signal pin sets) respectively connected to different LED modules, and each LED module includes a display control chip supporting LVDS data transmission.

In summary, the display control chip of the present invention is disposed in the display module, the display control chip is provided with a first differential signaling pin set and a second differential signaling pin set, the second differential signaling pin set is connected to a third differential signaling pin set of the display driving circuit, the display control chip is used for receiving the first LVDS data packet via the first differential signaling pin set, analyzing the first LVDS data packet to obtain image data and control information, and packaging the image data and the control information to obtain a second LVDS data packet, which is output to the display driving circuit via the second differential signaling pin set, so as to simplify the internal structure of the display module, simplify the connection relationship between the display control chip and the display driving circuit in the display module, reduce the communication lines between the display module and the preceding stage device, and reduce the abnormal display condition of the display screen, the standard differential signal pin is adopted, strict requirements on a sampling clock do not exist, a display control chip only needs to directly sample a transmission signal by using a specific frequency according to a transmission bandwidth without complicated sampling and oversampling processes, the situations that clock and data phases are deviated and even data is lost are avoided, the standardized design of a display module is easy, the compatibility is good, the expansibility is strong, the design complexity of the display module is reduced, the data transmission bandwidth is greatly improved, the integrated equipment of the display module is facilitated, the transmission stability of the signal is improved, and long-distance transmission is realized.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system and apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (10)

1. A display module, comprising:

a first printed circuit board;

a second printed circuit board;

display control chip is provided with: a first differential signal pin group and a second differential signal pin group;

a display drive circuit provided with: the driving circuit comprises a third differential signal pin group and a driving current output pin group, wherein the third differential signal pin group is electrically connected with the second differential signal pin group;

the display unit array is electrically connected with the driving current output pin group;

the display control chip is arranged on the first printed circuit board, the display driving circuit is arranged on the second printed circuit board, the display control chip is used for receiving a first LVDS data packet through the first differential signal pin group, analyzing and processing the first LVDS data packet to obtain image data and control information, and packaging the image data and the control information to obtain a second LVDS data packet which is output to the display driving circuit through the second differential signal pin group, and the display driving circuit is used for analyzing the second LVDS data packet to generate driving current and outputting the driving current to the display unit array through the driving current output pin group to drive and display.

2. The display module assembly of claim 1, wherein the display module assembly further comprises: the sensor circuit is connected with the display unit array and the display control chip and is used for monitoring the display unit array to obtain first monitoring information and outputting the first monitoring information to the display control chip;

the display driving circuit is further configured to provide second monitoring information, and output the second monitoring information to the second differential signal pin group of the display control chip via the third differential signal pin group; and

the display control chip is used for generating return information according to the first monitoring information and the second monitoring information and outputting the return information through the first differential signal pin group.

3. The display module of claim 1, wherein the first set of differential signal pins comprises: at least one pair of first differential data signal pins is used as a signal input pin, or the at least one pair of first differential data signal pins and one pair of first differential clock signal pins are used as the signal input pin.

4. The display module of claim 2, wherein the first set of differential signal pins comprises:

at least one pair of first differential data signal pins are used as signal input pins, or the at least one pair of first differential data signal pins and one pair of first differential clock signal pins are used as the signal input pins; and

at least one pair of second differential data signal pins is used as a signal output pin, or the at least one pair of second differential data signal pins and the pair of second differential clock signal pins are used as the signal output pin.

5. The display module of claim 1, wherein the display driving circuit further comprises: a fourth differential signal pin group;

the display module assembly includes: the display driving circuits are cascaded, the display driving circuit of the first stage and the display driving circuit of the last stage are both connected to the second differential signal pin group, and the fourth differential signal pin group of one display driving circuit in two adjacent display driving circuits is connected to the third differential signal pin group of the other display driving circuit.

6. The display module of claim 1, wherein the display driving circuit further comprises: a fourth differential signal pin group;

the display module assembly includes: a plurality of display driving circuit groups connected in parallel to the second differential signal pin group; wherein each of the display driving circuit groups includes a plurality of the display driving circuits connected in series, and the fourth differential signal pin group of one of the display driving circuits in two adjacent display driving circuits is connected to the third differential signal pin group of the other display driving circuit.

7. The display module according to claim 1, wherein the first differential signaling pin set transmits signals using an LVDS level protocol or a mini LVDS level protocol.

8. The display module of claim 2, wherein the display control chip comprises:

a memory;

a processor connecting the memory and the first set of differential signal pins;

the data analysis module is connected with the first differential signal pin group, the processor and the memory;

the image processing module is connected with the data analysis module, the processor and the memory;

the display driving module is connected with the image processing module, the second differential signal pin group, the processor and the memory;

the monitoring processing module is connected with the second differential signal pin group and the first differential signal pin group;

the data analysis module is used for receiving and analyzing the first LVDS data packet transmitted by the first differential signal pin group to obtain initial image data and the control information;

the image processing module is used for receiving the initial image data and carrying out image processing on the initial image data to obtain the image data;

the display driving module is used for receiving the image data, packaging the control information and the image data to obtain a second LVDS data packet, and outputting the second LVDS data packet to the display driving circuit through the second differential signal pin group; and

the monitoring processing module is used for generating the return information according to the first monitoring information and the second monitoring information and outputting the return information through the first differential signal pin group;

the data analysis module is further configured to receive and analyze the command data packet transmitted by the first differential signal pin group to obtain command data, and output the command data to the processor, so that the processor executes a related command operation based on the command data.

9. A display cabinet, comprising:

a data forwarding card comprising: a target differential signal pin group;

the display module of any one of claims 1-8, wherein the display module is directly connected to the set of target differential signal pins of the data forwarding card through the first set of differential signal pins.

10. The display cabinet of claim 9, wherein the data forwarding card comprises: the programmable logic device is used for receiving an input original data packet through the first data input interface, and performing format conversion on the original data packet to obtain a first LVDS data packet and outputting the first LVDS data packet through the target differential signal pin group; or

The data forwarding card comprises: the LVDS chip comprises the target differential signal pin set, and is used for receiving the input first LVDS data packet through the second data input interface and forwarding the input first LVDS data packet to be output through the target differential signal pin set.

Images