CN213845271U - Chip internal ground plane layout structure - Google Patents

Abstract

The utility model discloses a novel chip inside ground plane layout structure belongs to chip design technical field. The ground plane layout inside the chip is laid in a plane by adopting a ground wire unit array, and the ground wire unit array comprises a plurality of ground wire units which can be completely butted with each other. All the grounding areas are paved in the whole area, and the layers are fully connected through a large number of through holes, so that the parasitic resistance of the ground wire is reduced; the ground wire unit meets all process requirements, so that the problems of metal density and punching process do not need to be considered for the ground layout region with any width, area and shape, and the ground wire unit array is suitable for most layout design processes; the IR DROP is reduced to the minimum as much as possible by the largest grounding area, so that the ground potentials of all the modules are ensured to be consistent; when a plurality of ground wire units are called to form an array, all the ground wire units are in seamless butt joint, errors are not easy to occur, and the laying is convenient.

Description

Chip internal ground plane layout structure

Technical Field

The utility model belongs to the technical field of chip design, more specifically relates to chip inside ground plane territory structure.

Background

Each module, especially a radio frequency circuit module, in a chip layout structure needs to be well grounded.

In the prior art, the ground wires of each module need to be connected to a ground connection Pin (PAD) by a long wire, so that the long ground wires occupy a large layout area, and are too long to run, which also causes an excessive parasitic inductance and voltage DROP or rise (IR DROP) on a power supply and ground network.

In addition, if the long routing adopts a large-area metal layer ground wire, the local density of metal on the layout is too high, the yield is influenced, and the layout design rule is not met; the traditional large-area metal connecting wire is grounded, so that the grounding parasitic is large, and the grounding parasitic cannot be realized in silicon-based processes such as CMOS/SiGe/SOI and the like;

when various problems such as different distances from each module to the ground PAD, different metal densities, different punching processes and the like are processed, different layout engineers have different processing modes, so that the length and the width of wiring from the ground wire of each module to the ground PAD are different, and further the local ground potentials between the modules are different; even, in the layout design process, the situation that ground wires are disordered and too narrow and are not easy to find, the layout design efficiency is low, the ground contact is very poor easily occurs, and the problem that the grounding part is fused due to the fact that the wires are too thin can also occur under the extreme situation.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing, in order to overcome the not enough and proposed the inside ground plane territory structure of chip that prior art exists, adopt the ground wire unit to constitute the array and carry out the plane to the inside ground wire territory region of chip and lay, realize face ground connection.

The utility model provides a following technical scheme.

The ground plane layout inside the chip is laid in a plane by adopting a ground wire unit array, and the ground wire unit array comprises a plurality of ground wire units which can be completely butted with each other.

Each ground wire unit comprises an active layer and k layers of metal, the active layer is connected with the first layer of metal through a plurality of through holes, the first layer of metal is connected with the second layer of metal through a plurality of through holes, and the like, and the k-1 layer of metal is connected with the k layer of metal through a plurality of through holes.

Preferably, the first and second electrodes are formed of a metal,

the metal density required by the process rule is taken as a limit value, and the width of each layer of metal is designed according to the maximum value.

Preferably, the first and second electrodes are formed of a metal,

the number of the through holes between the active layer and the first layer of metal is determined by the area of the projection overlapping of the active layer and the first layer of metal, and the number of the through holes between two adjacent layers of metal is determined by the area of the projection overlapping of the two adjacent layers of metal.

Preferably, the first and second electrodes are formed of a metal,

the ground wire unit array is laid right above the protected signal wire to provide a ground path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

Preferably, the first and second electrodes are formed of a metal,

the ground wire unit array is laid right below the protected signal wire to provide a ground path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

Preferably, the first and second electrodes are formed of a metal,

when the protected signal line passes through the ground line unit array, deleting the mth layer of metal in each ground line unit, and taking the protected signal line as the mth layer, wherein m is more than or equal to 1 and less than or equal to k;

the m-1 th layer metal and the m +1 th layer metal adjacent to the protected signal line provide a ground path for the protected signal line.

The utility model adopts the above technical scheme, compare with prior art, have following technological effect:

1. the ground wire unit array provided by the utility model is applied to the radio frequency circuit layout, all grounding areas are laid in the whole area, and the layers are connected through a large number of through holes to ensure the sufficient connection, thereby reducing the parasitic resistance of the ground wire;

2. the ground wire unit meets all process requirements, so that the problems of metal density and punching process do not need to be considered for the ground layout region with any width, area and shape, and the ground wire unit array can be suitable for most layout design processes;

3. the traditional wiring grounding is changed into plane grounding, so that the largest grounding area is realized, and the IR DROP is reduced to the minimum as possible, thereby ensuring the consistency of the ground potentials of all modules;

4. when a plurality of ground wire units are called to form an array, all the ground wire units are in seamless butt joint, errors are not easy to occur, and the laying is convenient.

Drawings

Fig. 1 is a schematic diagram of a longitudinal structure of a single ground wire unit in the chip internal ground plane layout structure of the present invention;

fig. 2 is a top-view comparison diagram of each layer of metal of a single ground wire unit and each layer of metal of a 3 × 3 ground wire unit array in the chip internal ground plane layout structure of the present invention;

fig. 3 is a top view comparing diagram of the active layer of a single ground wire unit and the active layer of a 3 × 3 ground wire unit array in the chip internal ground plane layout structure of the present invention;

fig. 4 is a top view of the chip internal ground plane layout structure of the present invention.

Detailed Description

The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The ground plane layout inside the chip is laid in a plane by adopting a ground wire unit array, and the ground wire unit array comprises a plurality of ground wire units which can be completely butted with each other.

Each ground wire unit comprises an active layer and k layers of metal, the active layer is connected with the first layer of metal through a plurality of through holes, the first layer of metal is connected with the second layer of metal through a plurality of through holes, and the like, and the k-1 layer of metal is connected with the k layer of metal through a plurality of through holes.

In the preferred embodiment, the longitudinal structure of the ground wire unit is as shown in fig. 1, the ground wire unit includes an active layer and six layers of metals, the active layer is connected with the first layer of metal through a plurality of through holes, the first layer of metal is connected with the second layer of metal through a plurality of through holes, and so on, and the fifth layer of metal is connected with the sixth layer of metal through a plurality of through holes.

For each ground wire unit, the metal layers and the through holes can be modified in the attributes according to requirements, convenience and rapidness are achieved, and flexibility is strong.

The through hole design of each layer of metal refers to an optimal grounding connection mode realized by digging small holes in each layer of metal within the allowable range of the design rule. It should be noted that the design method of the through hole in the present invention includes, but is not limited to, the hole digging manner shown in fig. 2, and those skilled in the art can adopt any hole digging manner that meets the design rule. The design of the through holes in the preferred embodiment is a non-limiting preferred choice.

In the preferred embodiment, the shapes of the first to sixth layer metals in a single ground line unit and the 9 ground line units are extended to the shapes of the first to sixth layer metals in the ground line unit array in a 3 × 3 manner, as shown in fig. 2.

It should be noted that each ground wire unit can be completely connected, and those skilled in the art can implement complete connection of a plurality of ground wire units to form a ground wire unit array according to application requirements.

In particular, the amount of the solvent to be used,

the metal density required by the process rule is taken as a limit value, and the width of each layer of metal is designed according to the maximum value.

In the preferred embodiment, the shape of each layer of metal is as shown in figure 2,

in particular, the amount of the solvent to be used,

the number of the through holes between the active layer and the first layer of metal is determined by the area of the projection overlapping of the active layer and the first layer of metal, and the number of the through holes between two adjacent layers of metal is determined by the area of the projection overlapping of the two adjacent layers of metal.

Fig. 3 is a layout design schematic diagram of an active layer, and due to the adoption of the design of a ground wire unit, the connection of the ground wire and the substrate contact are combined into a whole, so that the parasitics of the substrate contact are effectively reduced. The lower left corner of fig. 3 also shows the ground line unit of the active layer grounded, and the right side shows the 3 × 3 ground line unit array formed by the ground line units.

In particular, the amount of the solvent to be used,

the ground wire unit array is laid right above the protected signal wire to provide a ground path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

In particular, the amount of the solvent to be used,

the ground wire unit array is laid right below the protected signal wire to provide a ground path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

In particular, the amount of the solvent to be used,

when the protected signal line passes through the ground line unit array, deleting the mth layer of metal in each ground line unit, and taking the protected signal line as the mth layer, wherein m is more than or equal to 1 and less than or equal to k;

the m-1 th layer metal and the m +1 th layer metal adjacent to the protected signal line provide a ground path for the protected signal line.

The utility model discloses the inside ground plane layout structure of chip is shown in figure 4.

The utility model adopts the above technical scheme, compare with prior art, have following technological effect:

1. the ground wire unit array provided by the utility model is applied to the radio frequency circuit layout, all grounding areas are laid in the whole area, and the layers are connected through a large number of through holes to ensure the sufficient connection, thereby reducing the parasitic resistance of the ground wire;

2. the ground wire unit meets all process requirements, so that the problems of metal density and punching process do not need to be considered for the ground layout region with any width, area and shape, and the ground wire unit array can be suitable for most layout design processes;

3. the traditional wiring grounding is changed into plane grounding, so that the largest grounding area is realized, and the IR DROP is reduced to the minimum as possible, thereby ensuring the consistency of the ground potentials of all modules;

4. when a plurality of ground wire units are called to form an array, all the ground wire units are in seamless butt joint, errors are not easy to occur, and the laying is convenient.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can understand the changes or substitutions within the technical scope of the present invention, and the present invention should be covered within the protection scope of the present invention.

Claims (6)

1. A chip internal ground plane layout structure is characterized in that,

the ground plane layout inside the chip adopts a ground wire unit array for plane laying, the ground wire unit array comprises a plurality of ground wire units which can be completely butted with each other,

each ground wire unit comprises an active layer and k layers of metal, the active layer is connected with the first layer of metal through a plurality of through holes, the first layer of metal is connected with the second layer of metal through a plurality of through holes, and the like, and the k-1 layer of metal is connected with the k layer of metal through a plurality of through holes.

2. The in-chip ground plane layout structure according to claim 1,

the metal density required by the process rule is taken as a limit value, and the width of each layer of metal is designed according to the maximum value.

3. The in-chip ground plane layout structure according to claim 1,

the number of the through holes between the active layer and the first layer of metal is determined by the area of the projection overlapping of the active layer and the first layer of metal, and the number of the through holes between two adjacent layers of metal is determined by the area of the projection overlapping of the two adjacent layers of metal.

4. The in-chip ground plane layout structure according to claim 1,

the ground wire unit array is laid right above the protected signal wire to provide a grounding path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

5. The in-chip ground plane layout structure according to claim 1,

the ground wire unit array is laid under the protected signal wire to provide a grounding path for the protected signal wire, and the protected signal wire and the ground wire unit array are connected through a plurality of through holes among the metal layers.

6. The in-chip ground plane layout structure according to claim 1,

when the protected signal line passes through the ground line unit array, deleting the mth layer of metal in each ground line unit, and taking the protected signal line as the mth layer, wherein m is more than or equal to 1 and less than or equal to k;

the m-1 th layer metal and the m +1 th layer metal adjacent to the protected signal line provide a ground path for the protected signal line.

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