CN213781601U - Semiconductor memory device with a plurality of memory cells - Google Patents
Semiconductor memory device with a plurality of memory cells Download PDFInfo
- Publication number
- CN213781601U CN213781601U CN202022837767.3U CN202022837767U CN213781601U CN 213781601 U CN213781601 U CN 213781601U CN 202022837767 U CN202022837767 U CN 202022837767U CN 213781601 U CN213781601 U CN 213781601U
- Authority
- CN
- China
- Prior art keywords
- transistor
- electric fuse
- electric
- memory
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The utility model provides a semiconductor memory device, including being the electric fuse array of ranks distribution, every row has the electric fuse unit group of a plurality of symmetries, every have the electric fuse memory of two symmetries in the electric fuse unit group, every all have two transistors in the electric fuse memory, all the transistors in every row are established ties in proper order. The utility model discloses in every row correspondence at the electric fuse array has set up two bit lines, electric fuse memory sharing one bit line on this line in the electric fuse unit group of odd number position in every row, electric fuse memory sharing another bit line on this line in the electric fuse unit group of even number position in every row to can lay out more electric fuse units under the same area, reduced the size of device.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor memory device.
Background
Efuse (electrically programmable Fuse) technology is a technology developed by using metal Electromigration (EM) characteristics, and unlike conventional Laser Fuse (Laser Fuse) technology, Efuse technology can be used to generate a much smaller electrical Fuse (E-Fuse) structure. The initial resistance of the electric fuse is small, and when a large current passes through the electric fuse, the electric fuse is blown, and the resistance value thereof is multiplied. The blown eFUSE will remain permanently open, while the unblown eFUSE remains open. Therefore, the data stored in the memory cell formed by the electric fuse is known by determining whether the electric fuse is blown or not.
The Efuse technology is mainly used for repairing chips on site, executing redundancy and the like. Compared with the conventional laser fuse technology, the Efuse technology mainly has the following advantages: the manufacturing method is completely compatible with the CMOS manufacturing process widely applied at present, does not add extra process steps, and has low price; the volume is small, the occupied area of a silicon chip is smaller, and higher flexibility can be provided, so that the method is widely applied to embedded systems and one-time programmable storage application; thirdly, due to the use of a polysilicon material which is one of the MOS grid, the contractibility of the future technology is good; the Efuse technology also has the function of repairing the chip on site, so that the programming after packaging can be realized, and no special instrument is needed for programming or testing, so that the Efuse technology not only can completely replace the application of the laser fuse, but also expands the application range of the Efuse technology.
An electric fuse (eFuse) is a One Time programming device (OTP for short), and can store data by programming, and as the theory and technology of the electric fuse gradually mature, the application range of the electric fuse rapidly expands. An electrical fuse IP Core (electrical fuse) includes an electrical fuse array, and with the shrinking of device size, how to layout as many electrical fuse cells as possible in the same area is a technical problem to be solved.
SUMMERY OF THE UTILITY MODEL
An object of the present invention is to provide a semiconductor memory device which can reduce the size of the device by arranging more electric fuse cells in the same area.
In order to achieve the above object, the present invention provides a semiconductor memory device, which includes an electrical fuse array distributed in rows and columns, each row having a plurality of electrical fuse unit groups, each electrical fuse unit group having two electrical fuse memories therein, each electrical fuse memory having two transistors therein, all the transistors in each row being connected in series in sequence;
two bit lines are correspondingly arranged in each row, the electric fuse unit group in each row is alternately connected with the two bit lines in the row, and all transistors in each electric fuse unit group share the connected bit lines.
Optionally, in two adjacent groups of the electrical fuse units in each row, two adjacent electrical fuse memories share one word line.
Optionally, in two adjacent rows of the groups of efuse units in each column, two adjacent rows of the efuse memories share one word line.
Optionally, two efuse memories in the efuse cell group are a first efuse memory and a second efuse memory respectively, two transistors in the first efuse memory are a first switch transistor and a first storage transistor respectively, two transistors in the second efuse memory are a second switch transistor and a second storage transistor respectively, and the first storage transistor and the second storage transistor are used as efuses;
the grid electrode of the first switch transistor is connected with the source electrode of the first switch transistor and the corresponding word line, and the drain electrode of the first switch transistor is connected with the grid electrode and the source electrode of the first storage transistor;
the grid electrode of the second switch transistor is connected with the drain electrode of the second switch transistor and the corresponding word line, and the source electrode of the second switch transistor is connected with the drain electrode and the grid electrode of the second storage transistor;
the drain of the first storage transistor is connected to the source of the second storage transistor.
Optionally, the drain of the first memory transistor is connected to the source of the second memory transistor through a first electrical connection, and the first electrical connection in each group of electrical fuse units is alternately connected to two bit lines of the row.
Optionally, the gate of each column of the first switching transistor is of an integrated structure; and/or the grid electrode of the second switch transistor in each column is of a whole structure.
Optionally, the gate of the first switch transistor in each column is connected to the gate of the second switch transistor in an adjacent column via a second electrical connection.
Optionally, the gate of the first switch transistor in each column is connected to the gate of the second switch transistor in an adjacent column by at least two second electrical connections.
Optionally, the gate of the first switch transistor in each row is connected to the gate of the adjacent second switch transistor by one of the second electrical connections.
Optionally, the gate of the first memory transistor is connected to the source thereof through a third electrical connection, and the gate of the second memory transistor is connected to the drain thereof through a fourth electrical connection.
The utility model provides a semiconductor memory device has the electric fuse unit group of a plurality of symmetries including being the electric fuse array of ranks distribution, every row has the electric fuse memory of two symmetries in the electric fuse unit group, every all have two transistors in the electric fuse memory, all the transistors of every row are established ties in proper order. The utility model discloses in every row correspondence at the electric fuse array has set up two bit lines, electric fuse memory sharing one bit line on this line in the electric fuse unit group of odd number position in every row, electric fuse memory sharing another bit line on this line in the electric fuse unit group of even number position in every row to can lay out more electric fuse units under the same area, reduced the size of device.
Drawings
Fig. 1a is a partial schematic view of an electrical fuse array according to an embodiment of the present invention;
fig. 1b is a partial schematic view of an electrical fuse array according to an embodiment of the present invention;
fig. 2 is a partial schematic view of an electrical fuse array according to a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
The embodiment provides a semiconductor memory device, which comprises an electric fuse array distributed in rows and columns, wherein each row is provided with a plurality of electric fuse unit groups, each electric fuse unit group is provided with two electric fuse memories, each electric fuse memory is provided with two transistors, and all the transistors in each row are sequentially connected in series;
two bit lines are correspondingly arranged in each row, the electric fuse unit group in each row is alternately connected with the two bit lines in the row, and all transistors in each electric fuse unit group share the connected bit lines.
Specifically, fig. 1a is a partial schematic diagram of an electrical fuse array provided in this embodiment. As shown in fig. 1, the efuse array has 4 rows, each row having 3 efuse cell groups, which are efuse cell group a, efuse cell group B, and efuse cell group C, respectively, where efuse cell group a is adjacent to efuse cell group B, and efuse cell group B is adjacent to efuse cell group C. The electric fuse unit group a is provided with two electric fuse memories, namely a first electric fuse memory a1 and a second electric fuse memory a2, and the first electric fuse memory a1 corresponds to the second electric fuse memory a2 in connection relation; the electric fuse unit group B is provided with two electric fuse memories, namely a first electric fuse memory B1 and a second electric fuse memory B2, and the first electric fuse memory B1 corresponds to the second electric fuse memory B2 in connection relation; the electrical fuse unit group C has two electrical fuse memories, namely a first electrical fuse memory C1 and a second electrical fuse memory C2, and the first electrical fuse memory C1 and the second electrical fuse memory C2 are connected correspondingly.
Each electric fuse memory is provided with two transistors which are distributed in a row; each group of electric fuse cells has 4 transistors, and thus each row in fig. 1a has 12 transistors, and the sources and drains of the 12 transistors are connected in series in order to connect the 12 transistors in series in turn.
Referring to fig. 1a, two bit lines, namely a bit line BL11 and a bit line BL12, are correspondingly disposed in the first row; two bit lines are correspondingly arranged in the second row, namely a bit line BL21 and a bit line BL 22; the third row is correspondingly provided with two bit lines, namely a bit line BL31 and a bit line BL 32; the fourth row is correspondingly provided with two bit lines, namely a bit line BL41 and a bit line BL 42. Taking the first row as an example, the electric fuse cell group a and the electric fuse cell group C are connected to the bit line BL11, all transistors in the electric fuse cell group a and the electric fuse cell group C share the bit line BL11, the electric fuse cell group B is connected to the bit line BL12, and all transistors in the electric fuse cell group B share the bit line BL 12. Similarly to the first row, the groups of electric fuse cells in the second row to the fourth row are alternately connected to two bit lines of the row, and are not explained one by one here.
Further, in two adjacent groups of the electric fuse cells in each row, two adjacent electric fuse memories share one word line. With continued reference to fig. 1a, the group a of efuses is adjacent to the group B of efuses, and the second efuse a2 shares the word line WL2 with the first efuse B1; the electric fuse cell group B is adjacent to the electric fuse cell group C, and the second electric fuse memory B2 shares the word line WL3 with the first electric fuse memory C1. Similarly, the word line WL1 is shared by the first electrical fuse memory a1 and its neighboring second electrical fuse memory (not shown), and the word line WL4 is shared by the second electrical fuse memory C2 and its neighboring first electrical fuse memory (not shown).
And in two adjacent rows of the electric fuse unit groups in each column, two adjacent rows of the electric fuse memory share one word line. With continued reference to fig. 1a, the efuse memories belonging to the same column as the first efuse memory a1 (the efuse memories corresponding to the position of the first efuse memory a1 in the remaining rows) share the word line WL 1; the electric fuse memories belonging to the same column as the second electric fuse memory a2 (the electric fuse memories corresponding to the position of the second electric fuse memory a2 in the remaining rows) share the word line WL 2; the electric fuse memories belonging to the same column as the first electric fuse memory B1 (the electric fuse memories corresponding to the position of the first electric fuse memory B1 in the remaining rows) share the word line WL 2; the electric fuse memories belonging to the same column as the second electric fuse memory B2 (the electric fuse memories corresponding to the position of the second electric fuse memory B2 in the remaining rows) share the word line WL 3; the electric fuse memories belonging to the same column as the first electric fuse memory C1 (the electric fuse memories corresponding to the position of the first electric fuse memory C1 in the remaining rows) share the word line WL 3; the electric fuse memories belonging to the same column as the second electric fuse memory C2 (the electric fuse memories corresponding to the position of the second electric fuse memory C2 in the remaining rows) share the word line WL 4.
Compared with the case that two electric fuse memories in each electric fuse unit group are respectively controlled by one word line, the area of the electric fuse array can be further reduced by sharing the word lines of the adjacent electric fuse memories in the adjacent electric fuse unit groups, and the electric fuse array can arrange more electric fuse units in the same area.
Further, the two transistors in each electrical fuse memory are a switching transistor and a storage transistor, respectively, and the storage transistors serve as electrical fuses. The grid electrode of the first switch transistor is connected with the source electrode of the first switch transistor and the corresponding word line, and the drain electrode of the first switch transistor is connected with the grid electrode and the source electrode of the first storage transistor; the grid electrode of the second switch transistor is connected with the drain electrode of the second switch transistor and the corresponding word line, and the source electrode of the second switch transistor is connected with the drain electrode and the grid electrode of the second storage transistor; the drain of the first storage transistor is connected to the source of the second storage transistor.
With reference to fig. 1a, taking the first row as an example, the two transistors in the first electrical fuse memory a1 are the first switch transistor a11 and the first memory transistor a12, respectively, and the two transistors in the second electrical fuse memory a2 are the first switch transistor a21 and the second memory transistor a22, respectively; two transistors in the first electrical fuse memory B1 are a first switching transistor B11 and a first storage transistor B12, respectively, and two transistors in the second electrical fuse memory B2 are a first switching transistor B21 and a second storage transistor B22, respectively; two transistors in the first electrical fuse memory C1 are a first switching transistor C11 and a first storage transistor C12, respectively, and two transistors in the second electrical fuse memory C2 are a first switching transistor C21 and a second storage transistor C22, respectively. The first storage transistor a12, the second storage transistor a22, the first storage transistor B12, the first storage transistor B22, the first storage transistor C12 and the second storage transistor C22 are used as electric fuses.
Taking the first electrical fuse memory B1 and the second electrical fuse memory B2 as an example, the gate G11 of the first switch transistor B11 is connected to the source S11 and the word line WL2 thereof, and the drain D11 is connected to the gate G12 and the source S12 of the first memory transistor B12; the gate G21 of the second switch transistor B21 is connected to the drain D21 and the word line WL3, the source S21 is connected to the drain D22 and the gate G22 of the second memory transistor B22, and the drain D12 of the first memory transistor B12 is connected to the source S22 of the second memory transistor B22. Similarly, the first electrical fuse memory a1 and the second electrical fuse memory a2, and the first electrical fuse memory C1 and the second electrical fuse memory C2 are also the same connection method as the first electrical fuse memory B1 and the second electrical fuse memory B2, and a description thereof is not repeated one by one.
Fig. 1b is another partial schematic diagram of an electrical fuse array provided in this embodiment. Referring to fig. 1a and 1b, in the present embodiment, the sources and the drains of all the transistors are located in the same substrate, and the gates of all the transistors are located on the substrate. In this way, the active regions corresponding to the sources and drains of all the transistors can be connected into a whole, and the connected sources and drains can be connected in a common manner, for example, the source S11 of the first switch transistor B11 can be shared with the drain of the first switch transistor a21, the drain D11 of the first switch transistor B11 can be shared with the source S12 of the first memory transistor B12, the drain D12 of the first memory transistor B12 can be shared with the source S22 of the second memory transistor B22, the drain D22 of the second memory transistor B22 can be shared with the source S21 of the second switch transistor B21, and the drain D21 of the second switch transistor B21 can be shared with the source of the first switch transistor C11; thus, area can be saved more.
Further, the drain of the first memory transistor is connected with the source of the second memory transistor through a first electrical connection, and the first electrical connection in each group of electrical fuse units is alternately connected with two bit lines of the row. Taking the group B of efuses as an example, the first electrical connector 101B is disposed on the drain D12 of the first memory transistor B12 and the source S22 of the second memory transistor B22, and the first electrical connector 101B is connected to the drain D12 of the first memory transistor B12 and the source S22 of the second memory transistor B22; of course, in the electric fuse cell group a, the drain of the first memory transistor a12 and the source of the second memory transistor a22 are also connected through one first electric connection 101 a; in the electric fuse cell group C, the drain of the first memory transistor C12 and the source of the second memory transistor C22 are also connected through one first electric connection 101C. The first electrical connector 101a and the first electrical connector 101C are connected to the bit line BL11, and the first electrical connector 101B is connected to the bit line BL12, so that all transistors in the electric fuse cell group a and the electric fuse cell group C share the bit line BL11, and all transistors in the electric fuse cell group B share the bit line BL 12.
In this embodiment, the gate of each row of the first switch transistors is an integrated structure, the gate of each row of the second switch transistors is an integrated structure, and the gate of each row of the first switch transistors is connected to the gate of the adjacent row of the second switch transistors through a second electrical connection. With continued reference to fig. 1a and 1b, the gates of all the switch transistors in the same row as the first switch transistor a11 are connected to form a single gate, and the gates of all the switch transistors in the same row as the second switch transistor a21 are connected to form a single gate; the gates of all the switching transistors in the same column as the first switching transistor B11 are connected in one line, and the gates of all the switching transistors in the same column as the second switching transistor B21 are connected in one line; the gates of all the switching transistors in the same column as the first switching transistor C11 are connected to one, and the gates of all the switching transistors in the same column as the second switching transistor C21 are connected to one. One gate of the second switching transistor a21 is connected to one gate of the first switching transistor B11 by a second electrical connection 102 a; one gate of the second switch transistor B21 is connected to one gate of the first switch transistor C11 by a second electrical connection 102B. The word lines can be shared by connecting the second electrical connectors 102a and 102b to the word lines WL2 and WL3, respectively.
Further, the grid electrode of the first storage transistor is connected with the source electrode of the first storage transistor through a third electric connection piece, and the grid electrode of the second storage transistor is connected with the drain electrode of the second storage transistor through a fourth electric connection piece. Taking the first memory transistor B12 and the second memory transistor B22 as an example, the gate G12 of the first memory transistor B12 is connected to its source S12 through the third electrical connection 103, and the gate G22 of the second memory transistor B22 is connected to its drain D22 through the fourth electrical connection 104. Of course, the connection of the first and second memory transistors a12 and a22, and the first and second memory transistors C12 and C22 are also the same, and will not be illustrated.
It should be understood that, in the present embodiment, the first electrical connection member, the second electrical connection member and the third electrical connection member are all contact holes formed in the dielectric layer.
Example two
The difference from the first embodiment is that in the present embodiment, the gate of the first switch transistor in each column is connected to the gate of the second switch transistor in the adjacent column through at least two second electrical connections.
Fig. 2 is a partial schematic view of an electrical fuse array provided in the present embodiment. As shown in fig. 2, the gate of the first switch transistor in each column is an integral structure, the gate of the second switch transistor in each column is an integral structure, and the gate of the first switch transistor in each column is connected to the gate of the second switch transistor in an adjacent column through at least two second electrical connectors. With continued reference to fig. 1a and 2, the gates of all the switch transistors in the same row as the first switch transistor a11 are connected to form a single gate, and the gates of all the switch transistors in the same row as the second switch transistor a21 are connected to form a single gate; the gates of all the switching transistors in the same column as the first switching transistor B11 are connected in one line, and the gates of all the switching transistors in the same column as the second switching transistor B21 are connected in one line; the gates of all the switching transistors in the same column as the first switching transistor C11 are connected to one, and the gates of all the switching transistors in the same column as the second switching transistor C21 are connected to one. One gate of the second switching transistor a21 is connected to one gate of the first switching transistor B11 by at least two second electrical connections 102 a; one gate of the second switching transistor B21 is connected to one gate of the first switching transistor C11 by at least two second electrical connections 102B. The word lines can be shared by connecting the second electrical connectors 102a and 102b to the word lines WL2 and WL3, respectively.
Further, the grid electrode of the first switch transistor in each row is connected with the grid electrode of the adjacent second switch transistor through the second electric connection piece, and therefore the conducting performance of the word line is improved. For example, the gates of all the switch transistors of the column in which the second switch transistor a21 is located are connected to the gates of the corresponding switch transistors of the column in which the first switch transistor B11 is located by a second electrical connection 102 a; the gates of all the switching transistors of the column in which the second switching transistor B21 is located are connected to the gates of the corresponding switching transistors of the column in which the first switching transistor C11 is located by a second electrical connection 102B.
To sum up, the utility model provides a semiconductor memory device, including being the electric fuse array of ranks distribution, every row has the electric fuse unit group of a plurality of symmetries, every electric fuse memory that has two symmetries in the electric fuse unit group, every all have two transistors in the electric fuse memory, all transistors in every row are established ties in proper order. The utility model discloses in every row correspondence at the electric fuse array has set up two bit lines, electric fuse memory sharing one bit line on this line in the electric fuse unit group of odd number position in every row, electric fuse memory sharing another bit line on this line in the electric fuse unit group of even number position in every row to can lay out more electric fuse units under the same area, reduced the size of device.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.
Claims (10)
1. A semiconductor memory device is characterized by comprising an electric fuse array distributed in rows and columns, wherein each row is provided with a plurality of electric fuse unit groups, each electric fuse unit group is provided with two electric fuse memories, each electric fuse memory is provided with two transistors, and all the transistors in each row are sequentially connected in series;
two bit lines are correspondingly arranged in each row, the electric fuse unit group in each row is alternately connected with the two bit lines in the row, and all transistors in each electric fuse unit group share the connected bit lines.
2. The semiconductor memory device according to claim 1, wherein, of two adjacent groups of the electric fuse cells in each row, two adjacent electric fuse memories share one word line.
3. The semiconductor memory device according to claim 2, wherein, of the two adjacent rows of the groups of the electric fuse cells in each column, the two adjacent rows of the electric fuse cells share one word line.
4. The semiconductor memory device according to any one of claims 1 to 3, wherein two electric-fuse memories in the electric-fuse cell group are a first electric-fuse memory and a second electric-fuse memory, respectively, two transistors in the first electric-fuse memory are a first switching transistor and a first memory transistor, respectively, two transistors in the second electric-fuse memory are a second switching transistor and a second memory transistor, respectively, the first memory transistor and the second memory transistor being electric fuses;
the grid electrode of the first switch transistor is connected with the source electrode of the first switch transistor and the corresponding word line, and the drain electrode of the first switch transistor is connected with the grid electrode and the source electrode of the first storage transistor;
the grid electrode of the second switch transistor is connected with the drain electrode of the second switch transistor and the corresponding word line, and the source electrode of the second switch transistor is connected with the drain electrode and the grid electrode of the second storage transistor;
the drain of the first storage transistor is connected to the source of the second storage transistor.
5. The semiconductor memory device according to claim 4, wherein the drain of the first memory transistor and the source of the second memory transistor are connected by a first electric connection, and the first electric connection in each electric fuse cell group is alternately connected to two bit lines of the row.
6. The semiconductor memory device according to claim 4, wherein the gate of the first switching transistor of each column is a unitary structure; and/or the grid electrode of the second switch transistor in each column is of a whole structure.
7. The semiconductor memory device according to claim 6, wherein the gate of the first switching transistor of each column is connected to the gate of the second switching transistor of an adjacent column via a second electrical connection.
8. The semiconductor memory device according to claim 6, wherein the gate of the first switching transistor of each column is connected to the gate of the second switching transistor of an adjacent column by at least two second electrical connections.
9. The semiconductor memory device of claim 8, wherein the gate of a first switch transistor in each row is connected to the gate of an adjacent second switch transistor by one of said second electrical connections.
10. The semiconductor memory device according to claim 4, wherein the gate of the first memory transistor is connected to its source by a third electrical connection, and the gate of the second memory transistor is connected to its drain by a fourth electrical connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022837767.3U CN213781601U (en) | 2020-11-30 | 2020-11-30 | Semiconductor memory device with a plurality of memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022837767.3U CN213781601U (en) | 2020-11-30 | 2020-11-30 | Semiconductor memory device with a plurality of memory cells |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213781601U true CN213781601U (en) | 2021-07-23 |
Family
ID=76895206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022837767.3U Active CN213781601U (en) | 2020-11-30 | 2020-11-30 | Semiconductor memory device with a plurality of memory cells |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213781601U (en) |
-
2020
- 2020-11-30 CN CN202022837767.3U patent/CN213781601U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106981300B (en) | One-time programming memory cell, memory array and related random code generation method | |
| US6128241A (en) | Repair circuit of semiconductor memory device using anti-fuse | |
| KR100630519B1 (en) | Dimension programmable fusebanks and methods for making the same | |
| US20110241077A1 (en) | Integrated circuit 3d memory array and manufacturing method | |
| JPH0254500A (en) | Semiconductor memory cell and semiconductor memory device | |
| US4393474A (en) | EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like | |
| US5793666A (en) | Single-chip memory system having an array of read-only memory cells | |
| US5452258A (en) | Semiconductor read only memory | |
| CN213781601U (en) | Semiconductor memory device with a plurality of memory cells | |
| US9263383B2 (en) | Anti-fuse array of semiconductor device and method for operating the same | |
| CN113571511A (en) | Layout structure of anti-fuse array | |
| CN112349313B (en) | Semiconductor memory device with a plurality of memory cells | |
| JP2000150821A (en) | Semiconductor storage device | |
| JP2003309177A (en) | Semiconductor device | |
| US7683456B2 (en) | Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods | |
| US9007802B2 (en) | E-fuse array circuit | |
| CN113327641B (en) | EFuse memory cell, eFuse memory array, method of using eFuse memory cell, eFuse system | |
| US9123428B2 (en) | E-fuse array circuit | |
| US6459642B1 (en) | Semiconductor memory device | |
| US6906969B2 (en) | Hybrid fuses for redundancy | |
| KR100372250B1 (en) | Semiconductor memory device | |
| CN114357926A (en) | Layout method of electric fuse unit array | |
| US6680857B2 (en) | Unit-architecture with implemented limited bank-column-select repairability | |
| KR100878496B1 (en) | Semiconductor device and Method for fabricating the same | |
| KR100400771B1 (en) | Circuit for Word Line Redundancy |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |