CN213751052U - Dual-core chip capable of performing program backup and recovery - Google Patents

Dual-core chip capable of performing program backup and recovery Download PDF

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CN213751052U
CN213751052U CN202022194088.9U CN202022194088U CN213751052U CN 213751052 U CN213751052 U CN 213751052U CN 202022194088 U CN202022194088 U CN 202022194088U CN 213751052 U CN213751052 U CN 213751052U
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cpu1
cpu2
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program
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蔡晓杰
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Suzhou Haipeng Technology Co ltd
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Suzhou Haipeng Technology Co ltd
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Abstract

The utility model discloses a can carry out program backup and dual-core chip of recovering, dual-core chip, include: a first central processing unit CPU1, abbreviated CPU 1; a second central processor CPU2, abbreviated CPU2, communicatively connected to the first central processor CPU1 via an internal communication bus; a first flash module operated by the first central processor CPU1, comprising a CPU1 boot loader region, a CPU1 application execution region, a CPU1 application staging region, and a CPU2 application backup region; a second flash module operated by the second central processor CPU2, comprising a CPU2 boot loader region, a CPU2 application execution region, a CPU2 application staging region, and a CPU1 application backup region; the dual-core chip is communicated with the outside through an external communication bus. To sum up, the utility model provides a dual-core chip has realized program backup and recovery simply reliably through utilizing the inside Flash space of chip, has improved entire system's MTBF, has improved whole embedded system's anti-interference recovery ability.

Description

Dual-core chip capable of performing program backup and recovery
[ technical field ] A method for producing a semiconductor device
The utility model belongs to the technical field of embedded system and specifically relates to a can carry out program backup and dual-core chip who resumes.
[ background of the invention ]
Once a program of the embedded system is updated and has errors, the system is down, cannot be recovered through remote upgrade again, and can only be maintained on site or returned to the factory, so that the after-sale maintenance cost is increased, and the service life of the whole embedded system is reduced.
Therefore, there is a need to provide a new technical solution to overcome the above problems.
[ Utility model ] content
The to-be-solved technical problem of the utility model is to provide a can carry out program backup and the dual-core chip who restores, it does not utilize external storage device, just can be safe quick carry out cross backup and restore fast.
In order to solve the above problem, according to the utility model discloses an aspect, the utility model provides a dual-core chip, it includes: a first central processing unit CPU1, abbreviated CPU 1; a second central processing unit CPU 2; a first flash module operated by the first central processor CPU1, comprising a CPU1 boot loader region, a CPU1 application execution region, a CPU1 application staging region, and a CPU2 application backup region; a second flash module operated by the second central processor CPU2, comprising a CPU2 boot loader region, a CPU2 application execution region, a CPU2 application staging region, and a CPU1 application backup region; an internal communication bus for communication connection between the first CPU1 and the second CPU 2; an external communication bus for the first CPU1 and the second CPU2 to communicate with the outside.
Compared with the prior art, the utility model provides a dual-core chip does not utilize outside storage device, just can be safe quick alternately backup and restore fast to under the special case, single chip procedure makes mistakes and leads to the unable normal operating of system, thereby prolongs whole embedded system's life, and entire system's interference immunity.
With regard to other objects, features and advantages of the present invention, the following detailed description will be made in conjunction with the accompanying drawings.
[ description of the drawings ]
The present invention will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
fig. 1 is a schematic structural diagram of a dual core chip according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a program recovery method of the dual core chip shown in FIG. 1 in one embodiment;
FIG. 3 is a flow chart illustrating a program recovery method of the dual core chip shown in FIG. 1 according to another embodiment;
fig. 4 is a flowchart illustrating a program backup method of the dual core chip shown in fig. 1 according to an embodiment.
[ detailed description ] embodiments
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The term "a plurality" or "a plurality" in the present invention means two or more than two. In the present invention, "and/or" means "and" or ".
Please refer to fig. 1, which is a schematic structural diagram of a dual core chip according to an embodiment of the present invention. The dual core chip 110 shown in fig. 1 includes a first Central Processing Unit (CPU) 1, a second central processing unit (CPU 2), a first flash memory module 112 (or flash memory), and a second flash memory module 114.
The first central processor CPU1 is communicatively connected to the second central processor CPU2 via an internal communication bus; the first flash module 112 is operated by the first central processor CPU1 (or the first central processor CPU1 performs rights management on the first flash module 112); the second flash module 114 is operated by the second central processor CPU2 (or the second central processor CPU2 performs rights management on the second flash module 114).
For convenience of description, the CPU1 is the first CPU1, and the CPU2 is the second CPU 2.
The first flash memory module 112 is divided into four regions: the first area is a BootLoader (BootLoader) area of the CPU1, the second area is an application program execution area of the CPU1, the third area is a temporary storage area of the application program of the CPU1, and the fourth area is an application program backup area of the CPU 2. The CPU1 boots a loader (BootLoader) area as a fixed program, which is used to execute the upgrade; the CPU1 application execution area is used to store applications that the CPU1 actually runs (or applications that the CPU1 normally runs); the CPU1 application program temporary storage area is used for storing programs to be upgraded of the CPU 1; the CPU2 application backup area is used to backup a complete CPU2 program. The second flash module 114 also separates into four regions: the first area is a BootLoader (BootLoader) area of the CPU2, the second area is an application program execution area of the CPU2, the third area is a temporary storage area of the application program of the CPU2, and the fourth area is an application program backup area of the CPU 1. The CPU2 boots a loader (BootLoader) area as a fixed program, which is used to execute the upgrade; the CPU2 application execution area is used to store applications that the CPU2 actually runs (or applications that the CPU2 normally runs); the CPU2 application program temporary storage area is used for storing programs to be upgraded of the CPU 2; the CPU1 application backup area is used to backup a complete CPU1 program. That is, the CPU1 bootloader area and the CPU2 bootloader area are respectively used for storing the bootloader of the CPU corresponding thereto, and respectively used for receiving the upgrade application of the CPU corresponding thereto and performing the upgrade; the CPU1 application program execution area and the CPU2 application program execution area are respectively used for storing application programs actually run by the corresponding CPUs; the CPU1 application program temporary storage area and the CPU2 application program temporary storage area are respectively used for storing programs to be upgraded of the corresponding CPUs; the CPU1 application backup area and the CPU2 application backup area are respectively used for backing up complete counterpart CPU programs, i.e., the CPU2 program is backed up in the CPU1, and the CPU1 program is backed up in the CPU 2.
In the embodiment shown in fig. 1, the first Flash module 112 is located inside the first CPU1, that is, the first Flash module 112 is an internal Flash of the first CPU 1; the second Flash memory module 114 is located inside the second CPU2, that is, the second Flash memory module 114 is an internal Flash of the second CPU 2.
Two peripherals are related to upgrading, one is an internal communication bus which is connected with the CPU1 and the CPU2 and is used for communication between the CPU1 and the CPU 2; one is an external communication bus, which may be I2C, SPI, SCI, CAN, etc., which is used for the dual-core chip 110 to communicate (or communicate) with the external communication device 120.
Fig. 2 is a flowchart illustrating a program recovery method of the dual core chip shown in fig. 1 according to an embodiment. The program recovery method for the dual-core chip shown in fig. 2 is to find program abnormality and actively recover the dual-core chip 110 itself, and takes the CPU1 as an example, and specifically introduces the program recovery method for the CPU1 in the dual-core chip shown in fig. 1, which includes the following steps.
Step 201, the CPU1 checks whether the system is normal (or whether the CPU1 self-test program is normal), if normal (yes), the check is continued, and if not normal (no), the process goes to step 2.
In step 202, the CPU1 stops operating and starts the resume routine.
In step 203, the CPU1 notifies the CPU2 of stopping its operation via the internal communication bus.
In step 204, the CPU2 sends the CPU1 program backed up in the CPU1 application backup area in the FLASH (i.e., the second FLASH module) 114 of the CPU2 to the CPU1 via the internal communication bus.
In step 205, the CPU1 begins to check the received CPU1 program, and if the program passes the check (yes), the process proceeds to step 208, and if the check does not pass (no), the process proceeds to step 206.
Step 206, it is determined whether the check does not pass more than three times, and if it does, the process proceeds to step 207, and if it does not pass more than three times (no), the process proceeds to step 204.
And step 207, sending a recovery failure instruction through the external communication bus, and ending.
In step 208, the CPU1 writes the received CPU1 program into the CPU1 application buffer of the FLASH (i.e., the first FLASH module) 112 of the CPU 1.
Step 209, CPU1 sets the level update flag bit.
Step 210, CPU1 and CPU2 restart into respective bootloaders.
In step 211, the CPU1 transfers the CPU1 program from the CPU1 program buffer of its internal FLASH (i.e., the first FLASH module) 112 to the CPU1 program execution area.
Step 212, CPU1 resets the program update flag.
Step 213, CPU1 and CPU2 again restart into the respective bootloaders.
Step 214, CPU1, and CPU2 function normally. Specifically, the CPU1 and the CPU2 load respective application execution area data and start normal operation. For example, the CPU1 loads data of the CPU1 program execution area of its internal Flash (i.e., first Flash module) 112; the CPU2 loads data of the CPU1 program execution area of its internal Flash (i.e., second Flash module) 114.
Step 215, the CPU1 sends a resume success instruction through the external communication bus, and ends.
It should be noted that the program recovery method of the CPU2 in the dual-core chip shown in fig. 1 is similar to the program recovery method of the CPU1 in the dual-core chip shown in fig. 2, and therefore, the detailed description thereof is omitted here.
Fig. 3 is a flowchart illustrating a program recovery method for the dual core chip shown in fig. 1 according to another embodiment. The program recovery method of the dual core chip shown in fig. 3 is to send an instruction for external communication to recover the programs of the CPU1 and the CPU 2. The program recovery method of the dual core chip shown in fig. 3 includes the following steps.
In step 301, the CPU1 receives a program resume instruction based on the external communication bus, and starts execution of resume.
At step 302, the CPU1 stops operating.
Step 303, the CPU1 notifies the CPU2 to stop operating via the internal communication bus.
In step 304, the CPU2 transmits the CPU1 program backed up in the CPU1 application backup area in the FLASH (i.e., second FLASH module) 114 of the CPU2 to the CPU1 via the internal communication bus.
Step 305, the CPU1 begins to verify the received CPU1 program, and proceeds to step 308 if the program passes the verification (yes), and proceeds to step 306 if the verification fails (no).
Step 306, it is determined whether the check does not pass more than three times, and if it does, the process proceeds to step 307, and if it does not pass more than three times (no), the process proceeds to step 304.
And 307, sending a recovery failure instruction through the external communication bus, and ending.
In step 308, the CPU1 writes the received CPU1 program into the CPU1 application buffer of the FLASH (i.e., the first FLASH module) 112 of the CPU 1.
In step 309, the CPU1 sends the CPU2 program backed up in the CPU2 application backup area in the FLASH (i.e., the first FLASH module) 112 of the CPU1 to the CPU2 via the internal communication bus.
In step 310, the CPU2 begins to verify the received CPU2 program, and if the program passes the verification (yes), the process proceeds to step 312, and if the verification does not pass (no), the process proceeds to step 311.
In step 311, it is determined whether the check does not pass more than three times, and if it does, the process proceeds to step 307, and if it does not pass more than three times (no), the process proceeds to step 309.
In step 312, the CPU2 writes the received CPU2 program into the CPU2 application buffer of the FLASH (i.e., the second FLASH module) 114 of the CPU 2.
Step 313, CPU1 and CPU2 set the level update flag.
Step 314, CPU1 and CPU2 restart into the respective bootloaders.
In step 315, the CPU1 and the CPU2 transfer (or copy) data from the program temporary storage area of the respective internal Flash to the program execution area. Specifically, the CPU1 and the CPU2 determine that the program update flag bit is high, and start copying data from the respective program temporary area to the program execution area. For example, the CPU1 copies data (e.g., the aforementioned CPU1 program) from the CPU1 application program scratch area of its internal Flash (i.e., first Flash module) 112 to the CPU1 program execution area; the CPU2 copies data (e.g., the aforementioned CPU2 program) from the CPU2 application staging area of its internal Flash (i.e., second Flash module) 114 to the CPU2 program execution area.
Step 316, CPU1 and CPU2 reset the program update flag.
Step 317, CPU1 and CPU2 are again restarted into their respective bootloaders.
Step 318, CPU1, and CPU2 operate normally. Specifically, the CPU1 and the CPU2 load respective application execution area data and start normal operation. For example, the CPU1 loads data of the CPU1 program execution area of its internal Flash (i.e., first Flash module) 112; the CPU2 loads data of the CPU1 program execution area of its internal Flash (i.e., second Flash module) 114.
Step 319, the CPU1 sends a resume success instruction through the external communication bus, and ends.
Fig. 4 is a flowchart illustrating a program backup method of the dual core chip shown in fig. 1 according to an embodiment. The program backup method of the dual core chip shown in fig. 4 is to send an instruction for external communication to perform program backup on the CPU1 and the CPU 2. The program backup method of the dual core chip shown in fig. 4 includes the following steps.
In step 401, the CPU1 receives a program backup instruction based on the external communication bus, and starts executing backup.
Step 402, the CPU2 sends the CPU2 program in the CPU2 application execution area in the internal FLASH (i.e., the second FLASH module) 114 of the CPU2 to the CPU1 through the internal communication bus;
in step 403, the CPU1 begins to verify the received CPU2 program, and proceeds to step 406 if the program passes the verification (YES) and proceeds to step 404 if the verification does not pass (NO).
Step 404, determining whether the check does not pass more than three times (or is repeated three times), if so, entering step 405, and if not, entering step 402.
Step 405, sending a backup failure instruction through the external communication bus, and ending.
In step 406, the CPU1 writes the received CPU2 program into the CPU2 application backup area of the FLASH (i.e., the first FLASH module) 112 of the CPU 1.
Step 407, the CPU1 sends the CPU1 program in the CPU1 application execution area in the internal FLASH (i.e., the first FLASH module) 112 of the CPU1 to the CPU2 through the internal communication bus;
in step 408, the CPU2 begins checking the received CPU1 program, and proceeds to step 410 if the program passes the check (YES) and proceeds to step 409 if the check does not pass (NO).
Step 409, determining whether the check does not pass more than three times (or is repeated three times), if so, entering step 405, and if not, entering step 407.
In step 410, the CPU2 writes the received CPU1 program into the CPU1 application backup area of the FLASH (i.e., the second FLASH module) 114 of the CPU 2.
Step 411, sending a backup success command through the external communication bus, and ending.
In conclusion, the utility model provides a dual-core chip has realized program backup and recovery simply reliably through utilizing the inside Flash space of chip, has improved entire system's MTBF (mean time between failure), has improved the anti-interference recovery ability of whole embedded system.
In the present invention, the terms "connect", "connecting", and the like mean electrically connecting or communicating, and mean directly or indirectly electrically or communicating unless otherwise specified. As used herein, "coupled" refers to indirect or direct electrical connections, which may be through one or more electrical devices (e.g., resistors, capacitors, inductors, etc.).
The foregoing description has disclosed fully the embodiments of the present invention. It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not to be limited to the specific embodiments described above.

Claims (4)

1. A dual-core chip, comprising:
a first central processing unit CPU1, abbreviated CPU 1;
a second central processing unit CPU2, abbreviated CPU 2;
a first flash module operated by the first central processor CPU1, comprising a CPU1 boot loader region, a CPU1 application execution region, a CPU1 application staging region, and a CPU2 application backup region;
a second flash module operated by the second central processor CPU2, comprising a CPU2 boot loader region, a CPU2 application execution region, a CPU2 application staging region, and a CPU1 application backup region;
an internal communication bus for communication connection between the first CPU1 and the second CPU 2;
an external communication bus for the first CPU1 and the second CPU2 to communicate with the outside.
2. The dual core chip of claim 1,
the CPU1 boot loader area and the CPU2 boot loader area are respectively used for upgrading the corresponding CPUs;
the CPU1 application program execution area and the CPU2 application program execution area are respectively used for storing application programs actually run by the corresponding CPUs;
the CPU1 application program temporary storage area and the CPU2 application program temporary storage area are respectively used for storing programs to be upgraded of the corresponding CPUs;
the CPU1 application backup area is used for backing up complete CPU1 programs, and the CPU2 application backup area is used for backing up complete CPU2 programs; and/or.
3. The dual core chip of claim 1,
the first flash memory module is located inside the first central processing unit CPU 1;
the second flash memory module is located inside the second central processing unit CPU 2.
4. The dual core chip of any one of claims 1 to 3, wherein it is capable of program recovery,
the CPU1 is used for detecting whether the system is normal, if so, the detection is continued, otherwise, the CPU1 stops working;
the CPU1 is also used for informing the CPU2 to stop working after stopping working;
the CPU2 is configured to send the CPU1 program backed up in the CPU1 application backup area of the second flash memory module to the CPU 1;
the CPU1 is also configured to write the received CPU1 program to the CPU1 application staging area of the first flash module;
the CPU1 is also configured to perform program recovery based on the CPU1 program stored in the CPU1 application buffer of the first flash module.
CN202022194088.9U 2020-09-29 2020-09-29 Dual-core chip capable of performing program backup and recovery Active CN213751052U (en)

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