CN213748737U - Digital vibration sensor detection circuit - Google Patents
Digital vibration sensor detection circuit Download PDFInfo
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- CN213748737U CN213748737U CN202022969783.8U CN202022969783U CN213748737U CN 213748737 U CN213748737 U CN 213748737U CN 202022969783 U CN202022969783 U CN 202022969783U CN 213748737 U CN213748737 U CN 213748737U
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Abstract
The utility model discloses a digital vibration sensor detection circuit, the circuit includes CPU processing unit, SRAM buffer unit, vibration acquisition unit and transmission unit all are connected with CPU processing unit; the CPU processing unit comprises a processor U2, a key J2 and an emulator interface JTAG1, a resistor R3 is connected between a pin 14 and a pin 15 of the processor U2, the pin 14 of the processor U2 is further connected with one end of a resistor R1, the other end of the resistor R1 is connected with a + Vbat end, the pin 38 of the processor U2 is connected with the cathode of a light emitting diode D1, and the anode of the light emitting diode D1 is connected with one end of a resistor R5. The utility model discloses a to the collection of various vibration relevant data, then can extract vibration frequency spectrum, amplitude, primary harmonic, secondary harmonic after handling the analysis to data to reach vibration information, reduced vibration sensor's field operation requirement, the operation is convenient for the first hand.
Description
Technical Field
The utility model belongs to the technical field of the vibration sensor, in particular to digital vibration sensor detection circuitry.
Background
At present, there are many ways for a vibration sensor to measure vibration, but in summary, the following three principles are mostly adopted:
the mechanical measuring method comprises the following steps: converting the variable quantity of the engineering vibration into a mechanical signal, and then amplifying the mechanical signal by a mechanical system to measure and record, wherein common instruments comprise a lever type vibration meter and a Geiger vibration meter;
the optical measurement method comprises the following steps: converting the variable quantity of the engineering vibration into an optical signal, and displaying and recording the optical signal after the optical signal is amplified by an optical system;
the electrical measurement method comprises the following steps: the variable quantity of engineering vibration is converted into electric signal, and amplified by means of line and displayed and recorded, and the mechanical vibration quantity is converted into electric quantity, then the electric quantity is measured, and according to the correspondent relationship the vibration quantity can be known, so that it is the most extensive mode.
The sensors are analog quantity sensors, and vibration information can be obtained only by matching with corresponding equipment, so that the operation is inconvenient.
Therefore, a digital vibration sensor detection circuit is needed to solve the above-mentioned technical problems.
SUMMERY OF THE UTILITY MODEL
To the above problem, the utility model provides a digital vibration sensor detection circuitry to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme: a digital vibration sensor detection circuit comprises a CPU processing unit, an SRAM cache unit, a vibration acquisition unit and a transmission unit, wherein the SRAM cache unit, the vibration acquisition unit and the transmission unit are all connected with the CPU processing unit;
the CPU processing unit comprises a processor U2, a key J2, an emulator interface JTAG1 and a power supply decoupling capacitor, a resistor R3 is connected between a pin 14 and a pin 15 of the processor U2, the pin 14 of the processor U2 is also connected with one end of a resistor R1, the other end of the resistor R1 is connected with a + Vbat end, a pin 38 of the processor U2 is connected with the negative electrode of a light emitting diode D1, the positive electrode of the light emitting diode D1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a +3.3V power supply end, a pin 2 of the processor U2 is connected with a pin 2 of the key J2, a capacitor C6 is connected between the pin 1 and the pin 2 of the key J2, one end of the capacitor C6 is connected with the pin 1 of the key J2 and is grounded, a crystal oscillator Y1 is connected between the pin 3 and the pin 4 of the processor U2, one end of the crystal oscillator Y1 is connected with one end of a capacitor C11, and one end of the crystal oscillator Y12 is connected with the other end of the capacitor C12, the other end of the capacitor C11 and the other end of the capacitor C12 are both grounded, a pin 7 of the processor U2 is respectively connected with one end of a capacitor C10 and one end of a resistor R12, the other end of the resistor R12 is connected with a +3.3V power supply end, the other end of the capacitor C10 is grounded, and a pin 44 of the processor U2 is grounded;
the power decoupling capacitor comprises a capacitor C16, a capacitor C17 and a capacitor C18, wherein one end of the capacitor C16, one end of the capacitor C17 and one end of the capacitor C18 are respectively connected with a pin 1, a pin 9, a pin 24, a pin 36 and a pin 48 of a processor U2 and are connected with a +3.3V power supply end, and the other end of the capacitor C16, the other end of the capacitor C17 and the other end of the capacitor C18 are respectively connected with a pin 8, a pin 23, a pin 35 and a pin 47 of the processor U2 and are grounded.
Further, the SRAM buffer unit includes a buffer U3, pin 1 of the buffer U3 is connected to pin 22 of processor U2, pin 2 of the buffer U3 is connected to pin 18 of processor U2, pin 3 of the buffer U3 is connected to pin 17 of processor U2, pin 4 of the buffer U3 is grounded, pin 5 of the buffer U3 is connected to pin 19 of processor U2, pin 6 of the buffer U3 is connected to pin 21 of processor U2, pin 7 of the buffer U3 is connected to pin 16 of processor U2, pin 8 of the buffer U3 is connected to +3.3V power supply terminal and one end of capacitor C5, and the other end of the capacitor C5 is grounded.
Further, the vibration acquisition unit comprises an acquisition device U4, a pin 8 of the acquisition device U4 is connected to a +3.3V power supply terminal and one end of a capacitor C9, the other end of the capacitor C9 is grounded, a pin 9 of the acquisition device U4 is connected to a pin 27 of a processor U2, a pin 10 of the acquisition device U4 is connected to one end of a capacitor C8, the other end of the capacitor C8 is grounded, a pin 11 of the acquisition device U4 is connected to a pin 33 of the processor U2, a pin 12 of the acquisition device U4 is connected to a pin 32 of the processor U2, a pin 13 of the acquisition device U4 is connected to a +3.3V power supply terminal and one end of a capacitor C7, the other end of the capacitor C7 is grounded, and a pin 18 of the acquisition device U4 is grounded.
Furthermore, a pin 19, a pin 20, and a pin 25 of the collector U4 are all grounded, a pin 22 of the collector U4 is connected to a pin 25 of the processor U2, a pin 23 of the collector U4 is connected to a pin 26 of the processor U2, and a pin 24 of the collector U4 is connected to a pin 28 of the processor U2.
Further, the transmission unit includes a chip U5, pin 1 of the chip U5 is connected with pin 31 of the processor U2, pin 2 and pin 3 of the chip U5 are connected with one end of a resistor R1, the other end of the resistor R1 is connected with a +3.3V power supply end, pin 2 and pin 3 of the chip U5 are also connected with pin 3 of the triode Q1, pin 4 of the chip U5 is connected with pin 30 of the processor U2 and one end of the resistor R3, the other end of the resistor R3 is connected with pin 1 of the triode Q1, and pin 2 of the triode Q1 is grounded.
Further, the pin 5 of the chip U5 is grounded, the pin 6 of the chip U5 is connected to the pin 2 of the shorting cap J1, one end of the resistor RT5 and one end of the resistor RT4 respectively, the other end of the resistor RT5 is connected to the +3.3V power supply terminal, the other end of the resistor RT4 is connected to the negative electrode of the schottky diode DT3 and the negative electrode of the schottky diode DT2 respectively, the positive electrode of the schottky diode DT3 is grounded, the pin 7 of the chip U5 is connected to one end of the resistor RT3, one end of the resistor RT1 and one end of the resistor RT2 respectively, the other end of the resistor RT3 is connected to the pin 1 of the shorting cap J1, the other end of the resistor RT1 is grounded, the other end of the resistor RT2 is connected to the positive electrode of the schottky diode DT2 and the positive electrode of the schottky diode DT1 respectively, the negative electrode of the schottky diode DT1 is grounded, the other ends of the resistor RT2 and the resistor 4 are connected to the external collection terminal, the pin 8 of the chip U5 is connected to the +3.3V power supply terminal and the capacitor C4 respectively, the other end of the capacitor C4 is grounded.
The utility model discloses a technological effect and advantage:
the utility model discloses a to the collection of various vibration relevant data, then can extract vibration frequency spectrum, amplitude, primary harmonic, secondary harmonic after handling the analysis to data to reach vibration information, do not need supporting corresponding equipment, reduced vibration sensor's field usage requirement, the operation is convenient for the first hand.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 shows a schematic wiring diagram of part U2A of a processor U2 according to an embodiment of the present invention;
fig. 2 shows a schematic wiring diagram of part U2B of a processor U2 according to an embodiment of the present invention;
fig. 3 shows a wiring diagram of an emulator interface JTAG1 according to an embodiment of the present invention;
fig. 4 shows a power supply decoupling capacitance circuit diagram of processor U2 of an embodiment of the present invention;
fig. 5 shows a schematic wiring diagram of a buffer U3 according to an embodiment of the present invention;
fig. 6 shows a schematic wiring diagram of collector U4 according to an embodiment of the present invention;
fig. 7 shows a wiring diagram of the chip U5 according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides a digital vibration sensor detection circuit, exemplarily, as shown in FIGS. 1-7, the circuit includes a CPU processing unit, an SRAM cache unit, a vibration acquisition unit and a transmission unit, the SRAM cache unit, the vibration acquisition unit and the transmission unit are all connected with the CPU processing unit;
the CPU processing unit comprises a processor U2, a key J2, an emulator interface JTAG1 and a power supply decoupling capacitor, a resistor R3 is connected between a pin 14 and a pin 15 of the processor U2, the pin 14 of the processor U2 is also connected with one end of a resistor R1, the other end of the resistor R1 is connected with a + Vbat end, a pin 38 of the processor U2 is connected with the negative electrode of a light emitting diode D1, the positive electrode of the light emitting diode D1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a +3.3V power supply end, a pin 2 of the processor U2 is connected with a pin 2 of the key J2, a capacitor C6 is connected between the pin 1 and the pin 2 of the key J2, one end of the capacitor C6 is connected with the pin 1 of the key J2 and is grounded, a crystal oscillator Y1 is connected between the pin 3 and the pin 4 of the processor U2, one end of the crystal oscillator Y1 is connected with one end of a capacitor C11, and one end of the crystal oscillator Y12 is connected with the other end of the capacitor C12, the other end of the capacitor C11 and the other end of the capacitor C12 are both grounded, a pin 7 of the processor U2 is respectively connected with one end of a capacitor C10 and one end of a resistor R12, the other end of the resistor R12 is connected with a +3.3V power supply end, the other end of the capacitor C10 is grounded, and a pin 44 of the processor U2 is grounded;
the power decoupling capacitor comprises a capacitor C16, a capacitor C17 and a capacitor C18, wherein one end of the capacitor C16, one end of the capacitor C17 and one end of the capacitor C18 are respectively connected with a pin 1, a pin 9, a pin 24, a pin 36 and a pin 48 of a processor U2 and are connected with a +3.3V power supply end, and the other end of the capacitor C16, the other end of the capacitor C17 and the other end of the capacitor C18 are respectively connected with a pin 8, a pin 23, a pin 35 and a pin 47 of the processor U2 and are grounded.
The SRAM cache unit comprises a buffer U3, a pin 1 of the buffer U3 is connected with a pin 22 of a processor U2, a pin 2 of the buffer U3 is connected with a pin 18 of a processor U2, a pin 3 of the buffer U3 is connected with a pin 17 of a processor U2, a pin 4 of the buffer U3 is grounded, a pin 5 of the buffer U3 is connected with a pin 19 of a processor U2, a pin 6 of the buffer U3 is connected with a pin 21 of a processor U2, a pin 7 of the buffer U3 is connected with a pin 16 of a processor U2, a pin 8 of the buffer U3 is respectively connected with a +3.3V power supply terminal and one end of a capacitor C5, and the other end of the capacitor C5 is grounded.
The vibration acquisition unit comprises an acquisition device U4, a pin 8 of an acquisition device U4 is respectively connected with a +3.3V power supply end and one end of a capacitor C9, the other end of the capacitor C9 is grounded, a pin 9 of the acquisition device U4 is connected with a pin 27 of a processor U2, a pin 10 of an acquisition device U4 is connected with one end of a capacitor C8, the other end of the capacitor C8 is grounded, a pin 11 of an acquisition device U4 is connected with a pin 33 of the processor U2, a pin 12 of an acquisition device U4 is connected with a pin 32 of the processor U2, a pin 13 of an acquisition device U4 is respectively connected with a +3.3V power supply end and one end of a capacitor C7, the other end of the capacitor C7 is grounded, and a pin 18 of the acquisition device U4 is grounded.
The transmission unit comprises a chip U5, a pin 1 of the chip U5 is connected with a pin 31 of a processor U2, a pin 2 and a pin 3 of the chip U5 are connected with one end of a resistor R1, the other end of the resistor R1 is connected with a +3.3V power supply end, the pin 2 and the pin 3 of the chip U5 are further connected with a pin 3 of a triode Q1, a pin 4 of the chip U5 is respectively connected with one end of a pin 30 of a processor U2 and one end of a resistor R3, the other end of the resistor R3 is connected with a pin 1 of the triode Q1, and a pin 2 of the triode Q1 is grounded.
The pin 5 of the chip U5 is grounded, the pin 6 of the chip U5 is respectively connected with the pin 2 of the shorting cap J1, one end of a resistor RT5 and one end of a resistor RT4, the other end of the resistor RT5 is connected with a +3.3V power supply terminal, the other end of the resistor RT4 is respectively connected with the cathode of a Schottky diode DT3 and the cathode of a Schottky diode DT2, the anode of the Schottky diode DT3 is grounded, the pin 7 of the chip U5 is respectively connected with one end of a resistor RT3, one end of a resistor RT1 and one end of a resistor RT2, the other end of the resistor RT3 is connected with the pin 1 of the shorting cap J1, the other end of the resistor RT1 is grounded, the other end of the resistor RT2 is respectively connected with the anode of a Schottky diode DT2 and the anode of a Schottky diode DT1, the cathode of the Schottky diode DT1 is grounded, the cathode of the resistor RT2 and the other end of the resistor RT4 are both connected with an external collection terminal, the pin 8 of the chip U5 is respectively connected with one end of the + 3V power supply terminal and the capacitor C4, the other end of the capacitor C4 is grounded.
The embodiment of the utility model provides an in, STM32L431CBT6 is adopted to the model of treater U2, and the highest frequency can reach 80MHz, is the ultra low power dissipation treater that has ARM Cortex into M4 kernel that has DSP and Floating Point Unit (FPU). The processor U2 controls the light emitting diode D1 to indicate the running state of the system through the PA15, sets the system to enter a configuration program through a key J2, configures the system entries, and the simulator interface JTAG1 is connected with the PA13 and the PA14 of the processor U2 to simulate and program the system entries.
In the embodiment of the present invention, the model of the buffer U3 adopts LY68L6400SLIT, and PB0, PB1, PB10, PB11, PA6, PA7 through Quad SPI interface and processor U2 are connected.
The embodiment of the utility model provides an in, MPU6500 is adopted to collector U4's model, PB12 through SPI interface and treater U2, PB13, PB14, PB15 links to each other.
The embodiment of the utility model provides an in, MAX1487 is adopted to chip U5's model, all has a driver and a receiver in every device of this chip, but the maximum reduction heat dissipation of low-power consumption, reduce system cost to improve system reliability. The chip U5 is connected with PA9 and PA10 of the processor U2 through pins 1 and 4, and controls a triode Q1 (8050) through pin 4, so that the communication direction is controlled, the short circuit cap J1 is used for selecting whether a 120 ohm sampling resistor is adopted, and two communication lines for externally outputting A, B are connected with an external acquisition end, so that the communication function is realized.
The embodiment of the utility model provides a under CPU processing unit's the leading, through the collection of vibration acquisition unit entry acceleration and angular velocity, save SRAM buffer unit. And after one-minute uninterrupted acquisition, calculating a vibration frequency spectrum, an amplitude, a first harmonic wave, a second harmonic wave and the like through correlation operation, and finally outputting related data through a transmission unit.
The utility model discloses a to the collection of various vibration relevant data, then can extract vibration frequency spectrum, amplitude, primary harmonic, secondary harmonic after handling the analysis to data to reach vibration information, do not need supporting corresponding equipment, reduced vibration sensor's field usage requirement, the operation is convenient for the first hand.
Although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (6)
1. A digital vibration sensor detection circuit is characterized by comprising a CPU (central processing unit), an SRAM (static random access memory) cache unit, a vibration acquisition unit and a transmission unit, wherein the SRAM cache unit, the vibration acquisition unit and the transmission unit are all connected with the CPU;
the CPU processing unit comprises a processor U2, a key J2, an emulator interface JTAG1 and a power supply decoupling capacitor, a resistor R3 is connected between a pin 14 and a pin 15 of the processor U2, the pin 14 of the processor U2 is also connected with one end of a resistor R1, the other end of the resistor R1 is connected with a + Vbat end, a pin 38 of the processor U2 is connected with the negative electrode of a light emitting diode D1, the positive electrode of the light emitting diode D1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a +3.3V power supply end, a pin 2 of the processor U2 is connected with a pin 2 of the key J2, a capacitor C6 is connected between the pin 1 and the pin 2 of the key J2, one end of the capacitor C6 is connected with the pin 1 of the key J2 and is grounded, a crystal oscillator Y1 is connected between the pin 3 and the pin 4 of the processor U2, one end of the crystal oscillator Y1 is connected with one end of a capacitor C11, and one end of the crystal oscillator Y12 is connected with the other end of the capacitor C12, the other end of the capacitor C11 and the other end of the capacitor C12 are both grounded, a pin 7 of the processor U2 is respectively connected with one end of a capacitor C10 and one end of a resistor R12, the other end of the resistor R12 is connected with a +3.3V power supply end, the other end of the capacitor C10 is grounded, and a pin 44 of the processor U2 is grounded;
pin 1, pin 24, pin 36, pin 48 and pin 9 of the processor U2 are all connected to a +3.3V power supply terminal, and pin 8, pin 47, pin 35 and pin 23 of the processor U2 are all grounded;
pin 1 of the emulator interface JTAG1 is connected to the + Vbat terminal, pin 2 of the emulator interface JTAG1 is connected to pin 34 of the U2 of the processor, pin 3 of the emulator interface JTAG1 is grounded, and pin 4 of the emulator interface JTAG1 is connected to pin 37 of the U2 of the processor;
the power decoupling capacitor comprises a capacitor C16, a capacitor C17 and a capacitor C18, wherein one end of the capacitor C16, one end of the capacitor C17 and one end of the capacitor C18 are respectively connected with a pin 1, a pin 9, a pin 24, a pin 36 and a pin 48 of a processor U2 and are connected with a +3.3V power supply end, and the other end of the capacitor C16, the other end of the capacitor C17 and the other end of the capacitor C18 are respectively connected with a pin 8, a pin 23, a pin 35 and a pin 47 of the processor U2 and are grounded.
2. The digital vibration sensor detection circuit according to claim 1, wherein the SRAM buffer unit comprises a buffer U3, pin 1 of the buffer U3 is connected to pin 22 of processor U2, pin 2 of the buffer U3 is connected to pin 18 of processor U2, pin 3 of the buffer U3 is connected to pin 17 of processor U2, pin 4 of the buffer U3 is grounded, pin 5 of the buffer U3 is connected to pin 19 of processor U2, pin 6 of the buffer U3 is connected to pin 21 of processor U2, pin 7 of the buffer U3 is connected to pin 16 of processor U2, pin 8 of the buffer U3 is connected to +3.3V power supply terminal and one terminal of a capacitor C5, and the other terminal of the capacitor C5 is grounded.
3. The digital vibration sensor detection circuit according to claim 1, wherein the vibration acquisition unit comprises an acquisition device U4, a pin 8 of the acquisition device U4 is connected to +3.3V power supply terminal and one end of a capacitor C9, the other end of the capacitor C9 is grounded, a pin 9 of the acquisition device U4 is connected to a pin 27 of a processor U2, a pin 10 of the acquisition device U4 is connected to one end of a capacitor C8, the other end of the capacitor C8 is grounded, a pin 11 of the acquisition device U4 is connected to a pin 33 of the processor U2, a pin 12 of the acquisition device U4 is connected to a pin 32 of the processor U2, a pin 13 of the acquisition device U4 is connected to +3.3V power supply terminal and one end of a capacitor C7, the other end of the capacitor C7 is grounded, and a pin 18 of the acquisition device U4 is grounded.
4. The digital vibration sensor detecting circuit according to claim 3, wherein the pin 19, the pin 20 and the pin 25 of the collector U4 are all grounded, the pin 22 of the collector U4 is connected with the pin 25 of the processor U2, the pin 23 of the collector U4 is connected with the pin 26 of the processor U2, and the pin 24 of the collector U4 is connected with the pin 28 of the processor U2.
5. The digital vibration sensor detection circuit according to claim 1, wherein the transmission unit comprises a chip U5, pin 1 of the chip U5 is connected with pin 31 of a processor U2, pin 2 and pin 3 of the chip U5 are connected with one end of a resistor R1, the other end of the resistor R1 is connected with a +3.3V power supply terminal, pin 2 and pin 3 of the chip U5 are also connected with pin 3 of a transistor Q1, pin 4 of the chip U5 is respectively connected with pin 30 of a processor U2 and one end of a resistor R3, the other end of the resistor R3 is connected with pin 1 of the transistor Q1, and pin 2 of the transistor Q1 is grounded.
6. The digital vibration sensor detecting circuit according to claim 5, wherein the pin 5 of the chip U5 is grounded, the pin 6 of the chip U5 is connected to the pin 2 of the shorting cap J1, one end of the resistor RT5 and one end of the resistor RT4 respectively, the other end of the resistor RT5 is connected to the +3.3V power supply terminal, the other end of the resistor RT4 is connected to the cathode of the Schottky diode DT3 and the cathode of the Schottky diode DT2 respectively, the anode of the Schottky diode DT3 is grounded, the pin 7 of the chip U5 is connected to the one end of the resistor RT3, one end of the resistor RT1 and one end of the resistor RT2 respectively, the other end of the resistor RT3 is connected to the pin 1 of the shorting cap J1, the other end of the resistor RT1 is grounded, the other end of the resistor RT2 is connected to the anode of the Schottky diode 2 and the anode of the Schottky diode 96 1 respectively, the cathode of the Schottky diode DT1 is grounded, the other end of the resistor RT2 and the other end of the resistor RT4 are connected to the external collecting terminal, and a pin 8 of the chip U5 is respectively connected with a +3.3V power supply end and one end of a capacitor C4, and the other end of the capacitor C4 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022969783.8U CN213748737U (en) | 2020-12-13 | 2020-12-13 | Digital vibration sensor detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022969783.8U CN213748737U (en) | 2020-12-13 | 2020-12-13 | Digital vibration sensor detection circuit |
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| CN213748737U true CN213748737U (en) | 2021-07-20 |
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