CN213693148U - Novel radar sensor timesharing power saving circuit - Google Patents
Novel radar sensor timesharing power saving circuit Download PDFInfo
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- CN213693148U CN213693148U CN202022986059.6U CN202022986059U CN213693148U CN 213693148 U CN213693148 U CN 213693148U CN 202022986059 U CN202022986059 U CN 202022986059U CN 213693148 U CN213693148 U CN 213693148U
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Abstract
The utility model discloses a novel radar sensor timesharing power saving circuit for thereby avoid radar chip to start consuming time overlength and realize the power saving, including master control circuit, radar chip circuit, intermediate frequency voltage holding circuit and intermediate frequency circuit, master control circuit respectively with radar chip circuit and intermediate frequency circuit electric connection, radar chip circuit pass through master control circuit's first field effect transistor Q1 and radar power supply electric connection, radar chip circuit still passes through intermediate frequency voltage holding circuit's second field effect transistor Q2 and third field effect transistor Q3 respectively with intermediate frequency circuit electric connection. The utility model discloses a novel radar sensor timesharing power saving circuit, its power break-make and the radar output voltage who controls the radar chip respectively through three MOS pipe keep, and it switches different circuit states through analog switch, avoids radar system to start overlength consuming time, realizes the power saving purpose.
Description
Technical Field
The utility model belongs to the technical field of radar sensor timesharing power saving, concretely relates to novel radar sensor timesharing power saving circuit.
Background
The 24GHz radar sensor has a certain market in the application of the Internet of things, and has more applications in the aspects of intelligent home, intelligent transportation, intelligent electricity and the like. However, the operating power consumption of 24GHz is relatively large, and in a 5V environment, an operating current of about 50mA is generally available. The purpose of power saving can be achieved by enabling the radar chip to work in a time-sharing mode, however, the starting time of the radar circuit is slow, so that the time for turning off and starting the radar is long, and the requirement for power saving cannot be met.
In the starting process of the radar, devices such as an operational amplifier in the intermediate frequency amplifying circuit bring larger starting time delay, which is a main reason for causing the starting time to be too slow, and the stable state of the circuit can be reached only by waiting for hundreds of milliseconds. The output voltage of the radar chip has the greatest influence, the signal output can jump from 0 volt to 1.6 volts when the radar chip is switched on from off, the jump can lead to the complete saturation of a following intermediate frequency amplifying circuit, and the stable state can be recovered after hundreds of milliseconds, so that the problems of long consumed time and power waste of the radar system are caused.
SUMMERY OF THE UTILITY MODEL
A primary object of the utility model is to provide a novel radar sensor timesharing power saving circuit, its power break-make and the radar output voltage who controls the radar chip respectively through three MOS pipe keep, and it switches different circuit states through analog switch, avoids radar system to start overlength consuming time, realizes the power saving purpose to through the switch switching, the static direct current level of maintaining the circuit is in stable state, avoids starting the problem of consuming time length.
In order to achieve the above object, the utility model provides a novel radar sensor timesharing power saving circuit for thereby avoid radar chip to start consuming time overlength and realize the power saving, including master control circuit, radar chip circuit, intermediate frequency voltage holding circuit and intermediate frequency circuit, master control circuit respectively with radar chip circuit and intermediate frequency circuit electric connection, wherein:
the radar chip circuit is electrically connected with a radar power supply through a first field-effect tube Q1 of the master control circuit, and is also electrically connected with the intermediate frequency circuit through a second field-effect tube Q2 and a third field-effect tube Q3 (two channels) of the intermediate frequency voltage maintaining circuit respectively;
when the first field effect tube Q1 is closed and the radar power supply supplies power to a radar chip U2 of the radar chip circuit, the second field effect tube Q2 and the third field effect tube Q3 are closed, the radar chip circuit is conducted with the intermediate frequency circuit, and the radar chip circuit outputs an analog signal to the intermediate frequency circuit;
when the first field effect transistor Q1 is disconnected and the radar power supply does not supply power to the radar chip U2 of the radar chip circuit, the second field effect transistor Q2 and the third field effect transistor Q3 are disconnected and supply power to the intermediate frequency circuit through the intermediate frequency maintaining fixed voltage of the intermediate frequency voltage maintaining circuit;
the first field effect transistor Q1, the second field effect transistor Q2 and the third field effect transistor Q3 are used for switching so as to replace different circuit states, and the static direct current level of the intermediate frequency circuit is in a stable state.
As a further preferable technical solution of the above technical solution, one path of the gate of the second field effect transistor Q2 is grounded through a resistor R43, the other path of the gate of the second field effect transistor Q2 is connected to a power supply through a resistor R42, and the drain of the second field effect transistor Q2 is grounded through a resistor R40 and a resistor R41 in sequence;
one path of the grid of the third field effect transistor Q3 is grounded through a resistor R47, the other path of the grid of the third field effect transistor Q3 is connected with a power supply through a resistor R46, and the drain of the third field effect transistor Q3 is grounded through a resistor R44 and a resistor R45 in sequence.
As a further preferable technical solution of the above technical solution, the intermediate frequency circuit includes an operational amplifier U3, one path of the positive input terminal of the operational amplifier U3 is electrically connected to the IFQ terminal of the radar chip U2 through a resistor R49 (output signal), and the other path of the positive input terminal of the operational amplifier U3 is electrically connected to the common terminal of the resistor R40 and the resistor R41 (so that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U3 is grounded through a resistor R4 and a capacitor C7 in sequence, a resistor R3 is connected between the negative input end and the output end of the operational amplifier U3 in series, and two ends of the resistor R3 are connected with a capacitor C5 in parallel.
As a further preferable technical solution of the above technical solution, the intermediate frequency circuit includes an operational amplifier U4, one path of the positive input terminal of the operational amplifier U4 is electrically connected to the IFI end of the radar chip U2 through a resistor R48 (output signal), and the other path of the positive input terminal of the operational amplifier U4 is electrically connected to the common terminal of the resistor R44 and the resistor R45 (so that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U4 is grounded through a resistor R9 and a capacitor C10 in sequence, a resistor R8 is connected between the negative input end and the output end of the operational amplifier U4 in series, and two ends of the resistor R8 are connected with a capacitor C8 in parallel.
As a further preferable technical solution of the above technical solution, the RX end of the radar chip U2 is electrically connected to the antenna ANT2, and the TX end of the radar chip U2 is electrically connected to the antenna ANT 1.
As a further preferable technical solution of the above technical solution, the main control circuit includes a processor U4, a pin 10 of the processor U4 is electrically connected to a gate of the first fet Q1, one path of the gate of the first fet Q1 is grounded through a resistor R22, a resistor R15 is connected in series between the gate and the source of the first fet Q1, a resistor R21 is connected in series between the source and the drain of the first fet Q1, and one end of the resistor R21 close to the first fet Q1 is grounded through a capacitor C20.
As a further preferable technical solution of the above technical solution, the pin 6 of the processor U4 is electrically connected to the output terminal of the operational amplifier U3 through a resistor R5, and the pin 7 of the processor U4 is electrically connected to the output terminal of the operational amplifier U4 through a resistor R10.
Drawings
Fig. 1 is the utility model discloses a novel radar sensor timesharing power saving circuit's radar chip power saving state schematic diagram.
Fig. 2 is the utility model discloses a novel radar sensor timesharing power saving circuit's radar chip operating condition schematic diagram.
Fig. 3 is a circuit diagram for maintaining the intermediate frequency voltage of the novel radar sensor time-sharing power saving circuit of the present invention.
Fig. 4 is a circuit diagram of a radar chip of a novel radar sensor time-sharing power-saving circuit of the present invention.
Fig. 5 is an intermediate frequency circuit diagram of a novel radar sensor time-sharing power-saving circuit of the present invention.
Fig. 6 is a main control circuit diagram of a novel radar sensor time-sharing power-saving circuit of the present invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.
In the preferred embodiments of the present invention, it should be noted by those skilled in the art that the antenna, the resistor, and the like according to the present invention can be regarded as the prior art.
A first embodiment.
The utility model discloses a novel radar sensor timesharing power saving circuit for thereby avoid radar chip to start consuming time overlength and realize the power saving, including master control circuit, radar chip circuit, intermediate frequency voltage holding circuit and intermediate frequency circuit, master control circuit respectively with radar chip circuit and intermediate frequency circuit electric connection, wherein:
the radar chip circuit is electrically connected with a radar power supply through a first field-effect tube Q1 of the master control circuit, and is also electrically connected with the intermediate frequency circuit through a second field-effect tube Q2 and a third field-effect tube Q3 (two channels) of the intermediate frequency voltage maintaining circuit respectively;
when the first field-effect tube Q1 is closed and a radar power supply supplies power to a radar chip U2 (a 24GHz single-chip full-integrated millimeter wave radar sensor chip) of the radar chip circuit, the second field-effect tube Q2 and the third field-effect tube Q3 are closed, the radar chip circuit is conducted with the intermediate frequency circuit, and the radar chip circuit outputs an analog signal to the intermediate frequency circuit;
when the first field effect tube Q1 is disconnected and the radar power supply does not supply power to the radar chip U2 of the radar chip circuit, the second field effect tube Q2 and the third field effect tube Q3 are disconnected (the intermediate frequency voltage maintaining circuit is electrically connected with the intermediate frequency circuit), and the intermediate frequency circuit is supplied with power by the intermediate frequency maintaining fixed voltage of the intermediate frequency voltage maintaining circuit;
the first field effect transistor Q1, the second field effect transistor Q2 and the third field effect transistor Q3 are used for switching to replace different circuit states (the radar system is prevented from consuming too long time to achieve the purpose of saving electricity), and the static direct current level of the intermediate frequency circuit is in a stable state (the problem of consuming long time to start is avoided).
Specifically, one path of the gate of the second fet Q2 is grounded through a resistor R43, the other path of the gate of the second fet Q2 is connected to a power supply (VCC33) through a resistor R42, and the drain of the second fet Q2 is grounded through a resistor R40 and a resistor R41 in sequence;
one path of the grid of the third field effect transistor Q3 is grounded through a resistor R47, the other path of the grid of the third field effect transistor Q3 is connected with a power supply (VCC33) through a resistor R46, and the drain of the third field effect transistor Q3 is grounded through a resistor R44 and a resistor R45 in sequence.
More specifically, the intermediate frequency circuit includes an operational amplifier U3, one path of the positive input terminal of the operational amplifier U3 is electrically connected to the IFQ terminal of the radar chip U2 through a resistor R49 (output signal), and the other path of the positive input terminal of the operational amplifier U3 is electrically connected to the common terminal of the resistor R40 and the resistor R41 (so that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U3 is grounded through a resistor R4 and a capacitor C7 in sequence, a resistor R3 is connected between the negative input end and the output end of the operational amplifier U3 in series, and two ends of the resistor R3 are connected with a capacitor C5 in parallel.
Further, the intermediate frequency circuit includes an operational amplifier U4, one path of the positive input terminal of the operational amplifier U4 is electrically connected to the IFI terminal of the radar chip U2 through a resistor R48 (output signal), and the other path of the positive input terminal of the operational amplifier U4 is electrically connected to the common terminal of the resistor R44 and the resistor R45 (such that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U4 is grounded through a resistor R9 and a capacitor C10 in sequence, a resistor R8 is connected between the negative input end and the output end of the operational amplifier U4 in series, and two ends of the resistor R8 are connected with a capacitor C8 in parallel.
Furthermore, the RX end of the radar chip U2 is electrically connected to the antenna ANT2, and the TX end of the radar chip U2 is electrically connected to the antenna ANT 1.
Preferably, the main control circuit comprises a processor U4, a pin 10 of the processor U4 is electrically connected to a gate of the first fet Q1, one way of the gate of the first fet Q1 is grounded through a resistor R22, a resistor R15 is connected in series between the gate and the source of the first fet Q1, a resistor R21 is connected in series between the source and the drain of the first fet Q1, and one end of the resistor R21 close to the first fet Q1 is grounded through a capacitor C20.
Preferably, the 6 th pin of the processor U4 is electrically connected to the output terminal of the operational amplifier U3 through a resistor R5, and the 7 th pin of the processor U4 is electrically connected to the output terminal of the operational amplifier U4 through a resistor R10.
Preferably, when the radar is powered on and works, the intermediate frequency output of the radar chip U2 is directly connected to the intermediate frequency (amplifying) circuit, when the radar is powered off, the intermediate frequency output of the radar chip U2 is disconnected, the fixed voltage switched to the intermediate frequency voltage maintaining circuit is continuously supplied to the intermediate frequency circuit, when the radar is powered on and works again, the radar is switched back to directly provide signals for the intermediate frequency amplifying circuit, the two states are switched back and forth at high speed, the problem of overlong circuit state switching time is avoided, and the purpose of high-speed time sharing and power saving is achieved.
Preferably, the time-sharing power saving speed is high, and the time-sharing power saving requirement can be met. Adopt the utility model discloses preceding, the timesharing power saving can only accomplish speed that 1 second surveyed once, and the power saving is about 50%, can improve the speed that 10ms surveyed once after adopting this scheme, can reach power saving 90%.
A second embodiment.
The utility model discloses a novel radar sensor timesharing power saving circuit for thereby avoid radar chip to start consuming time overlength and realize the power saving, including master control circuit, radar chip circuit, intermediate frequency voltage holding circuit and intermediate frequency circuit, master control circuit respectively with radar chip circuit and intermediate frequency circuit electric connection, wherein:
the radar chip circuit is electrically connected with a radar power supply through a first field-effect tube Q1 of the master control circuit, and is also electrically connected with the intermediate frequency circuit through a second field-effect tube Q2 and a third field-effect tube Q3 (two channels) of the intermediate frequency voltage maintaining circuit respectively;
specifically, one path of the gate of the second fet Q2 is grounded through a resistor R43, the other path of the gate of the second fet Q2 is connected to a power supply (VCC33) through a resistor R42, and the drain of the second fet Q2 is grounded through a resistor R40 and a resistor R41 in sequence.
One path of the grid of the third field effect transistor Q3 is grounded through a resistor R47, the other path of the grid of the third field effect transistor Q3 is connected with a power supply (VCC33) through a resistor R46, and the drain of the third field effect transistor Q3 is grounded through a resistor R44 and a resistor R45 in sequence.
More specifically, the intermediate frequency circuit includes an operational amplifier U3, one path of the positive input terminal of the operational amplifier U3 is electrically connected to the IFQ terminal of the radar chip U2 through a resistor R49 (output signal), and the other path of the positive input terminal of the operational amplifier U3 is electrically connected to the common terminal of the resistor R40 and the resistor R41 (so that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U3 is grounded through a resistor R4 and a capacitor C7 in sequence, a resistor R3 is connected between the negative input end and the output end of the operational amplifier U3 in series, and two ends of the resistor R3 are connected with a capacitor C5 in parallel.
Further, the intermediate frequency circuit includes an operational amplifier U4, one path of the positive input terminal of the operational amplifier U4 is electrically connected to the IFI terminal of the radar chip U2 through a resistor R48 (output signal), and the other path of the positive input terminal of the operational amplifier U4 is electrically connected to the common terminal of the resistor R44 and the resistor R45 (such that the intermediate frequency circuit is electrically connected to the intermediate frequency voltage maintaining circuit);
the negative input end of the operational amplifier U4 is grounded through a resistor R9 and a capacitor C10 in sequence, a resistor R8 is connected between the negative input end and the output end of the operational amplifier U4 in series, and two ends of the resistor R8 are connected with a capacitor C8 in parallel.
Furthermore, the RX end of the radar chip U2 is electrically connected to the antenna ANT2, and the TX end of the radar chip U2 is electrically connected to the antenna ANT 1.
Preferably, the main control circuit comprises a processor U4, a pin 10 of the processor U4 is electrically connected to a gate of the first fet Q1, one way of the gate of the first fet Q1 is grounded through a resistor R22, a resistor R15 is connected in series between the gate and the source of the first fet Q1, a resistor R21 is connected in series between the source and the drain of the first fet Q1, and one end of the resistor R21 close to the first fet Q1 is grounded through a capacitor C20.
Preferably, the 6 th pin of the processor U4 is electrically connected to the output terminal of the operational amplifier U3 through a resistor R5, and the 7 th pin of the processor U4 is electrically connected to the output terminal of the operational amplifier U4 through a resistor R10.
Preferably, when the radar is powered on and works, the intermediate frequency output of the radar chip U2 is directly connected to the intermediate frequency (amplifying) circuit, when the radar is powered off, the intermediate frequency output of the radar chip U2 is disconnected, the fixed voltage switched to the intermediate frequency voltage maintaining circuit is continuously supplied to the intermediate frequency circuit, when the radar is powered on and works again, the radar is switched back to directly provide signals for the intermediate frequency amplifying circuit, the two states are switched back and forth at high speed, the problem of overlong circuit state switching time is avoided, and the purpose of high-speed time sharing and power saving is achieved.
Preferably, the time-sharing power saving speed is high, and the time-sharing power saving requirement can be met. Adopt the utility model discloses preceding, the timesharing power saving can only accomplish speed that 1 second surveyed once, and the power saving is about 50%, can improve the speed that 10ms surveyed once after adopting this scheme, can reach power saving 90%.
It should be mentioned that the technical features such as the antenna and the resistor related to the present invention should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of these technical features may be selected conventionally in the field, which should not be regarded as the invention point of the present invention, and the present invention is not further specifically described in detail.
It will be apparent to those skilled in the art that modifications and variations can be made in the above-described embodiments, or some features of the invention may be substituted or omitted, and any modification, substitution, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. The utility model provides a novel radar sensor timesharing power saving circuit for thereby avoid radar chip to start consuming time overlength and realize the power saving, a serial communication port, including master control circuit, radar chip circuit, intermediate frequency voltage holding circuit and intermediate frequency circuit, master control circuit respectively with radar chip circuit and intermediate frequency circuit electric connection, wherein:
the radar chip circuit is electrically connected with a radar power supply through a first field-effect tube Q1 of the master control circuit, and is also electrically connected with the intermediate frequency circuit through a second field-effect tube Q2 and a third field-effect tube Q3 of the intermediate frequency voltage maintaining circuit respectively;
when the first field effect tube Q1 is closed and the radar power supply supplies power to a radar chip U2 of the radar chip circuit, the second field effect tube Q2 and the third field effect tube Q3 are closed, the radar chip circuit is conducted with the intermediate frequency circuit, and the radar chip circuit outputs an analog signal to the intermediate frequency circuit;
when the first field effect transistor Q1 is disconnected and the radar power supply does not supply power to the radar chip U2 of the radar chip circuit, the second field effect transistor Q2 and the third field effect transistor Q3 are disconnected and supply power to the intermediate frequency circuit through the intermediate frequency maintaining fixed voltage of the intermediate frequency voltage maintaining circuit;
the first field effect transistor Q1, the second field effect transistor Q2 and the third field effect transistor Q3 are used for switching so as to replace different circuit states, and the static direct current level of the intermediate frequency circuit is in a stable state.
2. The novel radar sensor time-sharing power-saving circuit as claimed in claim 1, wherein one path of the gate of the second fet Q2 is grounded through a resistor R43 and the other path of the gate of the second fet Q2 is connected to a power supply through a resistor R42, and the drain of the second fet Q2 is grounded through a resistor R40 and a resistor R41 in sequence;
one path of the grid of the third field effect transistor Q3 is grounded through a resistor R47, the other path of the grid of the third field effect transistor Q3 is connected with a power supply through a resistor R46, and the drain of the third field effect transistor Q3 is grounded through a resistor R44 and a resistor R45 in sequence.
3. The novel radar sensor time-sharing power saving circuit as claimed in claim 2, wherein the intermediate frequency circuit comprises an operational amplifier U3, one path of the positive input end of the operational amplifier U3 is electrically connected to the IFQ end of the radar chip U2 through a resistor R49, and the other path of the positive input end of the operational amplifier U3 is electrically connected to the common end of the resistor R40 and the resistor R41;
the negative input end of the operational amplifier U3 is grounded through a resistor R4 and a capacitor C7 in sequence, a resistor R3 is connected between the negative input end and the output end of the operational amplifier U3 in series, and two ends of the resistor R3 are connected with a capacitor C5 in parallel.
4. The novel radar sensor time-sharing power saving circuit as claimed in claim 3, wherein the intermediate frequency circuit comprises an operational amplifier U4, one path of the positive input end of the operational amplifier U4 is electrically connected with the IFI end of the radar chip U2 through a resistor R48, and the other path of the positive input end of the operational amplifier U4 is electrically connected with the common end of the resistor R44 and the resistor R45;
the negative input end of the operational amplifier U4 is grounded through a resistor R9 and a capacitor C10 in sequence, a resistor R8 is connected between the negative input end and the output end of the operational amplifier U4 in series, and two ends of the resistor R8 are connected with a capacitor C8 in parallel.
5. The novel time-sharing power-saving circuit for the radar sensor as claimed in claim 1, wherein the RX terminal of the radar chip U2 is electrically connected to an antenna ANT2, and the TX terminal of the radar chip U2 is electrically connected to an antenna ANT 1.
6. The novel radar sensor time-sharing power saving circuit as claimed in claim 4, wherein the master control circuit comprises a processor U4, the 10 pin of the processor U4 is electrically connected to the gate of the first fet Q1, one path of the gate of the first fet Q1 is grounded through a resistor R22, a resistor R15 is connected in series between the gate and the source of the first fet Q1, a resistor R21 is connected in series between the source and the drain of the first fet Q1, and one end of the resistor R21 close to the first fet Q1 is grounded through a capacitor C20.
7. The novel radar sensor time-sharing power-saving circuit as claimed in claim 6, wherein a pin 6 of the processor U4 is electrically connected to the output terminal of the operational amplifier U3 through a resistor R5, and a pin 7 of the processor U4 is electrically connected to the output terminal of the operational amplifier U4 through a resistor R10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022986059.6U CN213693148U (en) | 2020-12-09 | 2020-12-09 | Novel radar sensor timesharing power saving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022986059.6U CN213693148U (en) | 2020-12-09 | 2020-12-09 | Novel radar sensor timesharing power saving circuit |
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| Publication Number | Publication Date |
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| CN213693148U true CN213693148U (en) | 2021-07-13 |
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| CN202022986059.6U Active CN213693148U (en) | 2020-12-09 | 2020-12-09 | Novel radar sensor timesharing power saving circuit |
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