CN213692007U

CN213692007U - Packaging structure and electronic equipment

Info

Publication number: CN213692007U
Application number: CN202023206261.9U
Authority: CN
Inventors: 尹华钢
Original assignee: Qingdao Goertek Intelligent Sensor Co Ltd
Current assignee: Qingdao Goertek Intelligent Sensor Co Ltd
Priority date: 2020-12-25
Filing date: 2020-12-25
Publication date: 2021-07-13
Anticipated expiration: 2030-12-25

Abstract

The utility model discloses a packaging structure and electronic equipment, wherein, packaging structure includes first photoresist layer, first chip, first electrically conductive piece, first plastic envelope layer and second chip, first photoresist layer offers spaced first through-hole and mounting hole; the first chip is arranged in the mounting hole; the first conductive piece is arranged in the first through hole; the first plastic packaging layer covers the first chip and the upper surface of the first light resistance layer, and the first conductive piece is exposed; the second chip is arranged on the first plastic packaging layer and is electrically connected with the first conductive piece. The utility model discloses technical scheme's packaging structure can effectively simplify preparation technology.

Description

Packaging structure and electronic equipment

Technical Field

The utility model relates to an encapsulation technology field, in particular to packaging structure and electronic equipment.

Background

With the integration of electronic devices becoming higher and higher, chip stacking structures are increasingly produced to meet the trend of light, thin, short, small and diversified functions of electronic products. At present, in order to reduce the thickness of the package, a groove is formed in the front surface of a substrate, and a first chip is arranged in the groove in a flip-chip manner and electrically connected with the substrate; and arranging a second chip on the first chip, wherein the second chip is electrically connected with the substrate and packaged into a product. However, the process of forming the groove on the substrate is complicated, and a circuit layer needs to be designed for the first chip at the groove of the substrate, which increases the complexity of the substrate and the process cost.

SUMMERY OF THE UTILITY MODEL

The utility model mainly aims at providing a packaging structure aims at solving and piles up the technical problem that packaging structure preparation technology is complicated.

In order to achieve the above object, the present invention provides a package structure comprising:

the first light resistance layer is provided with a first through hole and a mounting hole which are spaced;

the first chip is arranged in the mounting hole;

the first conductive piece is arranged in the first through hole;

the first plastic packaging layer covers the first chip and the upper surface of the first light resistance layer, and the first conductive piece is exposed; and

and the second chip is arranged on the first plastic packaging layer and is electrically connected with the first conductive piece.

Optionally, a first pin is disposed on a surface of the second chip facing the first plastic package layer, the first pin corresponds to an outer peripheral edge of the mounting hole, and the first pin is electrically connected to the first conductive member.

Optionally, the first through holes are provided in plurality, the first through holes are annularly arranged on the periphery of the mounting hole, one first conductive piece is arranged in each first through hole, and the first pins are provided in plurality and are matched with the first conductive pieces.

Optionally, a protective film is plated on the outer surface of the first conductive member; and/or the first conductive piece is made of metal.

Optionally, the depth of the mounting hole is greater than or equal to the thickness of the first chip; and/or the presence of a gas in the gas,

the area of the opening of the mounting hole, which is far away from the first plastic packaging layer, is larger than or equal to the surface area of the first chip.

Optionally, an external solder ball is disposed on a surface of the first photoresist layer away from the second chip, and the external solder ball is electrically connected to the first conductive member and the first chip.

Optionally, the chip further comprises a second plastic package layer, and the second plastic package layer covers the upper surface and the side surface of the second chip.

Optionally, the package structure further includes:

the second light resistance layer is arranged on the first plastic packaging layer and is provided with an avoiding hole for avoiding the second chip, the second light resistance layer is also provided with a second through hole which is arranged at an interval with the avoiding hole, and the second through hole penetrates through the first light resistance layer;

the second conductive piece is arranged in the second through hole;

the second plastic packaging layer covers the second chip and the second light resistance layer and exposes the second conductive piece; and

and the third chip is arranged on the second plastic packaging layer and is electrically connected with the second conductive piece.

Optionally, the optical module further comprises a wiring layer, the wiring layer is arranged between the second plastic package layer and the third chip, a second pin is arranged on the surface of the third chip facing the second plastic package layer, and the projection of the second pin on the second photoresist layer is located in the avoiding hole; the wiring layer is electrically connected with the second conductive piece and the second pin.

The utility model also provides an electronic equipment, include the casing and locate packaging structure in the casing, packaging structure is as above packaging structure.

The utility model discloses packaging structure among the technical scheme includes first chip and second chip, and first chip and second chip superpose the setting in vertical direction, and will be used for the base plate of electricity connection to change into first light resistance layer, through deposit first light resistance layer on interim support plate, and can realize the setting of first through-hole and mounting hole through the photoetching, and the second chip can be through first electrically conductive piece with electric signal transmission to packaging structure's outside, packaging structure's processing procedure simple process can effectively reduce the cost of manufacture; and the first chip is not directly electrically connected with the outside through the substrate, so that the height of the packaging structure can be further reduced, and the miniaturization of a product is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a cross-sectional view of an embodiment of the package structure of the present invention;

FIG. 2 is a top view of a second chip in the package structure shown in FIG. 1;

fig. 3 is a cross-sectional view of another embodiment of the package structure of the present invention;

fig. 4 to fig. 11 are cross-sectional views of the package structure of the present invention during the processing.

The reference numbers illustrate:

100	packaging structure	70C	Third plastic packaging layer
				10	The first photoresist layer	80	Wiring layer
11	First through hole	81	Metal wire layer
				13	Mounting hole	83	Interlayer dielectric layer
20	External solder ball	90A	Second chip
				30	First chip	90B	Third chip
40	The second photoresist layer	91	First pin
				50	First conductive member	93	Second pin
60	The second conductive member	200	Temporary carrier plate
				70A	The first plastic packaging layer	400	High temperature glue line
70B	Second plastic packaging layer

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

In the present application, unless expressly stated or limited otherwise, the terms "connected" and "fixed" are to be construed broadly, e.g., "fixed" may be fixedly connected or detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In addition, descriptions in the present application as to "first", "second", and the like are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

The utility model provides a packaging structure 100.

Referring to fig. 1, in the embodiment of the present invention, the package structure 100 includes:

the device comprises a first light resistance layer 10, a second light resistance layer 10 and a third light resistance layer, wherein the first light resistance layer 10 is provided with a first through hole 11 and a mounting hole 13 which are spaced;

the first chip 30, the said first chip 30 locates in the said mounting hole 13;

a first conductive member 50, wherein the first conductive member 50 is disposed in the first through hole 11;

the first plastic package layer 70A covers the first chip 30 and the upper surface of the first photoresist layer 10, and exposes the first conductive member 50; and

and the second chip 90A is arranged on the first plastic package layer 70A, and is electrically connected with the first conductive member 50.

In this embodiment, the first chip 30 and the second chip 90A may be logic processing chips such as a processor, an FPGA (Field Programmable Gate Array), an MCU (micro controller Unit), or the like, may be memory chips such as a Flash and an EPROM, may be sensor chips, radio frequency chips, or the like, and are not limited herein. Specifically, the first photoresist layer 10 is made of a photoresist material, which is called a photoresist, and is a photosensitive material, and the solubility of the photoresist material can be changed under the illumination condition, so that various patterns can be formed, and the process is simple and convenient to implement. The first through hole 11 and the mounting hole 13 may be formed by a positive glue process and a negative glue process, and shapes of the two may be set according to actual requirements, for example, the chip is generally square, so the mounting hole 13 may be set to be square, the first conductive member 50 is columnar, and the opening of the first through hole 11 is circular, and of course, shapes of the mounting hole 13 and the first through hole 11 are not limited thereto. Since the package structure 100 is mainly used to realize the functions of each chip, the chip is generally mounted in the middle, and therefore the mounting hole 13 is disposed in the middle of the first photoresist layer 10, and the first through hole 11 is disposed at the periphery of the first photoresist layer 10.

It is understood that the first conductive member 50 is disposed in the first through hole 11 for transmitting the electrical signal of the second chip 90A to the bottom of the first photoresist layer 10, and the first photoresist layer 10 is installed in the applied product, thereby performing its function. Optionally, the first conductive member 50 is made of metal, such as copper, so that the cost is low, the structural stability and the conductivity are good, and the signal transmission stability of the second chip 90A is effectively ensured. Meanwhile, in order to further improve the transmission stability, in an embodiment, a protective film is plated on the outer surface of the first conductive member 50, and the protective film may be tin, gold, or the like, so that the conductivity of the protective film is better, and the electrical connection performance of the second chip 90A can be further improved; and can prevent oxidation of copper and improve structural stability and electrical properties of the first conductive member 50. The first molding compound layer 70A may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silica gel, or epoxy resin, and may be formed through a liquid-tight molding process, a vacuum lamination process, or a spin coating process, and the like, for fixing the first chip 30, and may effectively isolate the first chip 30 from the second chip 90A, prevent an electrical signal between the two from interfering, and improve the performance of the two.

The utility model discloses packaging structure 100 among the technical scheme includes first chip 30 and second chip 90A, first chip 30 and second chip 90A superpose in the vertical direction and set up, and will be used for the base plate of electricity connection to change into first light resistance layer 10, through deposit first light resistance layer 10 on interim support plate 200, and can realize the setting of first through-hole 11 and mounting hole 13 through the photoetching, second chip 90A can transmit the electric signal to the outside of packaging structure 100 through first electrically conductive piece 50, this packaging structure 100's processing procedure simple process, can effectively reduce the cost of manufacture; and the first chip 30 is not directly electrically connected to the outside through the substrate, so that the height of the package structure 100 can be further reduced, which is beneficial to product miniaturization.

Optionally, a surface of the second chip 90A facing the first molding compound layer 70A is provided with a first pin 91, the first pin 91 corresponds to an outer peripheral edge of the mounting hole 13, and the first pin 91 is electrically connected to the first conductive member 50.

In this embodiment, in order to facilitate connection between the second chip 90A and the first conductive member 50, a first pin 91 is disposed on a surface of the second chip 90A facing the first molding compound layer 70A, and the first pin 91 is an interface of the second chip 90A and is used for leading out an internal circuit of the second chip 90A to be electrically connected with an external circuit. Here, the surface area of the second chip 90A is larger than the surface area of the first chip 30, so that the first pins 91 are disposed corresponding to the outer periphery of the mounting hole 13, thereby facilitating the direct electrical connection of the first pins 91 with the first conductive member 50, simplifying the wiring process, and reducing the material cost. Optionally, the projection of the first pin 91 on the first photoresist layer 10 coincides with the first conductive member 50, so that the arrangement of the wiring layer 80 can be omitted, the processing process is further simplified, and the processing efficiency is improved.

Referring to fig. 2, optionally, a plurality of first through holes 11 are provided, the plurality of first through holes 11 are annularly provided on the periphery of the mounting hole 13, one first conductive member 50 is provided in one first through hole 11, and a plurality of first pins 91 are provided and adapted to the first conductive member 50.

In this embodiment, in order to improve the electrical connection stability, a plurality of first through holes 11 are provided, correspondingly, a plurality of first conductive members 50 are provided, and a plurality of first pins 91 are also provided, so that a one-to-one correspondence relationship between the plurality of first pins 91 and the plurality of first conductive members 50 is realized, and the electrical connection stability between the second chip 90A and the first conductive members 50 is improved. Meanwhile, the plurality of first through holes 11 are annularly arranged on the periphery of the mounting hole 13, so that the connection uniformity of the second chip 90A and the first conductive piece 50 can be improved, and the structural mounting stability of the second chip 90A can be ensured.

Optionally, the depth of the mounting hole 13 is greater than or equal to the thickness of the first chip 30; and/or the presence of a gas in the gas,

the opening area of the mounting hole 13 away from the first molding compound layer 70A is greater than or equal to the surface area of the first chip 30.

In this embodiment, when the first photoresist is subjected to photolithography, the longitudinal section of the formed mounting hole 13 is generally inverted trapezoid, so that, in order to facilitate mounting the first chip 30, the opening area of the mounting hole 13 away from the first plastic package layer 70A is set to be greater than or equal to the surface area of the first chip 30, so that the first chip 30 can be completely placed in the mounting hole 13, the first chip 30 is prevented from protruding out of the first photoresist layer 10 to increase the thickness of the package structure 100, and meanwhile, the surface of the first chip 30 departing from the first plastic package layer 70A is prevented from being flush with the surface of the first photoresist layer 10, thereby improving the convenience of electrical connection. Meanwhile, in order to facilitate the electrical connection between the second chip 90A and the first conductive member 50, the depth of the mounting hole 13 is set to be greater than or equal to the thickness of the first chip 30, so that the first chip 30 does not protrude out of the opening edge of the mounting hole 13, the thickness of the first molding compound layer 70A can be reduced, the length of the first conductive member 50 can be reduced, and the material cost can be saved.

Optionally, an external solder ball 20 is disposed on a surface of the first photoresist layer 10 facing away from the second chip 90A, and the external solder ball 20 is electrically connected to the first conductive member 50 and the first chip 30.

It can be understood that, in order to fix and electrically connect the package structure 100 to the inside of a desired product or a control board, the surface of the first photoresist layer 10 away from the second chip 90A is provided with a plurality of external solder balls 20, the external solder balls 20 are uniformly distributed on the lower surface of the first photoresist layer 10 at intervals, so as to improve the electrical connection uniformity of the package structure 100, because the first through holes 11 and the mounting holes 13 are holes penetrating through the first photoresist layer 10, the positions of the external solder balls 20 corresponding to the mounting holes 13 can be directly electrically connected to the first chip 30, and the positions corresponding to the first through holes 11 are directly electrically connected to the first conductive members 50, thereby facilitating the transmission of electrical signals.

Optionally, the chip package structure further includes a second molding compound layer 70B, and the second molding compound layer 70B covers the upper surface and the side surface of the second chip 90A.

In this embodiment, in order to improve the stability of the package structure 100, a second plastic package layer 70B is further disposed above the second chip 90A, the material and processing manner of the second plastic package layer 70B may be the same as those of the first plastic package layer 70A, and the second plastic package layer 70B covers the upper surface and the side surface of the second chip 90A, so that the second chip 90A may be stably fixed on the first plastic package layer 70A, and the second chip 90A is prevented from being disconnected from the first conductive member 50 due to shaking or dropping, thereby ensuring the stability of the structure and performance of the second chip 90A.

Referring to fig. 3, optionally, the package structure 100 further includes:

the second photoresist layer 40 is arranged on the first plastic package layer 70A, and is provided with an avoiding hole for avoiding the second chip 90A, the second photoresist layer 40 is also provided with a second through hole arranged at an interval with the avoiding hole, and the second through hole penetrates through the first photoresist layer 10;

a second conductive member 60, the second conductive member 60 being disposed in the second through hole;

a second plastic package layer 70B, where the second plastic package layer 70B covers the second chip 90A and the second photoresist layer 40, and exposes the second conductive member 60; and

and the third chip 90B is arranged on the second plastic package layer 70B, and is electrically connected with the second conductive member 60.

In this embodiment, the package structure 100 may further include a third chip 90B, and the third chip 90B is also stacked on the first chip 30 and the second chip 90A in the vertical direction, so as to realize the concentration of more functions, further reduce the occupied space of the chips, and improve the space utilization of the package structure 100. Specifically, in order to conveniently guide the electrical signal of the third chip 90B to the first photoresist layer 10, the second photoresist layer 40 is disposed on the first plastic package layer 70A, and the second photoresist layer 40 is made of the same material as the first photoresist layer 10 and has the same processing technology as the first photoresist layer 10, so that a second through hole and an avoiding hole can be conveniently formed, and the second through hole penetrates through the first photoresist layer 10, thereby avoiding the second chip 90A, facilitating the installation of the second conductive member 60, and realizing the transmission of the electrical signal of the third chip 90B to the first photoresist layer 10 through the second conductive member 60. Meanwhile, in order to stabilize the mounting of the second chip 90A, the second chip 90A and the second photoresist layer 40 are further covered with a second plastic package layer 70B, and the material and processing manner of the second plastic package layer 70B are the same as those of the first plastic package layer 70A, which is not described herein again. The second molding compound layer 70B can improve the structural stability of the second chip 90A, and can effectively isolate the second chip 90A from the third chip 90B to prevent signal interference therebetween. And the second plastic package layer 70B needs to expose the second conductive member 60, so that the position of the second plastic package layer 70B corresponding to the second through hole can be polished to be thinned, and the third chip 90B is conveniently electrically connected with the second conductive member 60.

Of course, the package structure 100 may further include a third molding compound layer 70C, so that the third chip 90B and the second molding compound layer 70B can be encapsulated, and the mounting stability of the third chip 90B is improved.

Optionally, the optical module further includes a wiring layer 80, the wiring layer 80 is disposed between the second plastic package layer 70B and the third chip 90B, a second pin 93 is disposed on a surface of the third chip 90B facing the second plastic package layer 70B, and a projection of the second pin 93 on the second photoresist layer 40 is located in the avoiding hole; the wiring layer 80 electrically connects the second conductive member 60 and the second pin 93.

In this embodiment, in order to facilitate connection between the third chip 90B and the second conductive member 60, the third chip 90B is provided with a second lead 93 facing the surface of the second molding compound layer 70B, and the second lead 93 and the first lead 91 are made of the same material. Here, the surface area of the third chip 90B is smaller than that of the second chip 90A, so that the projection of the second pin 93 on the second photoresist layer 40 is located in the avoiding hole, and the second through hole is formed at the outer periphery of the avoiding hole, so that a conductive line needs to be provided between the third chip 90B and the second conductive member 60, the wiring layer 80 is a conductive line for connecting the third chip 90B and the second conductive member 60, and is sandwiched between the second plastic package layer 70B and the third chip 90B, and may be formed by an additive method or a subtractive method, and the wiring layer 80 may be a single layer or may be provided with multiple layers.

Specifically, the wiring layer 80 includes a metal wire layer 81 and an interlayer dielectric layer 83, the metal wire layer 81 may be made of one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium, and has good conductivity and stable performance, the metal wire layer 81 may only include horizontal lines on a horizontal plane, or vertical lines and horizontal lines arranged in a staggered manner, and the setting is performed according to actual conditions, so that the electrical signal of the third chip 90B is led to the second conductive member 60 through the second pin 93. The interlayer dielectric layer 83 covers the metal line layer 81, and the material of the interlayer dielectric layer may include, but is not limited to, a low-K dielectric material, such as epoxy resin, silica gel, silicon oxide, or phosphosilicate glass, and may also be an organic insulating material such as PI (Polyimide), resin, and the like, and may be formed by spin coating, chemical vapor deposition, and the like, and may play a role in insulating and mechanically protecting the metal line layer 81.

Of course, in other embodiments, when the surface area of the third chip 90B is larger than the surface area of the second chip 90A, the wiring layer 80 does not need to be disposed, and the second pin 93 of the third chip 90B can be directly aligned with the position of the second conductive member 60 for electrical connection, so as to further simplify the manufacturing process.

Referring to fig. 4 to fig. 11, based on the package structure 100, the process steps for processing the package structure 100 of the present application include:

the method comprises the following steps: preparing a temporary carrier 200, and adhering a high-temperature adhesive layer 400 on the temporary carrier 200;

the material of the temporary carrier 200 may be glass, ceramic, polymer or silicon, etc., which provides a physical basis for the deposition of the first photoresist. The high-temperature adhesive in the high-temperature adhesive layer 400 is solid in low-temperature environment, has strong adhesion, can conveniently fix the first photoresist layer 10 and the first chip 30, disappears or weakens the adhesion in high-temperature environment, and can conveniently separate the temporary carrier plate 200 from the first photoresist layer 10.

Step two: attaching a first photoresist layer 10 on the high temperature adhesive layer 400, and forming spaced first through holes 11 and mounting holes 13 on the first photoresist layer 10;

the first photoresist layer 10 may be patterned by photolithography and development, and an insulator may be formed by ultraviolet irradiation, and the first photoresist layer 10 may be formed in a multiple-overlapping manner, so that a first through hole 11 having a larger depth-diameter ratio may be obtained, and the formed first through hole 11 and the mounting hole 13 both directly penetrate through the first photoresist layer 10. Because the mounting hole 13 formed by the photolithography method is generally in an inverted trapezoid shape, in order to facilitate the mounting and fixing of the first chip 30, the opening area of the mounting hole 13 close to the high temperature glue layer 400 is not smaller than the surface area of the first chip 30, thereby ensuring the quick and effective mounting of the first chip 30. The thickness of the first photoresist layer 10 is not less than that of the first chip 30, so as to facilitate the electrical connection between the second chip 90A and the first conductive member 50.

Step three: implanting a first conductive member 50 into the first through hole 11, placing the first chip 30 in the mounting hole 13 and attaching the first chip to the high temperature adhesive layer 400;

the first conductive member 50 may be made of copper, and in order to make the first conductive member 50 have better electrical connection and prevent copper oxidation, a layer of tin may be sputtered or sprayed on the surface of the first conductive member 50, so as to improve the electrical connection stability of the first conductive member 50.

Step four: and carrying out plastic packaging to form a first plastic packaging layer 70A, and grinding and thinning the first plastic packaging layer 70A to expose the first conductive parts 50.

Here, the first molding compound layer 70A fills the gap between the first chip 30 and the mounting hole 13, fixes the first chip 30 in the mounting hole 13, and covers the first chip 30 and the upper surface of the first photoresist layer 10, thereby realizing effective isolation of the first chip 30 and playing a certain role in protection. Meanwhile, the first molding compound layer 70A is ground to be thinned, and the first conductive member 50 may be exposed only at the position of the first through hole 11, or the surface of the first molding compound layer 70A may be thinned integrally without damaging the first chip 30, so that the package structure 100 is thinner.

Step five: the second chip 90A is placed on the first molding compound layer 70A, and the first pin 91 of the second chip 90A is electrically connected to the first conductive member 50.

Here, it is required that the surface area of the second chip 90A is larger than that of the first chip 30 so that the connection can be directly made.

Step six: carrying out secondary plastic package to form a second plastic package body;

the second molding compound layer 70B needs to cover the second chip 90A and the primary package body completely, so as to form a complete package structure 100, where the second package layer can be ground and thinned as required without damaging the second chip 90A.

Step seven: removing the high-temperature adhesive layer 400 and the temporary carrier plate 200;

the package structure 100 is heated until the viscosity of the high temperature adhesive layer 400 disappears or weakens, and at this time, the temporary carrier 200 and the high temperature adhesive layer 400 fall off from the insulator formed by the first photoresist layer 10, thereby exposing the first conductive member 50 and the first chip 30. To further facilitate the electrical connection of the first chip 30, the lower surface of the first photoresist layer 10 may be disposed on the same plane as the bonding pad of the first chip 30.

Step eight: the external solder balls 20 are implanted to form an electrical connection interface between the first chip 30 and the second chip 90A and an external circuit.

Certainly, there are three or more chips, the connection of the third chip 90B may be the same as the connection of the second chip 90A and the first chip 30, i.e. direct electrical connection, or connection may be performed by Fan-Out (Fan Out) packaging, and meanwhile, the conductive member for electrical connection is also formed on the photoresist layer, so as to simplify the manufacturing process, which is not described herein.

The utility model discloses still provide an electronic equipment (not shown), this electronic equipment includes the casing and locates packaging structure 100 in the casing, above-mentioned embodiment is referred to this packaging structure 100's specific structure, because this electronic equipment's packaging structure 100 has adopted the whole technical scheme of above-mentioned all embodiments, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, and it is no longer repeated here one by one.

The electronic device may be a mobile terminal, such as a mobile phone or a notebook computer, or may be an intelligent bracelet, which is not limited herein. A circuit board is disposed in the housing of the electronic device, and the external solder balls 20 in the package structure 100 are soldered to the circuit board, so as to electrically connect and mount the package structure 100.

The above only is the preferred embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made by the contents of the specification and the drawings under the inventive concept of the present invention, or the direct/indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A package structure, comprising:

the first chip is arranged in the mounting hole;

the first conductive piece is arranged in the first through hole;

2. The package structure of claim 1, wherein a surface of the second chip facing the first molding compound layer is provided with a first pin, the first pin corresponds to an outer peripheral edge of the mounting hole, and the first pin is electrically connected to the first conductive member.

3. The package structure of claim 2, wherein the first through holes are provided in plurality, the first through holes are arranged around the periphery of the mounting hole, a first conductive member is arranged in one of the first through holes, and the first pins are provided in plurality and matched with the first conductive member.

4. The package structure of claim 1, wherein an outer surface of the first conductive member is plated with a protective film; and/or the first conductive piece is made of metal.

5. The package structure of claim 1, wherein a depth of the mounting hole is greater than or equal to a thickness of the first chip; and/or the presence of a gas in the gas,

6. The package structure of claim 1, wherein a surface of the first photoresist layer facing away from the second chip is provided with an external solder ball, and the external solder ball is electrically connected to the first conductive member and the first chip.

7. The package structure of claim 1, further comprising a second molding compound encapsulating the second chip upper surface and side surfaces.

8. The package structure of any of claims 1 to 6, wherein the package structure further comprises:

the second conductive piece is arranged in the second through hole;

9. The package structure according to claim 8, further comprising a wiring layer, wherein the wiring layer is disposed between the second plastic package layer and the third chip, a surface of the third chip facing the second plastic package layer is provided with a second pin, and a projection of the second pin on the second photoresist layer is located in the avoiding hole; the wiring layer is electrically connected with the second conductive piece and the second pin.

10. An electronic device, comprising a housing and a package structure disposed in the housing, wherein the package structure is according to any one of claims 1 to 9.