CN213660399U - Semiconductor device with multilayer metal connecting wire - Google Patents
Semiconductor device with multilayer metal connecting wire Download PDFInfo
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- CN213660399U CN213660399U CN202022144091.XU CN202022144091U CN213660399U CN 213660399 U CN213660399 U CN 213660399U CN 202022144091 U CN202022144091 U CN 202022144091U CN 213660399 U CN213660399 U CN 213660399U
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Abstract
The utility model discloses a semiconductor device with multilayer metal connecting line, which comprises a semiconductor substrate, a first dielectric layer, a first SiN layer, a second dielectric layer and a second SiN layer which are arranged from bottom to top in sequence, and also comprises a first metal connecting line layer and a second metal connecting line layer, wherein the first metal connecting line layer is embedded in the first dielectric layer, and the second metal connecting line layer is embedded in the first SiN layer, the second dielectric layer and the second SiN layer; the bottom end of the first metal connecting line layer is connected with the semiconductor substrate, the top end of the first metal connecting line layer is connected with the bottom end of the second metal connecting line layer, and at least part of the top end of the second metal connecting line layer is exposed out of the second SiN layer. The parasitic effect between the conducting wires or elements is reduced through the low dielectric constant material, and the water vapor is blocked through the high waterproofness of the SiN, so that the parasitic effect reduction and the reliability increase in the multilayer metal connecting wire structure can be realized.
Description
Technical Field
The utility model relates to a semiconductor device technical field especially relates to a semiconductor device with multilayer metal line.
Background
Currently, as the integration level of compound semiconductors increases, more metal layer wires are required for device interconnection; meanwhile, along with the development requirements of the electronic device terminal industry, the requirements for the chip size are smaller and smaller while the I/O ports are increased, and along with the derived advanced packaging technology, the RDL process is also required to be used for I/O re-layout before packaging so as to ensure the high integration and reliability of the chip. At present, in gallium arsenide semiconductor devices, a multilayer metal interconnection layer stacking structure is mostly made of polyimide (polyimide) and gold, but the existing multilayer metal stacking structure has the problem of obvious parasitic effect between conducting wires or elements or the problem of reliability that the product fails due to the influence of factors such as water vapor and the like in the later use environment, and both the problems are difficult to be considered.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the not enough of prior art existence, provide a semiconductor device with multilayer metal line.
In order to realize the above purpose, the technical scheme of the utility model is that:
a semiconductor device having a multilayer metal line, characterized in that: the semiconductor substrate comprises a semiconductor substrate, a first dielectric layer, a first SiN layer, a second dielectric layer and a second SiN layer which are sequentially arranged from bottom to top, and further comprises a first metal connecting line layer and a second metal connecting line layer, wherein the first metal connecting line layer is embedded in the first dielectric layer, and the second metal connecting line layer is embedded in the first SiN layer, the second dielectric layer and the second SiN layer; the bottom end of the first metal connecting line layer is connected with the semiconductor substrate, the top end of the first metal connecting line layer is connected with the bottom end of the second metal connecting line layer, and at least part of the top end of the second metal connecting line layer is exposed out of the second SiN layer.
The second dielectric layer is made of a material with a low dielectric constant, such as at least one of PBO, BCB and PI.
Optionally, the thicknesses of the first SiN layer and the second SiN layer are 200-800 nm respectively.
Optionally, the thickness of the second dielectric layer is 6-15 μm.
Optionally, the thickness of the second dielectric layer is 8 μm.
Optionally, the second dielectric layer is made of PI, BCB, or PBO.
Optionally, the first SiN layer and the second dielectric layer are provided with through holes, the second metal wiring layer fills the through holes and extends to the surface of the second dielectric layer, and the second SiN layer covers the second metal wiring layer and the second dielectric layer and is provided with an external connection port which enables the top end of the second metal wiring layer to be at least partially exposed.
Optionally, the second dielectric layer comprises an upper laminated layer and a lower laminated layer, wherein the lower layer is made of PBO or PI and has a thickness of 6-15 μm; the upper layer is made of PBO or BCB and has a thickness of 6-15 μm.
Optionally, first SiN layer and lower floor are equipped with the through-hole, second metal wiring layer fills the through-hole and extends to the surface of lower floor, upper strata cover second metal wiring layer and lower floor, second SiN layer covers the upper strata, upper strata and second SiN layer are equipped with the messenger the top on second metal wiring layer is at least partly exposed outer mouthful.
Optionally, the first SiN layer and the second SiN layer further cover sidewalls of the first dielectric layer and the second dielectric layer.
Optionally, the semiconductor substrate includes a gallium arsenide-based, gallium nitride-based, or silicon carbide-based substrate or an epitaxial wafer.
The utility model has the advantages that:
by adopting composite laminated layers of different dielectric materials, the parasitic effect between the conducting wires or elements is reduced through the low dielectric constant material, and the high waterproofness of SiN is used for blocking water vapor, so that the consideration of reducing the parasitic effect and improving the reliability in the multilayer metal connecting wire structure can be realized.
Drawings
Fig. 1 is a schematic structural view of a semiconductor device having a multilayer metal wiring of embodiment 1;
FIG. 2 is a schematic structural diagram of a second metal wiring layer in FIG. 1;
fig. 3 is a schematic structural view of a semiconductor device having a multilayer metal interconnection of embodiment 2.
Detailed Description
The invention is further explained below with reference to the drawings and the specific embodiments. The utility model discloses an each drawing only is the schematic in order to understand more easily the utility model discloses, its specific proportion can be adjusted according to the design demand. The relative positions of elements in the figures described herein are understood by those skilled in the art to refer to relative positions of elements, and thus all elements may be reversed to represent the same, all falling within the scope of the disclosure.
Example 1
Referring to fig. 1, a semiconductor device 100 with a multilayer metal interconnection includes a semiconductor substrate 1, a first dielectric layer 2, a first SiN layer 3, a second dielectric layer 4, and a second SiN layer 5, which are sequentially disposed from bottom to top, and further includes a first metal interconnection layer 6 and a second metal interconnection layer 7. The first metal connecting wire layer 6 is embedded in the first dielectric layer 2, and the second metal connecting wire layer 7 is embedded in the first SiN layer 3, the second dielectric layer 4 and the second SiN layer 5; the bottom end of the first metal wiring layer 6 is connected with the semiconductor substrate 1, the top end of the first metal wiring layer is connected with the bottom end of the second metal wiring layer 7, and at least part of the top end of the second metal wiring layer 7 is exposed out of the second SiN layer 5. The second dielectric layer is made of low dielectric constant materials such as poly-p-Phenylene Benzobisoxazole (PBO), benzocyclobutene (BCB), Polyimide (PI) and the like, and forms a composite interlayer dielectric layer of the metal connecting lines with the SiN material, so that the parasitic effect among the metal connecting lines is reduced, and the reliability is improved.
Specifically, the first SiN layer 3 covers the surfaces of the first dielectric layer 2 and the first metal connecting line layer 6 to play a role in protecting against water vapor and the like, and the thickness of the first SiN layer 3 is 200-800 nm, for example, 400 nm. The second dielectric layer 4 is disposed on the first SiN layer 3, and has a thickness of 6-15 μm, such as 8 μm. The first SiN layer 3 and the second dielectric layer 4 are respectively provided with through holes 3a and 4a corresponding in position and same in size or different in size, the through holes 3a and 4a correspond to the top end of the first metal connecting line layer 6, the second metal connecting line layer 7 fills the through holes 3a and 4a and extends to the surface of the second dielectric layer 2, namely, the through holes 3a and 4a are connected with the first metal connecting line layer 6, and wiring patterns are formed on the surface of the second dielectric layer 4. The second SiN layer 5 covers the surfaces of the second metal wiring layer 7 and the second dielectric layer 4 and is provided with an external connection port 5a which enables the top end of the second metal wiring layer 7 to be at least partially exposed. The thickness of the second SiN layer 5 is 200-800 nm, such as 400 nm. The second SiN layer 5 blocks moisture as an outermost protective layer.
Referring to fig. 2, the second metal wiring layer 7 may be formed using a process such as plating. In addition, a sputtering process may be used to deposit a bonding layer 71 before electroplating, the bonding layer 71 may be, for example, titanium (Ti), titanium Tungsten (TiW), tantalum (Ta), nickel vanadium (NiV), tantalum nitride (TaN), or the like to increase the bonding force between the electroplating metal and the dielectric material, and then the seed layer 72 is sputtered and electroplated to form the electroplated layer 73, and the materials of the seed layer 72 and the electroplated layer 73 include one of gold (Au), copper (Cu), aluminum (Al), or an alloy containing one of Au, Cu, and Al.
The first dielectric layer 2 comprises an upper lamination layer and a lower lamination layer, wherein the materials of the lower layer 21 and the upper layer 22 are respectively selected from PBO, BCB, PI, SiN and SiO2And the like. The lower layer 21 covers the surface of the semiconductor substrate 1 to protect the semiconductor substrate 1 and is provided with a through hole 21a, the first metal wiring layer 6 fills the through hole 21a and extends to the surface of the lower layer 21 to form a wiring pattern, and the upper layer 22 covers the first metal wiring layer 6 and the lower layer 21 and exposes the top end of the first metal wiring layer 6 at least partially to facilitate connection with the second metal wiring layer 7. In addition, the first metal interconnection layer 6 may also be a columnar structure, and penetrates through the first dielectric layer 2 from top to bottom.
The first SiN layer 3 covers the surface of the first dielectric layer 2, and the second SiN layer 5 covers the surface of the second dielectric layer 4, namely the top surface and the side surfaces are covered, so that corrosion caused by water vapor entering the metal connecting line structure from the side surfaces is avoided.
The semiconductor substrate 1 comprises a gallium arsenide-based, gallium nitride-based, silicon carbide-based substrate or epitaxial wafer or the like containing one or more active or passive component designs.
Example 2
Referring to fig. 3, a semiconductor device 200 with a multilayer metal interconnection, wherein a semiconductor substrate 1, a first dielectric layer 2, a first metal interconnection layer 6 and a first SiN layer 3 are the same as those of embodiment 1, and a second dielectric layer 4' comprises an upper layer and a lower layer, wherein a lower layer 41 is made of PBO or PI and has a thickness of 6 to 15 μm; the upper layer 42 is made of PBO or BCB (benzocyclobutene) and has a thickness of 6-15 μm. The first SiN layer 3 and the lower layer 41 are provided with through holes 3a, 41a, respectively, and the second metal wiring layer 7 fills the through holes 3a, 41a and extends to the surface of the lower layer 41. The upper layer 42 covers the second metal wiring layer 7 and the lower layer 41, the second SiN layer 5 covers the upper layer 42, and the upper layer 42 and the second SiN layer 5 are provided with external connection ports 42a, 5a that expose at least part of the top end of the second metal wiring layer 7. For example, the lower layer 41 is made of PI with a thickness of 8 μm, and the upper layer 42 is made of PBO with a thickness of 8 μm, wherein the PBO has better water resistance and is beneficial to isolating water vapor. According to the subsequent packaging requirements, a WB process or a bumping process is adopted, and the subsequent bump can be selectively electroplated to generate a Cu-pilar/Solder bump or processes of ball planting/printing and the like. For example, the top end of the second metal interconnection layer 7 is provided with a metal bump 8 protruding out of the surface of the second SiN layer 5 by a Cu-pilar process, the top end of the metal bump 8 includes a barrier layer 81 and a tin-silver cap 82, and the barrier layer 81 is made of metal titanium (Ti), titanium-Tungsten (TiW), tantalum (Ta), nickel-vanadium (NiV), tantalum nitride (TaN), or the like.
The properties of 3 specific types of low dielectric constant materials are listed below.
The material has lower dielectric constant and good insulating property, can effectively prevent the parasitic effect of a metal connecting wire layer of a device, and is matched with an SiN material with better waterproof property, so that the parasitic effect is reduced and the reliability of the device is improved.
The above embodiments are only used to further illustrate the semiconductor device with multilayer metal wires of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made by the technical entity of the present invention to the above embodiments all fall into the protection scope of the technical solution of the present invention.
Claims (10)
1. A semiconductor device having a multilayer metal line, characterized in that: the semiconductor substrate comprises a semiconductor substrate, a first dielectric layer, a first SiN layer, a second dielectric layer and a second SiN layer which are sequentially arranged from bottom to top, and further comprises a first metal connecting line layer and a second metal connecting line layer, wherein the first metal connecting line layer is embedded in the first dielectric layer, and the second metal connecting line layer is embedded in the first SiN layer, the second dielectric layer and the second SiN layer; the bottom end of the first metal connecting line layer is connected with the semiconductor substrate, the top end of the first metal connecting line layer is connected with the bottom end of the second metal connecting line layer, and at least part of the top end of the second metal connecting line layer is exposed out of the second SiN layer.
2. The semiconductor device with multilayer metal wiring of claim 1, wherein: the thicknesses of the first SiN layer and the second SiN layer are 200-800 nm respectively.
3. The semiconductor device with multilayer metal wiring of claim 1, wherein: the thickness of the second dielectric layer is 6-15 mu m.
4. The semiconductor device with multilayer metal wiring of claim 3, wherein: the thickness of the second dielectric layer is 8 μm.
5. The semiconductor device with multilayer metal wiring of claim 1, wherein: the second dielectric layer is made of PI, BCB or PBO.
6. The semiconductor device with multilayer metal wiring according to claim 5, wherein: the first SiN layer and the second medium layer are provided with through holes, the second metal connecting line layer fills the through holes and extends to the surface of the second medium layer, and the second SiN layer covers the second metal connecting line layer and the second medium layer and is provided with an outer connecting opening which enables the top end of the second metal connecting line layer to be at least partially exposed.
7. The semiconductor device with multilayer metal wiring of claim 1, wherein: the second dielectric layer comprises an upper laminated layer and a lower laminated layer, wherein the lower layer is made of PBO or PI and has the thickness of 6-15 microns; the upper layer is made of PBO or BCB and has a thickness of 6-15 μm.
8. The semiconductor device with multilayer metal wiring of claim 7, wherein: first SiN layer and lower floor are equipped with the through-hole, second metal wiring layer fills the through-hole and extends to the surface of lower floor, upper strata cover second metal wiring layer and lower floor, second SiN layer covers the upper strata, upper strata and second SiN layer are equipped with the messenger the top on second metal wiring layer is at least partly exposed outer mouthful.
9. The semiconductor device with multilayer metal wiring of claim 1, wherein: the first SiN layer and the second SiN layer further cover the side walls of the first dielectric layer and the second dielectric layer.
10. The semiconductor device with multilayer metal wiring of claim 1, wherein: the semiconductor substrate is a gallium arsenide-based substrate, a gallium nitride-based substrate, a silicon carbide-based substrate, a gallium arsenide-based epitaxial wafer, a gallium nitride-based epitaxial wafer or a silicon carbide-based epitaxial wafer.
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| CN202022144091.XU CN213660399U (en) | 2020-09-24 | 2020-09-24 | Semiconductor device with multilayer metal connecting wire |
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| CN202022144091.XU CN213660399U (en) | 2020-09-24 | 2020-09-24 | Semiconductor device with multilayer metal connecting wire |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113506790A (en) * | 2021-09-08 | 2021-10-15 | 北京芯愿景软件技术股份有限公司 | Chip, preparation method thereof and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113506790A (en) * | 2021-09-08 | 2021-10-15 | 北京芯愿景软件技术股份有限公司 | Chip, preparation method thereof and electronic equipment |
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