CN213583804U - High-speed switch structure - Google Patents
High-speed switch structure Download PDFInfo
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- CN213583804U CN213583804U CN202022643858.3U CN202022643858U CN213583804U CN 213583804 U CN213583804 U CN 213583804U CN 202022643858 U CN202022643858 U CN 202022643858U CN 213583804 U CN213583804 U CN 213583804U
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Abstract
The utility model discloses a high-speed switch structure, this high-speed switch includes: the P-type substrate, the shallow trench isolation and the deep trench ring are used for replacing the sidewall capacitor of the isolated PN junction in the prior art by forming the deep trench ring on the sidewall of the isolated PN junction of the MOS switch tube and filling a low-dielectric constant medium, so that the sidewall capacitor of the PN junction of the isolated well is eliminated, and meanwhile, the isolated well is biased with high potential, so that the bottom surface capacitors of the PN junction of the isolated well and the substrate as well as the isolated well and the MOS switch tube body area are further reduced, thereby reducing the parasitic capacitance between a signal channel of the MOS switch device and the ground and realizing the improvement of the bandwidth performance of a high-speed signal.
Description
Technical Field
The utility model relates to a semiconductor device prepares technical field, and more specifically the theory says, relates to a high-speed switch structure.
Background
High-speed switch Integrated Circuits (ICs) are a type of integrated circuits widely used in mobile portable devices, such as a Mobile Industry Processor Interface (MIPI) switch, a USB2.0 switch, a USB3.0 switch, and the like, and parasitic capacitance on a high-speed channel of the high-speed switch IC attenuates a signal to reduce a bandwidth of a signal that can pass through, so that it is necessary to reduce all parasitic capacitances to ground on the switch channel as much as possible. In the parasitic capacitance of the switch channel, the parasitic capacitance of the switch MOS tube to the ground is the most main capacitance, and the existing method for reducing the parasitic capacitance of the MOS device is to reduce the parasitic capacitance of the MOS tube to the ground by connecting the isolated PN junction capacitance to the ground in series.
The parasitic capacitance of the PN junction between the body region of the high-speed switch and the isolation and the substrate are main capacitances for determining the capacitance of the switch tube. The parasitic capacitor isolated to the substrate ground is composed of the bottom surface capacitor and the side wall capacitor of the isolated PN junction, the size proportion relation of the parasitic capacitor is changed along with the size of the area of the body region and the isolation area of the MOS switch, the smaller the area of the body region and the isolation well is, the smaller the capacitance proportion of the bottom surface of the PN junction is, and the larger the capacitance proportion of the side wall of the PN junction is. Along with the trend that the frequency of a communication signal is increased, the working voltage is reduced, and the width of an MOS switch pipeline is reduced, the side wall and the bottom surface of an isolation region of an MOS switch tube become main capacitors for determining the parasitic capacitance of the MOS switch to the ground.
Therefore, how to provide a high-speed switch structure is a problem that needs to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides a high-speed switch structure has reduced the signal attenuation of NMOS switch tube in the high-speed switch to ground, promotes the signal bandwidth to combine to keep apart on the trap offset high potential reduction parasitic capacitance to ground.
In order to achieve the above purpose, the utility model provides a following technical scheme:
in a first aspect, the present application provides a high speed switch architecture comprising:
a P-type substrate, a shallow trench isolation and a deep trench ring,
the P-type substrate is provided with a P-type substrate active leading-out end and a deep N-well isolation boundary, the shallow trench isolation is arranged on the inner side of the P-type substrate active leading-out end, and the deep trench ring is arranged on the inner side of the shallow trench isolation;
preferably, the deep groove ring inner part comprises the deep N-well isolation boundary, and the deep groove ring inner side is provided with a deep N-well isolation active region leading-out end.
Preferably, a P-type body region and a deep N-well isolation boundary are arranged on the inner side of the leading-out end of the deep N-well isolation active region;
preferably, the inner side of the boundary isolated by the P-type body region and the deep N well further comprises in sequence: an active leading-out end of the P-type body region, a source active region, a drain active region and a polysilicon gate.
Preferably, the depth of the deep groove ring is 5-120 μm, and the width of the deep groove ring is 5-50 μm.
Preferably, the included angle between the side wall of the deep groove ring and the bottom of the deep groove ring is 90-135 degrees, and the included angle between the side wall of the deep groove ring and the silicon horizontal surface at the top of the deep groove ring is also 90-135 degrees.
In a second aspect, the present invention provides a method for manufacturing a high-speed switch, the method comprising:
s1, forming an isolation deep N well and an active region of the MOS switch tube and injecting and diffusing a standardized N well and a standardized P well;
s2, depositing a first film outside the deep N well as a hard mask of the deep groove ring, coating photoresist on the first film, and performing deep groove ring pattern photoetching to form the deep groove ring, wherein the deep groove ring comprises a side wall of a deep N well isolation boundary on the P-type substrate, and a deep N well isolation active region leading-out end is arranged on the inner side of the deep groove ring;
s3, removing the photoresist and the hard mask, thermally growing a thin oxide layer as a transition layer, depositing a low dielectric constant medium to fill the deep groove ring, and then performing etching or chemical mechanical planarization;
and S4, carrying out metal post-processing, and forming a source drain region and a metal silicide by thermally growing a gate oxide layer and depositing polysilicon.
Preferably, the depth of the deep groove ring is 5-120 μm, and the width of the deep groove ring is 5-50 μm.
Preferably, the included angle between the side wall of the deep groove ring and the bottom of the deep groove ring is 90-135 degrees, and the included angle between the side wall of the deep groove ring and the silicon horizontal surface at the top of the deep groove ring is also 90-135 degrees.
Known through foretell technical scheme, compare with prior art, the utility model provides a high-speed switch structure has following effect:
the method of forming deep groove ring on the side wall of the isolation PN junction of the MOS switch tube and filling low dielectric constant medium replaces the side wall capacitance of the isolation PN junction in the prior art, because the depth and width of the deep groove ring can be greatly reduced to the substrate capacitance, the PN junction side wall capacitance of the isolation trap can be basically and equivalently eliminated, meanwhile, the isolation trap is biased with high potential, the PN junction bottom surface capacitance of the isolation trap and the substrate and the isolation trap and the MOS switch tube body area is further reduced, thereby greatly reducing the parasitic capacitance between the signal channel of the MOS switch device and the ground and improving the high-speed signal bandwidth performance.
The utility model discloses fill the effect that the slot reduces the total parasitic capacitance of PN junction between high speed channel to ground and reduce between 10% to 50%. For switches with lower working voltage, the effect of reducing the capacitance is more obvious by combining the isolation deep N-well biased to high voltage. Therefore, the method combining the two measures can effectively reduce the parasitic capacitance of the whole high-speed channel to the ground, and particularly achieves the effects of low cost and high efficiency for the high-speed switch bandwidth applied to more than 5 GHz.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a plan view of a PN junction isolator according to the prior art provided by the present invention;
fig. 2 is a longitudinal sectional view of a PN junction isolator formed according to the prior art provided by the present invention;
fig. 3 is a top view of a high-speed switch structure provided by the present invention;
fig. 4 is a longitudinal sectional view of a high-speed switch structure provided by the present invention.
In fig. 1-4:
1-deep N well isolation boundary, 2-P type body region and deep N well isolation boundary, 3-deep N well isolation active region leading-out end, 4-P type body region active leading-out end, 5-active region and drain active region, 6-polysilicon gate, 7-P type substrate, 8-P type substrate active leading-out end, 9-shallow groove isolation, 11-deep groove ring
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Example 1
In the following description, unless otherwise specified, a typical NMOS with deep N-well isolation is taken as an example, and a schematic diagram of a high-speed switch in the prior art shown in fig. 1-2 includes:
p type substrate 7, shallow slot isolation 9, it draws end 8 and dark N well isolation boundary 1 to be provided with the active terminal of drawing of P type substrate on the P type substrate 7, shallow slot isolation 9 sets up in the active inboard of drawing end 8 of P type substrate, shallow slot isolation 9 is inside to contain dark N well isolation boundary 1, shallow slot isolation 9 inboard is provided with dark N well isolation active area and draws end 3, 3 inboards of dark N well isolation active area are provided with P type somatic region and dark N well isolation boundary 2, the inboard of P type somatic region and dark N well isolation boundary 2 still outside-in includes in proper order: a P-type body region active terminal 4, source and drain active regions 5 and a polysilicon gate 6.
For the switch tube in the high speed switch IC circuit of the prior art, it is usually selected to use the MOS device with PN junction isolation, for example, the MOS device is made in the deep N well on the P-type substrate or the deep N well and N-type buried layer isolation structure, so the parasitic capacitance of the input terminal and the output terminal of the switch tube to the ground is composed of the following parts, as shown in fig. 2, firstly the PN junction capacitance Csd _ b between the source and drain terminals and the body terminal, the total PN junction capacitance Cb _ iso of the body terminal to the isolation well (iso), the total PN junction capacitance Ciso of the isolation well (iso) to the substrate, where Cb _ iso and Ciso _ sub are composed of the PN junction bottom capacitance and the side wall capacitance, respectively,
can be written as:
Cb_iso＝Cb_iso_0+Cb_iso_sw
and the number of the first and second groups,
Ciso_sub＝Ciso_sub_0+Ciso_sub_sw
cb _ iso _0 represents the PN junction bottom surface capacitance from the body end to the isolation well, and Cb _ iso _ sw represents the PN junction side wall capacitance from the body end to the isolation well; ciso _ sub _0 represents the isolation well to substrate PN junction bottom capacitance and Ciso _ sub _ sw represents the isolation well to substrate PN junction sidewall capacitance. Then the total capacitance of PN junction from high speed channel to ground is Csd _ b series Cb _ iso, then Ciso _ sub, the calculation formula of total capacitance of PN junction from high speed channel to ground in the prior art is:
1/Cj＝1/Csd_b+1/(Cb_iso_0+Cb_iso_sw)+1/(Ciso_sub_0+Ciso_sub_sw) (1.1)
to solve the above problem, embodiments of the present application provide a high-speed switch structure, which includes, with reference to fig. 3 to 4:
p-type substrate 7, shallow slot isolation 9 and deep groove ring 11, be provided with the active end 8 and the dark N well isolation border 1 of drawing forth of P-type substrate on the P-type substrate 7, shallow slot isolation 9 sets up in the active inboard of drawing forth end 8 of P-type substrate, deep groove ring 11 sets up in the inboard of shallow slot isolation 9, wherein, include dark N well isolation border 1 in the deep groove ring 11, and deep groove ring 11 inboard is provided with dark N well isolation active area and draws forth end 3, dark N well isolation active area is drawn forth 3 inboards and is provided with the P type somatic region and dark N well isolation border 2, wherein, the inboard of the border 2 that the P type somatic region and dark N well were kept apart still includes in proper order: an active terminal 4 of the P-type body region, a source active region and a drain active region 5 and a polysilicon gate 6.
Specifically, the depth of the deep groove ring 11 is the height from the bottommost part of the deep groove ring 11 to the silicon surface of the substrate, the depth of the deep groove ring 11 is 5-120 μm, and the width of the deep groove ring 11 is 5-50 μm.
Specifically, when the deep groove ring 11 is etched, an included angle between the side wall of the deep groove ring 11 and the bottom of the deep groove ring 11 is required to be 90-135 degrees, and an included angle between the side wall of the deep groove ring 11 and the silicon horizontal surface at the top of the deep groove ring 11 is also required to be 90-135 degrees.
In this embodiment, the dielectric capacitor of the deep trench ring 11 is used to replace the sidewall capacitor of the PN junction, because the capacitance value of the sidewall trench dielectric capacitor is inversely proportional to the width of the trench, and after the width of the deep trench 11 reaches above 10 μm, the sidewall capacitor of the deep trench 11 is basically very small, and can be reduced to below 1/100 of the sidewall capacitor of the PN junction, so as to basically achieve the effect of eliminating the sidewall PN junction capacitor, and therefore, the calculation formula of the total capacitance of the PN junction becomes:
1/Ct≈1/Csd_b+1/Cb_iso_0+1/Ciso_sub_0 (1.2)
since the inverse bias capacitance of the PN junction is inversely proportional to the root of the sum of the heat balance built-in potential at two ends of the PN junction and the absolute value of the inverse bias voltage, the capacitance of the inverse bias PN junction is smaller as the inverse bias voltage is higher, and the capacitances obtained after the isolation end (iso end) is biased to a high voltage are Cb _ iso _1 and Ciso _ sub _1, so the calculation formula of the total capacitance of the PN junction becomes:
1/Ct1≈1/Csd_b+1/Cb_iso_1+1/Ciso_sub_1 (1.3)
comparing equation 1.3 with equation 1.1, Ct1 benefits from eliminating sidewall capacitances Cb _ iso _ sw and Ciso _ sub _ sw, and Cb _ iso _1< Cb _ iso _0 and C iso _ sub _1< Ciso _ sub _0 after the isolation end (iso end) is biased to high voltage, the total capacitance Ct1 of the PN junction of the present invention is significantly smaller than the total capacitance Cj of the PN junction of the channel in the prior art.
As can be seen from the above, the effect of reducing capacitance is more pronounced for lower voltage switches, and in combination with the isolation well being biased to a high voltage, e.g., 15.4V, then Cb _ iso _1 becomes approximately one-fourth of Cb _ iso _0 and Ciso _ sub _1 becomes approximately one-fourth of Ciso _ sub _ 0.
More specifically, a deep groove ring pattern photomask can be added to the deep groove ring, and the pattern of the deep groove ring is an annular pattern which is expanded and extended to a certain size along the boundary of the body region and the isolation PN junction of the switch tube. The inner side boundary of the deep groove ring annular pattern extends from the P type body area of the switch tube and the deep N well isolation boundary 2 to the inside by 1 mu m to 10 mu m (namely, 1 mu m < b <10 mu m), and the outer side boundary of the deep groove ring annular pattern extends from the deep N well isolation of the switch tube and the PN junction boundary of the P type substrate 7 to the outside (namely, 1 mu m < a <40 mu m).
Simultaneously the utility model provides a fill in the deep groove ring and can be silicon oxide or other low dielectric constant's dielectric material, fill up after the deep groove ring and carry out the planarization or anti-carve. The specific trench etching and filling processes can be adjusted according to the optimization of materials and stress under specific conditions.
Example 2
The embodiment 2 provides a method for manufacturing a high-speed switch, which specifically includes:
and inserting a deep groove ring process module after forming a P well and an N well of the CMOS.
1. Typically involves forming an isolated N-type deep well, forming an active region, and standard CMOS N-well and P-well implantation and diffusion.
2. Depositing silicon oxide or silicon oxide and silicon nitride multilayer film as a deep groove etching hard mask, coating photoresist to perform deep groove ring pattern photoetching, and then performing deep groove etching, wherein the deep groove ring pattern is annular, the inner side of the deep groove ring is required to be within the PN junction boundary of the isolation N-type deep well of the MOS switch tube, and the outer side of the deep groove ring is required to be at a distance beyond the PN junction boundary of the isolation N-type deep well and the substrate, namely the side wall which contains the PN junction boundary of the isolation N-type deep well of the MOS switch tube and the substrate in the deep groove etching window.
3. Removing the photoresist and the hard mask, thermally growing a thin oxide layer as a transition layer, depositing a silicon oxide medium by a CVD or HDP method to fill the deep groove, and then carrying out etching or chemical mechanical planarization.
4. And continuing the standard CMOS process, which comprises the steps of thermally growing a gate oxide layer, depositing polycrystalline silicon, forming a source drain region, forming metal silicide and carrying out a metal subsequent process of the standard CMOS process.
Example 3
1. the standard isolation type CMOS switch front-end process generally comprises the steps of forming an isolation N-type deep well, forming an active region, injecting and diffusing the N well and a P well of a standard CMOS, and forming a polycrystalline grid electrode and a source drain region.
2. Depositing silicon oxide or silicon oxide and silicon nitride multilayer film as a deep groove etching hard mask, coating photoresist to perform deep groove ring pattern photoetching, and performing deep groove etching, wherein the inside of the deep groove etching window comprises a side wall of a PN junction boundary between an isolated N-type deep well of an MOS switch tube and a P substrate.
3. And removing the photoresist, depositing a silicon oxide medium by using a PECVD (plasma enhanced chemical vapor deposition) method and an HDP (high-density plasma treatment) method to fill the deep groove, and then carrying out etching or chemical mechanical planarization to remove the hard mask.
4. Metal post-processing of a standard CMOS process is performed.
Example 4
By utilizing the high-speed switch structure provided by the utility model, the middle switch P-type body area and the deep N-well isolated PN junction boundary 2 are not in the deep groove ring 11, but are in the N-type deep well region 1, therefore, the electric potential of the N-type deep well region 1 can be connected from the surface through the active leading-out terminal 3 of the N-type deep well region, namely the N-type deep well region 1 can be applied with bias voltage from the surface,
according to the depletion layer capacitance formula of a reverse biased diode:
in the formula (I), the compound is shown in the specification,
for the capacitance under reverse bias of the diode and the built-in potential under root sign, VdWhen reverse bias voltage is applied to the diode, VdIs negative and when the diode technology in the formula is determined, except for the bias voltage VdAnd others are all definite constants.
According to the formula, when the typical value of the diode built-in potential is 0.6V, then when Vdat-5V, the reverse biased PN junction capacitance between the isolation and substrate ground becomes 1/3 as before, and the isolation and open as beforeThe reverse bias capacitance between the body regions of the NMOS also becomes 1/3 of the previous case, which is very significant for reducing the parasitic capacitance.
As can be seen from example 4, the addition of the bias voltage has a great effect on reducing the reverse bias PN junction capacitance between the isolation and the substrate ground, and reducing the reverse bias capacitance between the isolation and the body of the switch NMOS.
Above-mentioned deep groove ring technology integration has the implementation of N type deep well in keeping apart the CMOS technology, other have many implementation manners in addition, for example with above-mentioned deep groove ring technology integration in the isolation CMOS technology that has P type epitaxy and N type buried layer or with this packing medium deep groove ring technology module other positions in the CMOS technology, as long as accord with the utility model discloses an integrated packing medium deep groove ring technology, the thought that replaces the PN junction lateral wall electric capacity between isolation N well and the P type substrate with the medium electric capacity in the deep groove ring all books with the utility model discloses within the protection range, simultaneously the utility model provides an N type deep well still should receive the high potential, further reduces the parasitic PN junction bottom surface electric capacity of keeping apart N type deep well and substrate to further reduce the high speed switch and to ground electric capacity, promote high speed switch product bandwidth performance.
In the above description of the disclosed embodiments, no matter what kind of deep trench ring pattern, as long as it is in line with the present invention, the method of forming the deep trench ring filled with the medium at the PN junction isolation boundary to replace the PN junction isolation sidewall capacitance idea is all within the scope of the present invention.
To enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A high speed switch architecture, comprising: a P-type substrate, a shallow trench isolation and a deep trench ring,
the P-type substrate is provided with a P-type substrate active leading-out end and a deep N-well isolation boundary, the shallow trench isolation is arranged on the inner side of the P-type substrate active leading-out end, and the deep trench ring is arranged on the inner side of the shallow trench isolation;
the deep groove ring is internally provided with the deep N-well isolation boundary, and the inner side of the deep groove ring is provided with a deep N-well isolation active region leading-out end.
2. The high-speed switch structure of claim 1, wherein a P-type body region and a deep N-well isolation boundary are disposed inside the deep N-well isolation active region lead-out;
wherein, the inside of the boundary that P type somatic region and deep N well keep apart still includes in proper order: an active leading-out end of the P-type body region, a source active region, a drain active region and a polysilicon grid.
3. A high speed switch architecture according to claim 1, wherein the deep trench rings have a depth of 5-120 μm and a width of 5-50 μm.
4. A high speed switch structure according to claim 3, wherein the angle between the side wall of said deep groove ring and the bottom of said deep groove ring is 90-135 °, and the angle between the side wall of said deep groove ring and the silicon horizontal surface at the top of said deep groove ring is also 90-135 °.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022643858.3U CN213583804U (en) | 2020-11-16 | 2020-11-16 | High-speed switch structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022643858.3U CN213583804U (en) | 2020-11-16 | 2020-11-16 | High-speed switch structure |
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| CN213583804U true CN213583804U (en) | 2021-06-29 |
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