CN213521866U - Receiver system adopting analog phase shift - Google Patents
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- CN213521866U CN213521866U CN202023146193.1U CN202023146193U CN213521866U CN 213521866 U CN213521866 U CN 213521866U CN 202023146193 U CN202023146193 U CN 202023146193U CN 213521866 U CN213521866 U CN 213521866U
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Abstract
The utility model provides an adopt receiver system of simulation phase shift, including the accept channel subassembly, the local oscillator subassembly, control module, self-checking module and DDS circuit, the accept channel subassembly is used for receiving radio frequency signal and generates the intermediate frequency signal with radio frequency signal mixing, the local oscillator subassembly provides the local oscillator signal for the accept channel subassembly, the accept channel subassembly is including the amplitude limiter that connects gradually, the frequency selection module, the frequency mixing module, phase shift module and intermediate frequency output module, the frequency selection module is including the first wave filter that connects gradually, STC control circuit, low noise amplifier, preselection filter group and first attenuator, the frequency mixing module is including the second low noise amplifier that connects gradually, mixer and second attenuator, the phase shift module is including the second wave filter that connects gradually, the third low noise amplifier, the third attenuator, the amplitude correction control circuit, the fourth attenuator, the direct current amplifier, A phase correction control circuit; the utility model discloses it is high, the cost is lower to move the phase precision.
Description
Technical Field
The utility model relates to a wireless communication technology field particularly, relates to an adopt simulation receiver system that moves mutually.
Background
The receiver is widely applied to the fields of frequency hopping communication, radar, satellite, electronic warfare and the like, wherein a frequency conversion component of the receiver is a key component for high-sensitivity receiving in the fields of radar countermeasure, satellite communication and the like and is responsible for radio filtering, amplification conditioning and frequency conversion processes. When the existing receiver receives signals, the frequency conversion component accesses the signals from the antenna unit, and is connected with the data processing unit after the frequency conversion component filters and performs frequency conversion treatment, the frequency conversion receiver generally has a plurality of channels, but a single channel in the receiver has simpler functions, and the multi-channel receiver has higher requirements on phase consistency, amplitude consistency and isolation degree due to a plurality of channels, so that the realization difficulty of the receiver is increased.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an adopt the simulation to move receiver system of phase, it adopts phase correction control circuit, and it is high to move the phase precision, easily satisfies the requirement of passageway phase uniformity.
The embodiment of the utility model discloses a realize through following technical scheme:
a receiver system adopting analog phase shift comprises a plurality of receiving channel assemblies and local oscillator assemblies, wherein the local oscillator assemblies are connected with the receiving channel assemblies, each receiving channel assembly comprises an amplitude limiter, a frequency selection module, a frequency mixing module, a phase shift module and an intermediate frequency output module which are sequentially connected, each frequency selection module comprises a first filter, an STC (time-to-date) control circuit, a low-noise amplifier, a preselection filter group and a first attenuator which are sequentially connected, each frequency mixing module comprises a second low-noise amplifier, a frequency mixer and a second attenuator which are sequentially connected, each phase shift module comprises a second filter, a third low-noise amplifier, a third attenuator, an amplitude correction control circuit, a fourth attenuator and a phase correction control circuit which are sequentially connected, each intermediate frequency output module comprises a fifth attenuator, a third filter and a fourth low-noise amplifier which are sequentially connected, and the output end of the local oscillator component is connected with the frequency mixer.
Preferably, the local oscillator module includes a filtering amplification module, a frequency doubling module and a power dividing module which are connected in sequence, the filtering amplification module includes a sixth attenuator, a fourth filter and a first amplifier which are connected in sequence, the frequency doubling module includes a frequency multiplier, a seventh attenuator, a fifth filter and a fifth low noise amplifier which are connected in sequence, the power dividing module includes a first power divider, an output end of the first power divider is connected with a plurality of first power dividing circuits, and the first power dividing circuits include a second power divider, an eighth attenuator and a second amplifier which are connected in sequence.
Preferably, the receiver system further includes a control module, the control module is respectively connected to the receiving channel module and the local oscillation module, the control module employs an FPGA chip, and the FPGA chip is respectively connected to the STC control circuit, the amplitude correction control circuit, and the phase correction control circuit.
Preferably, the receiver system further includes a power module, the power module includes a DC/DC converter, an output end of the DC/DC converter is connected to a plurality of filtering and isolating circuits respectively, the filtering and isolating circuits are used for isolating and filtering a power supply, and the filtering and isolating circuits are connected to the receiving channel component, the local oscillator component and the control module respectively.
Preferably, the receiver system further includes a self-checking module, the self-checking module is connected to the control module, the self-checking module includes a frequency source, a modulator, and a third power divider that are connected in sequence, an output end of the third power divider is further connected to a plurality of second power divider circuits, each of the second power divider circuits includes a fourth power divider, and an output end of the fourth power divider is connected to an output end of the receiving channel component.
Preferably, the receiver system further includes a DDS circuit, the DDS circuit is connected to the FPGA chip, and the DDS circuit is configured to provide a signal source for the local oscillation signal.
Preferably, the STC control circuit is composed of two stages of first digitally controlled attenuators connected in series.
Preferably, the phase correction control circuit includes an analog phase shifter and a digital potentiometer, the FPGA chip is connected to the digital potentiometer, and the digital potentiometer is connected to the analog phase shifter.
Preferably, the amplitude correction control circuit comprises a second digitally controlled attenuator.
Preferably, the first filter employs an image rejection filter.
The utility model discloses technical scheme has following advantage and beneficial effect at least:
1. the phase correction control circuit in the receiving channel assembly of the utility model adopts the cooperation of the analog phase shifter and the high-precision digital potentiometer, and the phase shifting precision is high;
2. the utility model arranges the phase correction control circuit in the intermediate frequency part, reduces the number of stages influencing the consistency of the radio frequency part, and the cost of the intermediate frequency phase shifter is relatively low;
3. the utility model adopts the DDS circuit to provide local oscillation signals for the local oscillation assembly, the frequency hopping speed is high, and the frequency precision is high;
the utility model relates to a rationally, simple structure, the practicality is strong and the cost is lower.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram of a receiver system according to embodiment 1 of the present invention;
fig. 2 is a structural diagram of a frequency selection module of a receiving channel assembly provided in embodiment 1 of the present invention;
fig. 3 is a structure diagram of a frequency mixing module of a receiving channel module according to embodiment 1 of the present invention;
fig. 4 is a structural diagram of a phase shift module of a receiving channel module according to embodiment 1 of the present invention;
fig. 5 is a structure diagram of an intermediate frequency output module of a receiving channel assembly provided in embodiment 1 of the present invention;
fig. 6 is a structural diagram of an amplifying and filtering module and a frequency doubling module of a local oscillator module according to embodiment 1 of the present invention;
fig. 7 is a structure diagram of a power division module of a local oscillator module according to embodiment 1 of the present invention;
fig. 8 is a structural diagram of a self-checking module provided in embodiment 1 of the present invention;
fig. 9 is a structural diagram of a control module provided in embodiment 1 of the present invention;
fig. 10 is a graph of phase shift versus voltage of the analog phase shifter according to embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship which is usually placed when the product of this application is used, the description is only for convenience of description and simplification, but the indication or suggestion that the device or element to be referred must have a specific orientation, be constructed in a specific orientation and be operated is not to be construed as limiting the present invention.
In the description of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
In this embodiment, the frequency of the rf signal is 999 MHz-1121 MHz, the frequency of the local oscillator signal is 322.5 MHz-357.5 MHz, the frequency of the high local oscillator signal is 1299 MHz-1421 MHz, the frequency of the intermediate frequency signal is 300MHz, the number of the receiving channel components is 6 channels,
as shown in fig. 1-9, a receiver system using analog phase shift includes a plurality of receiving channel assemblies and local oscillation assemblies, the local oscillation assemblies are connected to the receiving channel assemblies, the receiving channel assemblies include an amplitude limiter, a frequency selection module, a frequency mixing module, a phase shifting module and an intermediate frequency output module, the frequency selection module includes a first filter, an STC control circuit, a low noise amplifier, a preselection filter set and a first attenuator, which are connected in sequence, the frequency mixing module includes a second low noise amplifier, a frequency mixer and a second attenuator, which are connected in sequence, the phase shifting module includes a second filter, a third low noise amplifier, a third attenuator, an amplitude correction control circuit, a fourth attenuator and a phase correction control circuit, which are connected in sequence, the intermediate frequency output module includes a fifth attenuator, a third filter and a fourth low noise amplifier, which are connected in sequence, the output end of the local oscillator component is connected with the frequency mixer.
The principle of the receiving channel assembly is that a radio frequency signal enters from the input end of an amplitude limiter, the amplitude limiter carries out amplitude limiting processing on the radio frequency signal, then the radio frequency signal is filtered sequentially through a first filter, amplified through a low noise amplifier through an STC control circuit and frequency-selected through a preselected filter bank, power adjustment is carried out through a first attenuator after the frequency selection is finished, the radio frequency signal after the power adjustment enters a second low noise amplifier for power amplification again, the radio frequency signal after the power amplification and a local oscillation signal from a local oscillation assembly enter a mixer for frequency mixing to obtain an intermediate frequency signal, the power of the intermediate frequency signal is adjusted through the second attenuator by the intermediate frequency signal, the intermediate frequency signal enters a second filter for filtering in sequence, power amplification is carried out by a third low noise amplifier, power adjustment is carried out again by the third attenuator, the intermediate frequency signal after the power adjustment enters an amplitude correction control circuit for amplitude correction, and then the power of the intermediate frequency signal is adjusted by a fourth attenuator, the intermediate frequency signal adjusted by the fourth attenuator enters a phase correction control circuit for phase shift control, and the intermediate frequency signal after phase adjustment is filtered and amplified by a fifth attenuator, a third filter and a fourth low noise amplifier and then is output to a receiver system.
The amplitude correction control circuit can guarantee amplitude consistency of the receiving channel, the phase correction circuit guarantees phase consistency of intermediate frequency signals in the receiving channel, in the embodiment, the phase correction circuit is placed in the intermediate frequency part, phase shifting is only same-frequency phase shifting, compared with the situation that multiple frequency points need to be considered when the phase correction circuit is placed in the radio frequency part, the method is simple and many, devices related to frequency response at one stage are reduced, and the method is beneficial to frequency response consistency of the radio frequency part. Secondly, each channel is reduced in cost, and the cost is low.
The STC control circuit is used for controlling the gain of the radio frequency signal, the STC control circuit is used for correcting the receiving channel assembly,
the local oscillator module is including connecting gradually filtering amplification module, the frequency multiplication module and merit divide the module, filtering amplification module is including the sixth attenuator that connects gradually, fourth wave filter and first amplifier, the frequency multiplication module is including the frequency multiplier that connects gradually, the seventh attenuator, fifth wave filter and fifth low noise amplifier, the merit divides the module to include first merit and divides the ware, a plurality of first merit branch circuits are connected to the output of ware is divided to first merit, first merit divides the circuit to divide the ware including the second merit that connects gradually, eighth attenuator and second amplifier. The local oscillator subassembly provides local oscillator signal for the mixer in the receiving channel subassembly, and the principle of local oscillator subassembly is: a signal source from a crystal oscillator or a DDS circuit or other modes adjusts the power of a local oscillator signal through a sixth attenuator, then the local oscillator signal is subjected to filtering amplification treatment through a fourth filter and a first amplifier in sequence, then frequency doubling is carried out through a frequency multiplier to obtain a frequency-doubled local oscillator signal, the frequency-doubled local oscillator signal is subjected to power adjustment through a seventh attenuator, then the frequency-doubled local oscillator signal is subjected to filtering amplification through a fifth filter and a fifth low-noise amplifier in sequence, the amplified frequency-doubled local oscillator signal is subjected to power average distribution through a first power divider to obtain two frequency-doubled local oscillator signals, the two frequency-doubled local oscillator signals respectively enter two first power divider circuits, the two first power divider circuits are identical in structure, a second power divider in the first power divider circuit averagely divides the power of the frequency-doubled local oscillator signal into three high local oscillator signals, and the three high local oscillator signals are subjected to filtering adjustment through an eighth attenuator, a high local oscillator signal enters a mixer of a receive channel module to be mixed. The first power divider is a two-power divider, the second power divider is a three-power divider, and the frequency multiplier is a four-frequency multiplier.
The receiver system further comprises a control module, the control module is respectively connected with the receiving channel assembly and the local oscillation assembly, the control module adopts an FPGA chip, and the FPGA chip is respectively connected with the STC control circuit, the amplitude correction control circuit and the phase correction control circuit. The FPGA chip respectively sends corresponding amplitude control codes and phase control power supplies to all channels according to different temperatures, and controls an amplitude correction control circuit and a phase correction control circuit to meet the requirements of receiving channels on amplitude consistency and phase consistency; the FPGA chip also performs data interaction with a receiver terminal, and performs amplitude adjustment and phase adjustment according to the data of the receiver terminal.
The receiver system further comprises a power supply module, the power supply module comprises a DC/DC converter, the output end of the DC/DC converter is respectively connected with a plurality of filtering isolation circuits, the filtering isolation circuits are used for isolating and filtering the power supply, and the filtering isolation circuits are respectively connected with the receiving channel assembly, the local oscillator assembly and the control module. The DC/DC converter converts input voltage into rated voltage, ensures the strand strength among channels and the interference among analog-digital, and supplies power for a plurality of channels, local oscillation assemblies and a control module through a multi-channel filtering isolation circuit after the conversion of the DC/DC converter.
The receiver system further comprises a self-checking module, the self-checking module is connected with the control module, the self-checking module comprises a frequency source, a modulator and a third power divider which are sequentially connected, the output end of the third power divider is further connected with a plurality of second power divider circuits, each second power divider circuit comprises a fourth power divider, and the output end of each fourth power divider is connected with the input end of the receiving channel assembly. The FPGA chip is provided with a self-checking enabling pin, when a self-checking enabling end is started, a self-checking module starts to work, a frequency source outputs self-checking frequency, ASK modulation is carried out according to a modulation signal transmitted by a control module to form a total self-checking signal, power distribution is carried out through a third power divider to form two paths of first self-checking signals, the two paths of first self-checking signals are respectively distributed into three paths of second self-checking signals through the fourth power divider, and the total number of 6 paths of self-checking signals respectively enter 6 paths of receiving channel assemblies to carry out self-checking. The power module also supplies power for the self-checking circuit, and the self-checking power channel is closed after the self-checking is finished. The control module controls the frequency source to work according to the self-checking enabling signal input by the receiver terminal, and outputs a modulation signal to the frequency source according to the self-checking data.
The receiver system further comprises a DDS circuit, the DDS circuit is connected with the FPGA chip, and the DDS circuit is used for providing a signal source for the local oscillation signal. The DDS circuit provides a local oscillation signal of 322.5 MHz-357.5 MHz for the local oscillation component.
The STC control circuit consists of two stages of first numerical control attenuators connected in series. The STC control circuit is connected with the FPGA chip
The phase correction control circuit comprises an analog phase shifter and a digital potentiometer, the FPGA chip is connected with the digital potentiometer, and the digital potentiometer is connected with the analog phase shifter. The specific method of the phase correction control circuit comprises the following steps:
the phase shifter is simulated, the phase shift range of the phase shifter is larger than 360 degrees, the phase shift and control of the phase shifter are shown in figure 10, under the normal condition, each channel is shifted by about 10 degrees, and each channel is adjusted to meet the requirement of consistency by adjusting voltage. That is, there is a correction margin of 10 ° without turning on the phase correction. For example, when the final correction is made to be consistent, the absolute phase shift amount is a1 … … a6 (both are less than 10 °), and when the correction is turned on, 1 channel is added as the maximum shift amount, that is, 360 ° + a 1.
The slope according to the phase shifter is approximately 25 mV/Deg. The maximum output range of the digital potentiometer is set to be 0V-9V, the digit is 9 bits, the maximum resistance value is 10K, namely the stepping is 1 change range of 512 minutes, namely 17mV, and the corresponding phase shifter change precision is 0.7 degrees. Under normal temperature, the predicted correction precision is 1.4 degrees in consideration of the workload of program correction, and the inter-channel difference is less than 3 degrees through correction in the module when external correction is not started.
In addition to the uniformity variations of the channels themselves, the temperature variations of the digital potentiometers, and the phase shifters themselves, cause uniformity variations over the entire temperature range. The device data is checked to obtain that the temperature of the digital potentiometer is converted to 500 ppm/DEG C, and the temperature of the phase shifter is converted to 0.2 DEG/DEG C. The working temperature is-10 ℃ to +70 ℃, the calculation can be carried out, the total variation of the digital potentiometer is 400 ohms, and the phase shift step is 0.78mV after each bit is converted, so the phase consistency is basically not influenced by the temperature drift of the digital potentiometer, but the total phase change amount of the phase shifter is 16 degrees at most, and temperature correction is needed.
A value is to be corrected every 5 c taking into account the workload of the temperature correction procedure. And finally adjusting the correction value under each temperature section during debugging, and making the program into a table look-up mode, wherein when the temperature reaches a certain value during subsequent work, the program automatically adjusts the correction value, so that the phase consistency in the working temperature range can meet the technical requirement, and the theoretical temperature influence error is 1 degree.
When the correction is started, SPI data sent by an upper computer is received, a phase amount required to be shifted is extracted, the FPGA outputs a corresponding control code and a correction value at the current temperature, the control code and the correction value are converted into a data format of a digital potentiometer and sent to the digital potentiometer, the digital potentiometer outputs corresponding voltage to control the phase shift of the phase shifter, and finally, the error of each step is smaller than 2 degrees in actual debugging.
The amplitude correction control circuit includes a second digitally controlled attenuator. Because the receiving and leading-in components are all linear amplification, the numerical control attenuator only needs to adopt a 6-bit numerical control attenuator with the step of 0.5 dB.
The first filter adopts an image frequency suppression filter. The image reject filter is capable of performing an image reject function on the receive path components.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The utility model provides an adopt receiver system that simulation was shifted phase, its characterized in that, includes a plurality of receiving channel subassemblies and local oscillator subassembly, the local oscillator subassembly with the receiving channel subassembly is connected, the receiving channel subassembly is including the amplitude limiter, frequency-selecting module, mixing module, the module of shifting phase and the intermediate frequency output module that connect gradually, the frequency-selecting module is including the first wave filter, STC control circuit, first low-noise amplifier, preselection filter group and the first attenuator that connect gradually, the mixing module is including the second low-noise amplifier, mixer and the second attenuator that connect gradually, the module of shifting phase is including the second wave filter, the third low-noise amplifier, the third attenuator, the amplitude correction control circuit, the fourth attenuator, the phase correction control circuit that connect gradually, the intermediate frequency output module is including the fifth attenuator, the attenuator that connect gradually, The output end of the local oscillator component is connected with the frequency mixer.
2. The receiver system with analog phase shifting according to claim 1, wherein the local oscillator component comprises a filtering and amplifying module, a frequency doubling module and a power dividing module which are sequentially connected, the filtering and amplifying module comprises a sixth attenuator, a fourth filter and a first amplifier which are sequentially connected, the frequency doubling module comprises a frequency multiplier, a seventh attenuator, a fifth filter and a fifth low noise amplifier which are sequentially connected, the power dividing module comprises a first power divider, an output end of the first power divider is connected with a plurality of first power dividing circuits, and the first power dividing circuits comprise a second power divider, an eighth attenuator and a second amplifier which are sequentially connected.
3. The receiver system with analog phase shifting according to claim 1, further comprising a control module, wherein the control module is respectively connected to the receive channel module and the local oscillator module, the control module employs an FPGA chip, and the FPGA chip is respectively connected to the STC control circuit, the amplitude correction control circuit, and the phase correction control circuit.
4. The receiver system with analog phase shifting according to claim 1, further comprising a power module, wherein the power module comprises a DC/DC converter, the output end of the DC/DC converter is connected to a plurality of filter isolation circuits respectively, the filter isolation circuits are used for isolating and filtering the power, and the filter isolation circuits are connected to the receiving channel assembly, the local oscillator assembly and the control module respectively.
5. The receiver system using analog phase shifting according to claim 3, further comprising a self-checking module, wherein the self-checking module is connected to the control module, the self-checking module includes a frequency source, a modulator, and a third power divider, which are sequentially connected to each other, an output end of the third power divider is further connected to a plurality of second power divider circuits, each of the second power divider circuits includes a fourth power divider, and an output end of the fourth power divider is connected to an output end of the receiving channel component.
6. The receiver system with analog phase shifting according to claim 3, further comprising a DDS circuit, wherein the DDS circuit is connected to the FPGA chip, and the DDS circuit is configured to provide a signal source for the local oscillator signal.
7. The receiver system with analog phase shifting of claim 1, wherein the STC control circuit consists of a first digitally controlled attenuator in two stages in series.
8. The receiver system with analog phase shifting according to claim 3, wherein the phase correction control circuit comprises an analog phase shifter and a digital potentiometer, the FPGA chip is connected to the digital potentiometer, and the digital potentiometer is connected to the analog phase shifter.
9. The receiver system with analog phase shifting of claim 1, wherein the amplitude correction control circuit comprises a second digitally controlled attenuator.
10. The receiver system employing analog phase shifting of claim 1, wherein the first filter employs an image reject filter.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113970792A (en) * | 2021-10-26 | 2022-01-25 | 福建平潭旭坤实业有限公司 | Radio wave perspective instrument receiving system and receiving method thereof |
| CN116633327A (en) * | 2023-07-20 | 2023-08-22 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
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2020
- 2020-12-23 CN CN202023146193.1U patent/CN213521866U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113970792A (en) * | 2021-10-26 | 2022-01-25 | 福建平潭旭坤实业有限公司 | Radio wave perspective instrument receiving system and receiving method thereof |
| CN113970792B (en) * | 2021-10-26 | 2024-03-08 | 福建平潭旭坤实业有限公司 | Radio wave perspective instrument receiving system and receiving method thereof |
| CN116633327A (en) * | 2023-07-20 | 2023-08-22 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
| CN116633327B (en) * | 2023-07-20 | 2023-10-10 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
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