CN213521394U

CN213521394U - Clock circuit and equipment with power down holding function

Info

Publication number: CN213521394U
Application number: CN202022188464.3U
Authority: CN
Inventors: 赵字羽; 王伟伟; 董必文
Original assignee: Kyland Technology Co Ltd
Current assignee: Kyland Technology Co Ltd
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2021-06-22
Anticipated expiration: 2030-09-29

Abstract

The utility model provides a clock circuit with power-down maintaining function, which comprises a power supply circuit, a power-down maintaining circuit and a RTC circuit; the power supply circuit comprises a power supply source, a thermistor and a one-way diode, and the power supply source is sequentially connected with the thermistor and the one-way diode in series to supply power to the RTC circuit and keep one-way charging for the power failure; the power-down holding circuit comprises a farad capacitor, one end of the farad capacitor is connected with the output end of the one-way diode, and the other end of the farad capacitor is grounded; the filter circuit is connected with the farad capacitor in parallel. The utility model discloses a power down holding circuit that farad electric capacity constitutes is as stand-by power supply, when the emergence falls the electricity, also can guarantee the synchronism of clock, for clock circuit provides long-time power down retention function.

Description

Clock circuit and equipment with power down holding function

Technical Field

The utility model relates to a fall technical field of electric holding circuit, in particular to clock circuit and equipment with fall electric holding function.

Background

An rtc (real Time clock) real-Time clock circuit is widely applied to electronic systems in various industries to provide Time reference for the systems. In many cases, when the main power supply of the system is powered down, the RTC is required to continue to operate, which requires the RTC to have a power-down maintaining function. Different industries or equipment have different requirements on the power-down holding time, for example, the power-down holding time is required to be more than two months in the general PLC industry. In common designs, in order to implement the power-down retention function, there are several schemes as follows:

one solution is to use a button cell as a backup power supply to supply power to the RTC circuit and maintain the clock when the system is powered down. The button cell has the advantages of large battery capacity and long power-down retention time. However, a significant disadvantage of using the button cell is that after the button cell is used for a long time, the button cell needs to be replaced regularly due to leakage current or consumption of electricity. Is not beneficial to the maintenance of the equipment, especially the equipment which needs to be unpacked and the battery is replaced.

In another scheme, a super capacitor or a farad capacitor is used as a standby power supply to supply power to an RTC circuit and maintain a clock when a system is powered off. As in the utility model publication No. CN105278354A and the utility model publication No. CN111025887A, both super capacitors are used as backup power sources. However, the two schemes both have the following two disadvantages, one is that the capacitor charges the series resistor, if the resistor is too small, the capacitor is easy to cause the impact current of the capacitor to be too large when being powered on, and even the capacitor cannot be normally powered on, if the resistor is too large, the capacitor charges for too long, and if the capacitor is not fully charged and is powered off, the capacity of the capacitor cannot be fully utilized. In addition, the power supply for charging the capacitor is connected with a diode in series in the middle, and the diode generates voltage drop, so that the actual maximum voltage of the capacitor is smaller than the charging voltage, and the capacity of the capacitor cannot be fully utilized.

SUMMERY OF THE UTILITY MODEL

In view of this, the main object of the present invention is to provide a clock circuit and a device with a power down maintaining function, which can solve the above problems and deficiencies, and can ensure the clock synchronization when the power down occurs, so as to provide a long time power down maintaining function for the clock circuit.

The utility model adopts the technical scheme that the clock circuit with the power-down maintaining function comprises a power supply circuit, a power-down maintaining circuit and an RTC circuit;

the power supply circuit comprises a power supply source, a thermistor and a one-way diode, and the power supply source is sequentially connected with the thermistor and the one-way diode in series to supply power to the RTC circuit and keep one-way charging for the power failure;

the power-down holding circuit comprises a farad capacitor, one end of the farad capacitor is connected with the output end of the one-way diode, and the other end of the farad capacitor is grounded;

the filter circuit is connected with the farad capacitor in parallel.

From the above, the utility model discloses a power down holding circuit that farad electric capacity constitutes is as stand-by power supply, under normal operating condition, is supplied power for it by power supply circuit to for the power down holding circuit charges, and because this power supply circuit has adopted thermistor, according to the thermistor characteristic, when charging begins, the thermistor resistance is great, and the impulse current that charges for farad electric capacity is less, along with in the charging process, thermistor charges and generates heat, and the resistance descends, guarantees that charging current can not reduce, thereby shortens electric capacity charging's time; when power failure occurs, the fully charged power failure holding circuit can supply power for the RTC circuit, and meanwhile, due to the existence of the one-way diode, current is prevented from reversely flowing to a power supply source, so that the purpose of long-time power failure holding for the clock circuit can be achieved.

In a further improvement, the power supply circuit further comprises a first resistor connected in series between the power supply and the thermistor.

Therefore, the impulse current at the moment of charging the capacitor can be adjusted by connecting the first resistor in series and adjusting the resistance value.

In a further improvement, the power supply circuit further comprises a second resistor connected in parallel with the thermistor.

Therefore, the second resistor is connected in parallel with the two ends of the thermistor, so that the current for charging the farad capacitor can be increased in the charging process.

Preferably, the filter circuit comprises a first capacitor and a second capacitor connected in parallel.

Therefore, the first capacitor and the second capacitor which are connected in parallel are adopted, and the difference of the multiple of the two capacitors is 100 times in general, so that the filtering processing of the power supply voltage can be better realized.

Preferably, the RTC circuit includes an RTC chip, and a VDD port of the RTC chip is connected to an output terminal of the unidirectional diode;

the crystal oscillator port of the RTC chip is connected with a crystal oscillator.

Therefore, the voltages output by the power supply circuit and the power-down holding circuit are both provided to a VDD port of the RTC chip after being filtered by the filter circuit, and the crystal oscillator is used for providing heartbeat signals for the RTC chip.

Preferably, the power supply circuit further comprises a magnetic bead connected in series between the power supply and the thermistor.

Therefore, the magnetic beads can be used for filtering high-frequency noise and spike interference in the voltage output by the power supply.

The utility model also provides an equipment with above-mentioned clock circuit, this equipment is connected with clock line SCL and data line SDA of clock circuit's RTC circuit.

To sum up, the beneficial effects of the utility model are that: (1) the Farad capacitor is used as a standby power supply, so that cyclic utilization can be realized, and the service life of the standby power supply is prolonged; (2) the clock circuit can still keep normal work after being powered off for many times, thereby ensuring the time synchronism; (3) after the power is re-electrified every time, the farad capacitor can be charged in time, and then a standby power supply is ensured to be available after the next power failure; (4) the charging voltage of the farad capacitor is improved, so that the stored energy of the farad capacitor is increased, and the retention time of the clock circuit after power failure can be further prolonged.

Drawings

Fig. 1 is a circuit diagram of the clock circuit with power down hold function of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings.

As shown in fig. 1, the utility model provides a clock circuit with power down maintaining function, under the normal working condition, the RTC circuit 300 is powered by the power supply circuit 100, and the power down maintaining circuit 200 composed of farad capacitor is charged at the same time; when power failure occurs, the power failure holding circuit 200 supplies power to the RTC circuit 300, so as to ensure clock synchronization and provide a long-time power failure holding function for the clock circuit. Specifically, the clock circuit includes:

the power supply VDD is connected with a VDD port of the RTC chip U1 at the rear end after being sequentially connected with the magnetic bead FB1, the thermistor RT1 and the one-way diode D1 in series, and provides required working voltage for the RTC chip U1 and peripheral circuits thereof;

one end of a farad capacitor C2 is connected with the output end of the one-way diode D1, the other end is grounded, and when the power supply VDD is in a normal working state and supplies power to the rear RTC chip U1, the farad capacitor C2 is charged; when power failure occurs, the rear end RTC chip U1 is powered by the farad capacitor C2, and the unidirectional diode D2 ensures that the current output by the farad capacitor C2 cannot reversely flow into a power supply end;

the filter circuit 400 is connected in parallel to two ends of the farad capacitor C2 and comprises capacitors C1 and C4 which are connected in parallel, and by adopting the double-layer filter capacitor structure, the filter circuit can realize the filtering treatment of most of interference in the voltage output by a power supply VDD or the farad capacitor C2 and ensure the stability of the voltage input to the RTC chip;

the crystal oscillator port of the RTC chip U1 is connected with a crystal oscillator circuit, and the clock interface and the data interface are respectively connected with external equipment through a clock line SCL and a data line SDA so as to provide clock signals and data signals for the external equipment;

according to the characteristics of the thermistor, in an initial power-on state, the resistance value of the thermistor RT1 is large, at the moment, the impact current for charging the rear-end farad capacitor C2 is small, the farad capacitor C2 is not prone to damage, in the charging process, the thermistor RT1 is charged to generate heat, the resistance value is reduced, at the moment, the charging current is gradually stabilized and keeps large current, and the time for charging the farad capacitor C2 can be shortened.

It should be noted that, because different RTC devices have different requirements for farad capacitance and charging current, a resistor R1 may be connected in series between the power supply VDD and the thermistor RT1, the resistor R1 may adopt an adjustable resistor, and the resistance value in the initial state is 0, according to the system requirement, when the current output from the power supply VDD is large, the resistance value of the resistor R1 may be increased, so as to reduce the current for charging the back-end pull capacitor C2; similarly, when the charging current needs to be increased, the resistor R4 may be connected in parallel with the two ends of the thermistor RT1, and the current for charging the back-end pull-out capacitor C2 may be increased by adjusting the resistance of the resistor R4.

According to the maximum working voltage (generally 5.5V) of the RTC chip in the normal state, the output voltage of the power supply can be improved by adjusting the feedback resistor on the power supply, the output voltage is improved to 5.3V (which cannot exceed the RTC chip) from the conventional 5V, so that the charged voltage of the farad capacitor is increased, the stored energy of the farad capacitor is increased, and the holding time of the clock circuit after power failure can be further prolonged.

Continuing to refer to fig. 1, the utility model provides a clock circuit with power down retention function, the theory of operation is:

when the power supply is normally powered, the power supply VDD outputs voltage, and after filtering processing of filtering capacitors C1 and C4, the power supply is used for supplying power to the RTC chip and the peripheral circuit thereof at the rear end, and meanwhile, the power supply VDD also charges a farad capacitor C2;

when power failure occurs, the farad capacitor C2 outputs voltage, and the voltage is filtered by the filter capacitors C1 and C4 to supply power to the RTC chip and peripheral circuits at the rear end, and meanwhile, the unidirectional diode D1 can prevent the current output by the farad capacitor C2 from reversely flowing into the power supply VDD end.

To sum up, the utility model discloses following technological effect has: (1) the Farad capacitor is used as a standby power supply, so that cyclic utilization can be realized, and the service life of the standby power supply is prolonged; (2) the clock circuit can still keep normal work after being powered off for many times, thereby ensuring the time synchronism; (3) after the power is re-electrified every time, the farad capacitor can be charged in time, and then a standby power supply is ensured to be available after the next power failure; (4) the charging voltage of the farad capacitor is improved, so that the stored energy of the farad capacitor is increased, and the retention time of the clock circuit after power failure can be further prolonged.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A clock circuit with a power-down holding function is characterized by comprising a power supply circuit, a power-down holding circuit and an RTC circuit;

the filter circuit is connected with the farad capacitor in parallel.

2. The clock circuit of claim 1, wherein the power supply circuit further comprises a first resistor connected in series between the power supply and the thermistor.

3. The clock circuit of claim 1, wherein the power supply circuit further comprises a second resistor in parallel with the thermistor.

4. The clock circuit of claim 1, wherein the filter circuit comprises a first capacitor and a second capacitor connected in parallel.

5. The clock circuit of claim 1, wherein the RTC circuit comprises an RTC chip having a VDD port connected to the output of the unidirectional diode;

6. The clock circuit of claim 1, wherein the power supply circuit further comprises a magnetic bead connected in series between the power supply and the thermistor.

7. A device having a clock circuit as claimed in any one of claims 1 to 6, characterized in that the device is connected to a clock line SCL and a data line SDA of an RTC circuit of the clock circuit.