CN213482935U

CN213482935U - Circuit for executing Hash algorithm, computing chip and encrypted currency mining machine

Info

Publication number: CN213482935U
Application number: CN202023083500.6U
Authority: CN
Inventors: 范志军; 薛可; 许超; 杨作兴
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-06-18
Anticipated expiration: 2030-12-18

Abstract

The present disclosure relates to a circuit, a computing chip and a cryptocurrency mining machine that perform a hash algorithm. A circuit for performing a hash algorithm comprising: a plurality of operation stages arranged in a pipeline structure, each including 0 th to 15 th extension registers for storing extension data of a current operation stage; and a plurality of extended data operation logic blocks, each of which is disposed between two adjacent operation stages including a first operation stage and a subsequent second operation stage, and includes a first submodule for calculating extended data in a 0 th extended register of the second operation stage based on extended data in a 1 st extended register of the first operation stage and a second submodule for calculating extended data in a 15 th extended register of the second operation stage based on extended data in a 0 th extended register of the first operation stage, wherein extended data in an (i-1) th extended register of the second operation stage is extended data in an i th extended register of the first operation stage, i is 2 ≦ i ≦ 15, and i is an integer.

Description

Circuit for executing Hash algorithm, computing chip and encrypted currency mining machine

Technical Field

The present disclosure relates generally to circuits, computing chips, and cryptocurrency machines for performing hash algorithms.

Background

Bitcoin is a virtual encrypted digital currency in the form of P2P (Peer-to-Peer), the concept of which was originally proposed by the minwis at 11/1 of 2008 and was formally born at 3/1 of 2009. The bitcoin is unique in that it is not issued by a specific currency institution, but is generated by a large number of operations according to a specific algorithm. Bitcoin transactions use a distributed database of numerous nodes throughout the P2P network to validate and record all transactions and use cryptographic designs to ensure security. From a cryptographic perspective, Bibitcoin is a workload proof POW (proof of work) based on SHA-256 hashing algorithm, and its transaction integrity depends on the collision and pre-image resistance of SHA-256. The hash algorithm is an algorithm that takes variable-length data as input and produces a fixed-length hash value as output, and is essentially a refinement of information. Since 1993, the institute of standards and technology has designed and released several versions of the secure Hash algorithm SHA (secure Hash algorithm), where SHA-256 is one of the secure Hash algorithms with a Hash length of 256 bits.

The core of the mining machine for bitcoin excavation is to obtain the reward according to the computing capability of the mining machine to calculate SHA-256. For a mining machine, chip size, chip running speed and chip power consumption are three factors which are crucial to determining the performance of the mining machine, wherein the chip size determines the chip cost, the speed of chip running determines the running speed of the mining machine, namely computational power, and the chip power consumption determines the power consumption degree, namely the mining cost. In practical applications, the most important performance index for measuring the mining machine is the power consumption consumed by a unit computing power, i.e., a power computing power ratio. To improve security, SHA-256 is performed twice in the bitcoin protocol. Therefore, for bitcoin machines, it is most important to implement the hash algorithm SHA-256 with a low power consumption computation ratio.

SUMMERY OF THE UTILITY MODEL

According to a first aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each operation stage of the plurality of operation stages including 0 th to 15 th extension registers, each extension register configured to store extension data of a current operation stage; and a plurality of extended data arithmetic logic modules, each extended data arithmetic logic module disposed between a respective adjacent two of the plurality of arithmetic stages, the adjacent two arithmetic stages including a first arithmetic stage and a second arithmetic stage subsequent to the first arithmetic stage, each extended data arithmetic logic module comprising: a first submodule configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register of the first operation stage; and a second submodule configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on the extension data stored in a 0 th extension register of the first operation stage, wherein the extension data for storage into an (i-1) th extension register of the second operation stage is the extension data stored in an i th extension register of the first operation stage, where 2 ≦ i ≦ 15 and i is an integer.

According to a second aspect of the present disclosure, there is provided a circuit for performing a hash algorithm, comprising: an input module configured to receive data; and an operation module configured to calculate a hash value based on the received data, the operation module comprising: a plurality of operation stages arranged in a pipeline structure, each of the operation stages including 0 th to 15 th extension registers each configured to store extension data of a current operation stage and an additional register configured to store intermediate data for calculating the extension data; and a plurality of extended data arithmetic logic modules, each extended data arithmetic logic module disposed between a respective adjacent two of the plurality of arithmetic stages, the adjacent two arithmetic stages including a first arithmetic stage and a second arithmetic stage subsequent to the first arithmetic stage, each extended data arithmetic logic module comprising: a first submodule configured to calculate intermediate data for storage into an additional register of a second operation stage based on extension data stored in an extension register of a first operation stage; and a second submodule configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on the intermediate data stored in the additional register of the first operation stage, wherein the extension data for storage into an (i-1) th extension register of the second operation stage is extension data stored in an ith extension register of the first operation stage, where 1 ≦ i ≦ 15 and i is an integer.

According to a third aspect of the present disclosure, there is provided a computing chip comprising a circuit as described in the above aspect.

According to a fourth aspect of the present disclosure there is provided a cryptocurrency mining machine comprising one or more computing chips as described in the above aspects.

Other features of the present disclosure and advantages thereof will become more apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm;

FIG. 2 schematically illustrates conventional arithmetic logic between extended data in extended registers of two adjacent arithmetic stages in the pipeline structure of FIG. 1;

FIG. 3 shows a schematic block diagram of a circuit for performing a hashing algorithm, in accordance with some embodiments of the present disclosure;

4-7 schematically illustrate exemplary configurations of portions of the circuit shown in FIG. 3 that include extended data arithmetic logic blocks, according to embodiments of the present disclosure;

FIG. 8 shows a schematic block diagram of a circuit for performing a hashing algorithm in accordance with some embodiments of the present disclosure;

9-14 schematically illustrate exemplary configurations of portions of the circuit shown in FIG. 8 that include extended data arithmetic logic blocks, according to embodiments of the present disclosure; and

fig. 15 and 16 show exemplary flow diagrams of methods for computing extended data according to embodiments of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. Those skilled in the art will appreciate that they are merely illustrative of ways that may be used to implement the present invention, and not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In order to more clearly and intuitively present the concepts of the present disclosure, the SHA-256 algorithm will be briefly introduced below and used as a representative example of a hash algorithm to describe a circuit and related method for performing a hash algorithm according to embodiments of the present disclosure. Those skilled in the art will appreciate that the circuitry and associated methods for performing a hashing algorithm according to embodiments of the present disclosure are applicable to any hashing algorithm and may even further be applied to any other suitable circuitry and methods, not limited solely to implementing the SHA-256 algorithm.

FIG. 1 shows a schematic diagram of an exemplary pipeline structure for performing the SHA-256 algorithm. The input to SHA-256 is a maximum length of less than 2⁶⁴The output of the data of the bits is a data digest of 256 bits, i.e., a hash value. Input data is processed in units of 512-bit data blocks. To implement the SHA-256 algorithm, 64 rounds of repeating operations are required for each 512-bit data block, so that 64 sets of data can be operated in parallel using a pipeline structure including 64 operation stages. As shown in FIG. 1, the pipeline structure includes 0 th to 63 th operation stages, each of which includes 8 32-bit compression registers A to H for storing intermediate values and 16 32-bit extension registers R for storing extension data₀To R₁₅. The 0 th operation stage may receive an input data block, divide it into 8 32-bit data, store them in the compression registers a to H, and then perform operation processing on them and supply them to the 1 st operation stage. Then, each operation stage operates the operation result of the previous operation stage received by the operation stage and provides the operation result of the operation stage to the next operation stage. Finally, after 64 operation stages, the operation core may output a hash operation result of performing the SHA-256 algorithm once on the input data.

The internal logic of a round of operation performed by SHA-256 at each operation stage is discussed in detail below. The operation of the t-th round performed on the t-th operation stage is defined by the following operation formula (t is an integer and satisfies 0 ≦ t ≦ 63):

T1＝H+∑₁(E)+Ch(E，F，G)+K_t+W_t；

T2＝∑₀(A)+Maj(A，B，C)；

H＝G；

G＝F；

F＝E；

E＝D+T1；

D＝C；

C＝B；

B＝A；

a ═ T1+ T2; (operation formula 1)

Wherein:

wherein, ROTRⁿ(x) Representing a cyclic right shift of n bits for a 32-bit variable x; w_tIs a 32-bit word derived from the current 256-bit input data block; kt is a 32-bit additional constant; + is mode 2³²Adding; AND is a 32-bit bitwise AND operation; NOT is the operation of negation;

is an exclusive or operation.

The 32-bit word W is described next_tHow it is derived from a 512-bit block of data. W_tThe following operation can be followed:

for 0 ≦ t ≦ 15: w_tDirectly from the input data block;

for 16 ≦ t ≦ 63:

W_t＝σ₁(W_t-2)+W_t-7+σ₀(W_t-15)+W_t-16(operation formula 2)

Wherein:

wherein, ROTRⁿ(x) Representing a cyclic right shift of n bits for a 32-bit variable x; SHRⁿ(x) Represents shifting the 32-bit variable x to the right by n bits, and filling 0 on the left;

is an exclusive or operation; + is mode 2³²And (4) adding.

Note that above ∑₀(x)、∑₁(x)、σ₀(x)、σ₁(x) The formula of the function is a specific form given by way of example as SHA-256 for processing 32-bit data, and those skilled in the art will appreciate that these functions may be adapted to take other corresponding forms for processing other sizes of data (e.g., 64-bit data, etc.) in other SHA algorithms (e.g., SHA-512, etc.) and even other hash algorithms.

In particular, fig. 2 shows conventional arithmetic logic between extension data in extension registers of two adjacent arithmetic stages in the pipeline structure in fig. 1. An extended register R for each operation stage needs to be used₀、R₁、R₉And R₁₄To calculate an extension register R to be stored in a subsequent operation stage₁₅In (3) extended data, additionally extended register R₁To R₁₅The extension data in (1) can be directly shifted to the corresponding extension register R of the next operation stage₀To R₁₄In (1). Specifically, the extended register R of the t +1 th operation stage₁₅Extended data w in (1)₁₅' is to ADD the extension register R of the t-th operation stage by three adders ADD1, ADD2 and ADD3₀Extended data w in (1)₀σ meridian₀The arithmetic unit carries out sigma₀Extended register R of t-th operation stage after operation₁Extended data σ in (2)₀(w₁) T-th operation stage extension register R₉Extended data w in (1)₉σ meridian₁The arithmetic unit carries out sigma₁Extended register R of t-th operation stage after operation₁₄Extended data σ in (2)₁(w₁₄) Obtained by sequential addition, i.e. w₁₅′＝w₀+σ₀(w₁)+w₉+σ₁(w₁₄). It can be seen that the extended register R from the t-th arithmetic stage₀、R₁、R₉And R₁₄Extended data w in (1)₀、w₁、w₉、w₁₄Calculating an extended register R to be stored in a subsequent arithmetic stage₁₅Extended data w in (1)₁₅' the number of arithmetic logic stages that need to be experienced is as high as 4, which brings significant computation delay, limits the operation speed of the pipeline structure, and makes it difficult to achieve a lower power consumption computation ratio.

In this regard, the inventors of the present application noted that the extended register R of the t +1 th operation stage₀And an extended register R of the tth operation stage₁The two have a direct connection relation, i.e. the extension register R of the t-th operation stage₁The extension data stored in the buffer is directly shifted to the extension register R of the t +1 th operation stage₀. The inventors of the present application thus contemplate that an extended register R may be utilized₀、R₁Will be used to calculate the extended register R of the t +2 th arithmetic stage₁₅The extension register R of the t +1 th operation stage is involved in the process of storing the extension data₀Extended data in (i.e. extended register R of the tth operation stage)₁Extended data in) is advanced toExtended register R for calculating the t +1 th arithmetic stage₁₅The process of the extended data to be stored is simultaneously carried out and stored in the extended register R of the t +1 th operation stage₀. Thus, the extended register R can be used in the t +2 th operation stage₁₅After the process of the expansion data to be stored is disassembled, the disassembled part and an expansion register R used for calculating the t +1 th operation stage are disassembled₁₅The process of expanding data to be stored in (1) is processed in parallel. By parallel processing, the number of operational logic stages required to be experienced in computing the expanded data in each round of operation can be reduced.

Accordingly, the present disclosure provides a circuit for performing a hash algorithm with an improved extended data arithmetic logic block and an improved method of calculating extended data in a circuit for performing a hash algorithm, which can reduce the number of arithmetic logic stages that need to be experienced in calculating extended data of a subsequent operation stage based on extended data of a previous operation stage between adjacent operation stages, significantly increase the arithmetic speed of the circuit and thus a computing chip including the circuit, thereby facilitating a lower power consumption arithmetic ratio.

Fig. 3 shows a schematic block diagram of a circuit 100 for performing a hashing algorithm according to some embodiments of the present disclosure, wherein the arrows represent the data transfer direction. The circuit 100 may include an input module 110 and an operation module 120. The input module 110 may be configured to receive data. The operation module 120 may be configured to calculate a hash value based on the received data. The operation module 120 may include a plurality of operation stages 120-0, 120-63 arranged in a pipeline structure, each of which may include a 0 th extended register R₀To the 15 th extension register R₁₅Each extension register may be configured to store extension data for the current operational stage.

It should be understood that while the operational module 120 is depicted in the figures as including 64 operational stages, as has been mentioned previously herein merely by way of non-limiting example of circuitry for executing the SHA-256 algorithm, circuitry in accordance with the present disclosure may be adapted to execute virtually any hashing algorithm now known or later developed for use in an mining machine (not limited to the SHA series of algorithms) and may include any suitable number of operational stages. It should also be understood that the actual circuit may also have additional other components (such as compression registers, etc.), but these are not shown in the figures and are not discussed herein to avoid obscuring the points of the present disclosure.

Typically, the 0 th extended register R of the first operational stage 120-0 of the operational module 120₀To the 15 th extension register R₁₅The extension data stored in (1) can be directly taken from the data received by the input module 110, for example, and the 0 th extension register R of each operation stage from the operation stage 120-1₀To the 15 th extension register R₁₅The extension data to be stored in (a) may be based on, for example, the 0 th extension register R of the previous operation stage₀To the 15 th extension register R₁₅The extension data stored in (c) is determined. The present disclosure mainly discusses how to extend the register R based on the 0 th extension of the previous operation stage₀To the 15 th extension register R₁₅The extension data stored in it determines the 0 th extension register R of the following operation stage₀To the 15 th extension register R₁₅To be stored.

The operational module 120 may further include a plurality of extended data operational logic modules 130, each extended data operational logic module 130 disposed between a respective adjacent two of the plurality of operational stages 120-0,... 120-63 of the operational module 120. Herein, a preceding operation stage of two adjacent operation stages may be referred to as a first operation stage and a succeeding operation stage of two adjacent operation stages may be referred to as a second operation stage, and it is noted that "first" and "second" are merely used for distinction and are not restrictive. For example, as shown in FIG. 3, an extended data operation logic module 130 is disposed between two adjacent operation stages 120-a, 120-b. Each extended data operation logic module 130 may include a first submodule 131 and a second submodule 132.

The extended data operation logic module 130 may be configured to calculate extended data for storage into an extended register of a second operation stage (e.g., 120-b) based on the extended data stored in the extended register of the first operation stage (e.g., 120-a). The first sub-module 131 may be configured to1 st extension register R based on first operation stage₁The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀The extension data of (1). The second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage₀The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1). In addition, the extension data for storage into the (i-1) th extension register of the second operation stage may be extension data stored in the ith extension register of the first operation stage, where 2 ≦ i ≦ 15 and i is an integer. That is, in the circuit 100, the 0 th extension register R of the second operation stage₀And 15 th extension register R₁₅The extended data to be stored is obtained by operating the extended data stored in the extended register of the first operation stage, and the 1 st extended register R of the second operation stage₁To the 14 th extension register R₁₄Wherein the extension data to be stored is obtained by extending the 2 nd extension register R of the first operation stage₂To the 15 th extension register R₁₅The extension data stored in each extension register in (1) is directly shifted to the 1 st extension register R of the second operation stage₁To the 14 th extension register R₁₄Is obtained by extending the register accordingly.

In some embodiments, the 15 th extension register R of an operation stage subsequent to the second operation stage₁₅The extension data stored in (1) can be based on the 1 st extension register R of the first operation stage ₁2 nd extended register R₂10 th extended register R₁₀15 th extended register R₁₅Determined by the extension data stored therein. In some embodiments, the 15 th extension register R of an operation stage subsequent to the second operation stage₁₅Is stored in₁₅", the 1 st extension register R of the first operation stage₁Is stored in₁2 nd extended register R of the first operation stage₂Is stored in₂10 th extended register R of the first operation stage₁₀Is stored in₁₀And the 15 th extended register R of the first operation stage₁₅Is stored in₁₅The following relationship can be satisfied: w is a₁₅″＝w₁+σ₀(w₂)+w₁₀+σ₁(w₁₅) Where σ is₀、σ₁And + are as defined above.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 2 nd of the first operation stage₂10 th extended register R₁₀15 th extended register R₁₅Extended data stored in one or both of them and the 1 st extended register R of the first operation stage₁The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀The extension data of (1).

In some embodiments, the second submodule 132 may be configured to extend the register R based on the 1 st extension of the first arithmetic stage₁9 th extended register R₉14 th extended register R₁₄Extended data stored in one or both of them and the 0 th extended register R of the first operation stage₀The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

Several non-limiting example configurations of portions of the circuit shown in fig. 3 including extended data operation logic modules according to embodiments of the present disclosure are described below in conjunction with fig. 4-7. In these figures, two adjacent operational stages 120-a and 120-b are illustrated as examples, and it is understood that any two adjacent operational stages in the operational block 120 may be the operational stages 120-a and 120-b discussed below. In addition, in these figures, for the sake of clarity, the first sub-module 131 and the second sub-module 132 are indicated by dashed boxes, the moving direction of the extended data that is directly shifted without undergoing an operation is indicated by dotted arrows, the moving direction of the extended data processed via the first sub-module 131 is indicated by dashed arrows, and the moving direction of the extended data processed via the second sub-module 132 is indicated by solid arrows.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And a first2 extended register R₂The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage₀9 th extended register R₉And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 4, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' is performed by processing the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁And 2 nd extended register R₂Is stored in₂And (4) obtaining the product. In particular, in this example, the first submodule 131 comprises means for performing σ₀Sigma of the operation₀An operator and an adder ADD1 for performing an addition operation in which the data w is expanded₂Is inputted to sigma₀Operator, σ₀Output of arithmetic unit and spread data w₁Is input to the adder ADD1, and the output of the adder ADD1 is supplied to the 0 th extension register R of the arithmetic stage 120-b₀So that w₀′＝w₁+σ₀(w₂)。

As further shown in FIG. 4, the 15 th extended register R of the operational stage 120-b₁₅Extended data w in (1)₁₅' is performed by processing the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀9 th extended register R₉Is stored in₉And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 132 comprises means for performing σ₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁₄Is inputted to sigma₁Operator, σ₁Output of arithmetic unit, expanded data w₀And extension data w₉Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 120-b₁₅So that w₁₅′＝w₀+w₉+σ₁(w₁₄)。

As further shown in FIG. 4, the extension data stored in the ith extension register of the operational stage 120-a is directly shifted into the (i-1) th extension register of the operational stage 120-b, where 2 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 4, the number of operational logic stages experienced by the first sub-module 131 is 2 stages, and the number of operational logic stages experienced by the second sub-module 132 is 3 stages. The first sub-module 131 and the second sub-module 132 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by the final computation of the extended data for the operational stage 120-b is reduced to 3, the computation delay is greatly reduced, and the operational speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And 10 th extension register R₁₀The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage ₀1 st extended register R₁And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 5, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' is performed by processing the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁And 10 th extension register R₁₀Is stored in₁₀And (4) obtaining the product. In particular, in this example, the first submodule 131 comprises an adder ADD1 for performing an addition operation, wherein the extension data w₁And extension data w₁₀Is input to the adder ADD1, and the output of the adder ADD1 is supplied to the 0 th extension register R of the arithmetic stage 120-b₀So that w₀′＝w₁+w₁₀。

As further shown in FIG. 5, the 15 th extended register R of the operational stage 120-b₁₅Extended data w in (1)₁₅' is performed by processing the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀1 st extended register R₁Is stored in₁And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 132 comprises means for performing σ₀Sigma of the operation₀Arithmetic unit for performing sigma₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁Is inputted to sigma₀Operator, extended data w₁₄Is inputted to sigma₁Operator, σ₀Operation and sigma₁The operations may be performed simultaneously, for example. Then, σ₀Output of arithmetic unit, sigma₁Output of arithmetic unit and spread data w₀Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 120-b₁₅So that w₁₅′＝w₀+σ₀(w₁)+σ₁(w₁₄)。

As further shown in FIG. 5, the extension data stored in the ith extension register of the operational stage 120-a is directly shifted into the (i-1) th extension register of the operational stage 120-b, where 2 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 5, the number of operational logic stages experienced by the first sub-module 131 is 1 stage, and the number of operational logic stages experienced by the second sub-module 132 is 3 stages. The first sub-module 131 and the second sub-module 132 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by the final computation of the extended data for the operational stage 120-b is reduced to 3, the computation delay is greatly reduced, and the operational speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage ₁2 nd extended register R₂And 10 th extension register R₁₀The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage₀And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 6, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' is performed by processing the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁2 nd extended register R₂Is stored in₂And 10 th extension register R₁₀Is stored in₁₀And (4) obtaining the product. In particular, in this example, the first submodule 131 comprises means for performing σ₀Sigma of the operation₀An operator and a full adder FAA and an adder ADD1 for performing an addition operation in which the data w are spread₂Is inputted to sigma₀Operator, σ₀Output of arithmetic unit, expanded data w₁And extension data w₁₀Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD1, and the output of the adder ADD1 is supplied to the 0 th extension register R of the arithmetic stage 120-b₀So that w₀′＝w₁+σ₀(w₂)+w₁₀。

As further shown in FIG. 6, the 15 th extended register R of the operational stage 120-b₁₅Extended data w in (1)₁₅' is performed by processing the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. Specifically, in this example, the second subModule 132 includes logic for performing σ₁Sigma of the operation₁An operator and an adder ADD2 for performing an addition operation in which the data w is expanded₁₄Is inputted to sigma₁Operator, σ₁Output of arithmetic unit and spread data w₀Is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 120-b₁₅So that w₁₅′＝w₀+σ₁(w₁₄)。

As further shown in FIG. 6, the extension data stored in the ith extension register of the operational stage 120-a is directly shifted into the (i-1) th extension register of the operational stage 120-b, where 2 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 6, the number of operational logic stages experienced by the first sub-module 131 is 3 stages, and the number of operational logic stages experienced by the second sub-module 132 is 2 stages. The first sub-module 131 and the second sub-module 132 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by the final computation of the extended data for the operational stage 120-b is reduced to 3, the computation delay is greatly reduced, and the operational speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And 15 th extension register R₁₅The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage ₀1 st extended register R₁And 9 th extension register R₉The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 7, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' is performed by processing the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁And 15 th extension register R₁₅Is stored in₁₅And (4) obtaining the product. In particular, in this example, the first submodule 131 comprises means for performing σ₁Sigma of the operation₁An operator and an adder ADD1 for performing an addition operation in which the data w is expanded₁₅Is inputted to sigma₁Operator, σ₁Output of arithmetic unit and spread data w₁Is input to the adder ADD1, and the output of the adder ADD1 is supplied to the 0 th extension register R of the arithmetic stage 120-b₀So that w₀′＝w₁+σ₁(w₁₅)。

As further shown in FIG. 7, the 15 th extended register R of the operational stage 120-b₁₅Extended data w in (1)₁₅' is performed by processing the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀1 st extended register R₁Is stored in₁And 9 th extension register R₉Is stored in₉And (4) obtaining the product. In particular, in this example, the second submodule 132 comprises means for performing σ₀Sigma of the operation₀An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁Is inputted to sigma₀Operator, σ₀Output of arithmetic unit, expanded data w₀And extension data w₉Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 120-b₁₅So that w₁₅′＝w₀+σ₀(w₁)+w₉。

As further shown in FIG. 7, the extension data stored in the ith extension register of the operational stage 120-a is directly shifted into the (i-1) th extension register of the operational stage 120-b, where 2 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 7, the number of operational logic stages experienced by the first sub-module 131 is 2 stages, and the number of operational logic stages experienced by the second sub-module 132 is 3 stages. The first sub-module 131 and the second sub-module 132 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by the final computation of the extended data for the operational stage 120-b is reduced to 3, the computation delay is greatly reduced, and the operational speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage ₁2 nd extended register R₂And 15 th extension register R₁₅The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage₀And 9 th extension register R₉The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1). In particular, in some examples, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' it is possible to process the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁2 nd extended register R₂Is stored in₂And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operation stage 120-b is obtained₁₅Extended data w in (1)₁₅' it is possible to process the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀And 9 th extension register R₉Is stored in₉Is obtained such that w₀′＝w₁+σ₀(w₂)+σ₁(w₁₅)，w₁₅′＝w₀+w₉。

In some embodiments, the first submodule 131 may be configured to extend the register R based on the 1 st extension of the first operation stage₁10 th extended register R₁₀And 15 th extension register R₁₅The extension data stored in (1) is calculated for storing to the 0 th extension register R of the second operation stage₀And the second submodule 132 may be configured to extend the register R based on 0 th of the first operation stage₀And 1 st extension register R₁In memoryCalculates extension data for storage into the 15 th extension register of the second arithmetic stage. In particular, in some examples, the 0 th extended register R of the operational stage 120-b₀Extended data w in (1)₀' it is possible to process the 1 st extension register R of the operation stage 120-a by the first submodule 131₁Is stored in₁10 th extended register R₁₀Is stored in₁₀And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operation stage 120-b is obtained₁₅Extended data w in (1)₁₅' it is possible to process the 0 th extension register R of the operation stage 120-a by the second sub-module 132₀Is stored in₀And 1 st extension register R₁Is stored in₁Is obtained such that w₀′＝w₁+w₁₀+σ₁(w₁₅)，w₁₅′＝w₀+σ₀(w₁)。

Accordingly, the present disclosure also provides a method of computing expanded data in a circuit for performing a hash algorithm. Fig. 13 illustrates an exemplary flow diagram of a method 300 of computing expanded data in a circuit for performing a hashing algorithm according to an embodiment of the present disclosure. Such circuitry may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage may include 0 th to 15 th extension registers, each extension register may be configured to store extension data of a current operation stage. For two adjacent arithmetic stages of the plurality of arithmetic stages of the arithmetic module, including a first arithmetic stage and a second arithmetic stage subsequent to the first arithmetic stage, the method 300 may include: at S301, based on the extension data stored in the 1 st extension register of the first operation stage, the extension data for storage into the 0 th extension register of the second operation stage is calculated; at S302, calculating extension data for storage into a 15 th extension register of a second operation stage based on the extension data stored in the 0 th extension register of the first operation stage; and at S303, the extension data stored in the ith extension register of the first arithmetic stage is taken as the extension data for storage into the (i-1) th extension register of the second arithmetic stage, wherein 2 ≦ i ≦ 15 and i is an integer. Note that S301-S303 need not be performed in a sequential order, but may be performed in any order, or may be performed at least partially in parallel.

In some embodiments, the calculation of the extension data for storage into the 0 th extension register of the second arithmetic stage and the calculation of the extension data for storage into the 15 th extension register of the second arithmetic stage may be performed simultaneously.

In some embodiments, the extension data stored in the 15 th extension register of the operation stage subsequent to the second operation stage may be determined based on the extension data stored in the 1 st extension register, the 2 nd extension register, the 10 th extension register, and the 15 th extension register of the first operation stage.

The method 300 may also calculate the extension data in various manners described above with respect to the first sub-module 131 and the second sub-module 132, which are not described herein again. The method 300 may reduce computation delays caused by computing extended data in a circuit used to perform a hash algorithm, thereby substantially increasing the operational speed of the circuit and thus a computing chip incorporating the circuit, thereby achieving a lower power consumption computation ratio.

Further, in the circuit and method according to the above-described embodiment of the present disclosure, the extension register R is used₀To store an extended register R made in advance and originally used for calculating a subsequent operation stage₁₅In which the extension register R of the preceding operational stage is involved in the process of extending the data to be stored₁Is part of the extension data. In some alternative embodiments, the extension register R may alternatively be implemented using additional registers₀The effects are played in the above embodiments. Furthermore, when additional registers are used, it is not only possible to advance the extension register R that was originally used to compute the subsequent arithmetic stages₁₅In which the extension register R of the preceding operational stage is involved in the process of extending the data to be stored₁And can be mentionedPreceding an extended register R originally used for calculating a subsequent operation stage₁₅Any suitable part of the process of expanding data to be stored.

Fig. 8 shows a schematic block diagram of a circuit 200 for performing a hashing algorithm according to some further embodiments of the present disclosure. Wherein the arrows indicate the data transfer direction. The circuit 200 may include an input module 210 and an operation module 220. The input module 210 may be configured to receive data. The operation module 220 may be configured to calculate a hash value based on the received data. The operation module 220 may include a plurality of operation stages 220-0, 220-63 arranged in a pipeline structure, each of which may include a 0 th extended register R₀To the 15 th extension register R₁₅And additional registers X, each of which may be configured to store extended data of a current operation stage, and the additional registers may be configured to store intermediate data for calculating the extended data. In some embodiments, the intermediate data stored in the additional register X of the immediately preceding operational stage 220-0 is compared with the 0 th extended register R of the immediately preceding operational stage 220-0₀The extension data stored therein may be the same.

The operational module 220 may further include a plurality of extended data operational logic modules 230, each extended data operational logic module 230 disposed between a respective adjacent two of the plurality of operational stages 220-0,... 220-63 of the operational module 220. Herein, a preceding operation stage of two adjacent operation stages may be referred to as a first operation stage and a succeeding operation stage of two adjacent operation stages may be referred to as a second operation stage, and it is noted that "first" and "second" are merely used for distinction and are not restrictive. For example, as shown in FIG. 8, an extended data operation logic module 230 is disposed between two adjacent operation stages 220-a, 220-b. Each extended data operation logic module 230 may include a first submodule 231 and a second submodule 232.

The extended data operation logic module 230 may be configured to compute for storage to a second arithmetic stage (e.g., 220-a) based on extended data stored in an extended register of the first arithmetic stage (e.g., 220-a) and intermediate data stored in an additional register of the first arithmetic stage (e.g., 220-a)220-b) and intermediate data for storing into an additional register of the second arithmetic stage. The first submodule 231 may be configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in an extension register of the first arithmetic stage. The second submodule 232 may be configured to calculate extension data for storage into the 15 th extension register of the second arithmetic stage based on intermediate data stored in the additional register of the first arithmetic stage. In addition, the extension data for storage into the (i-1) th extension register of the second operation stage may be extension data stored in the ith extension register of the first operation stage, where 1 ≦ i ≦ 15 and i is an integer. That is, in the circuit 200, the 15 th extension register R of the second operation stage₁₅Wherein the extension data to be stored is obtained by operating on the intermediate data stored in the additional register of the first operation stage, and the 0 th extension register R of the second operation stage₀To the 14 th extension register R₁₄The extension data to be stored is obtained by extending the 1 st extension register R of the first operation stage₁To the 15 th extension register R₁₅The extension data stored in each extension register in (b) is directly shifted to the 0 th extension register R of the second operation stage₀To the 14 th extension register R₁₄Is obtained by extending the register accordingly.

In some embodiments, the 15 th extension register R of an operation stage subsequent to the second operation stage₁₅The extension data stored in (1) can be based on the 1 st extension register R of the first operation stage ₁2 nd extended register R₂10 th extended register R₁₀15 th extended register R₁₅Determined by the extension data stored therein. In some embodiments, the 15 th extension register R of an operation stage subsequent to the second operation stage₁₅Is stored in₁₅", the 1 st extension register R of the first operation stage₁Is stored in₁2 nd extended register R of the first operation stage₂Is stored in₂10 th extended register R of the first operation stage₁₀Is stored in₁₀15 th extended register R of the first operation stage₁₅Is stored in₁₅The following relationship can be satisfied: w is a₁₅″＝w₁+σ₀(w₂)+w₁₀+σ₁(w₁₅) Where σ is₀、σ₁And + are as defined above.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage ₁2 nd extended register R₂10 th extended register R₁₀15 th extended register R₁₅The extension data stored in two or three of them calculates intermediate data for storage into the additional register X of the second arithmetic stage.

In some embodiments, the second submodule 232 may be configured to extend the register R based on 0 th of the first operation stage ₀1 st extended register R₁9 th extended register R₉14 th extended register R₁₄The extension data stored in one or both of them and the intermediate data stored in the additional register X of the first arithmetic stage are calculated for storage into the 15 th extension register R of the second arithmetic stage₁₅The extension data of (1).

Several non-limiting example configurations of portions of the circuit shown in fig. 8 including extended data operation logic modules according to embodiments of the present disclosure are described below in conjunction with fig. 9-14. In these figures, two adjacent operational stages 220-a and 220-b are illustrated as examples, and it is understood that any two adjacent operational stages in the operational block 220 may be the operational stages 220-a and 220-b discussed below. In addition, in these figures, for the sake of clarity, the first submodule 231 and the second submodule 232 are indicated by a dotted-line box, the moving direction of the extended data that is directly shifted without undergoing an operation is indicated by a dotted-line arrow, the moving direction of the extended data processed via the first submodule 231 is indicated by a dotted-line arrow, and the moving direction of the extended data processed via the second submodule 232 is indicated by a solid-line arrow.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And 2 nd extended register R₂Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 9 th extension register R of the first arithmetic stage₉And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 9, intermediate data w in additional register X of operational stage 220-b_x' is processed by the first submodule 231 to the 1 st extension register R of the operation stage 220-a₁Is stored in₁And 2 nd extended register R₂Is stored in₂And (4) obtaining the product. In particular, in this example, the first submodule 231 comprises means for performing σ₀Sigma of the operation₀An operator and an adder ADD1 for performing an addition operation in which the data w is expanded₂Is inputted to sigma₀Operator, σ₀Output of arithmetic unit and spread data w₁Is input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the arithmetic stage 220-b, so that w_x′＝w₁+σ₀(w₂)。

As further shown in FIG. 9, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_x9 th extended register R₉Is stored in₉And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 232 comprises means for performing σ₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁₄Is inputted to sigma₁Operator, σ₁Output of arithmetic unit, intermediate data w_xAnd extension data w₉Is input to full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+w₉+σ₁(w₁₄)。

As further shown in FIG. 9, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 9, the number of operational logic stages experienced by the first sub-module 231 is 2 stages, and the number of operational logic stages experienced by the second sub-module 232 is 3 stages. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And 10 th extension register R₁₀Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 1 st extension register R of the first arithmetic stage₁And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 10, intermediate data w in additional register X of operational stage 220-b_x' is processed by the first submodule 231 to the 1 st extension register R of the operation stage 220-a₁Is stored in₁And 10 th extension register R₁₀Is stored in₁₀And (4) obtaining the product. In particular, in this example, the first submodule 231 comprises an adder ADD1 for performing an addition operation, wherein the extension data w₁And extension data w₁₀Is input to an adder ADD1, and addedThe output of the adder ADD1 is provided to the additional register X of the arithmetic stage 220-b, so that w_x′＝w₁+w₁₀。

As further shown in FIG. 10, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_x1 st extended register R₁Is stored in₁And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 232 comprises means for performing σ₀Sigma of the operation₀Arithmetic unit for performing sigma₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁Is inputted to sigma₀Operator, extended data w₁₄Is inputted to sigma₁Operator, σ₀Operation and sigma₁The operations may be performed simultaneously, for example. Then, σ₀Output of arithmetic unit, sigma₁Output of arithmetic unit and intermediate data w_xIs input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+σ₀(w₁)+σ₁(w₁₄)。

As further shown in FIG. 10, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 10, the number of operational logic stages experienced by the first sub-module 231 is 1 stage, and the number of operational logic stages experienced by the second sub-module 232 is 3 stages. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage ₁2 nd extended register R₂And 10 th extension register R₁₀Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 14 th extension register R of the first arithmetic stage₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 11, intermediate data w in additional register X of operational stage 220-b_x' is processed by the first submodule 231 to the 1 st extension register R of the operation stage 220-a₁Is stored in₁2 nd extended register R₂Is stored in₂And 10 th extension register R₁₀Is stored in₁₀And (4) obtaining the product. In particular, in this example, the first submodule 231 comprises means for performing σ₀Sigma of the operation₀An operator and a full adder FAA and an adder ADD1 for performing an addition operation in which the data w are spread₂Is inputted to sigma₀Operator, σ₀Output of arithmetic unit, expanded data w₁And extension data w₁₀Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD1, the output of the adder ADD1 is supplied to the additional register X of the arithmetic stage 220-b, so that w_x′＝w₁+σ₀(w₂)+w₁₀。

As further shown in FIG. 11, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_xAnd 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 232 comprises means for performing σ₁Sigma of the operation₁Arithmetic unit and method for executingAdder ADD2 for row addition operation, in which data w is expanded₁₄Is inputted to sigma₁Operator, σ₁Output of arithmetic unit and intermediate data w_xIs input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+σ₁(w₁₄)。

As further shown in FIG. 11, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 11, the number of operational logic stages experienced by the first sub-module 231 is 3 stages, and the number of operational logic stages experienced by the second sub-module 232 is 2 stages. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage₁And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 1 st extension register R of the first arithmetic stage₁And 9 th extension register R₉The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 12, intermediate data w in additional register X of operational stage 220-b_x' is processed by the first submodule 231 to the 1 st extension register R of the operation stage 220-a₁Is stored in₁And 15 th extension register R₁₅Is stored in₁₅And (4) obtaining the product. In particular, in this example, the first submodule 231 is included forPerforming sigma₁Sigma of the operation₁An operator and an adder ADD1 for performing an addition operation in which the data w is expanded₁₅Is inputted to sigma₁Operator, σ₁Output of arithmetic unit and spread data w₁Is input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the arithmetic stage 220-b, so that w_x′＝w₁+σ₁(w₁₅)。

As further shown in FIG. 12, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_x1 st extended register R₁Is stored in₁And 9 th extension register R₉Is stored in₉And (4) obtaining the product. In particular, in this example, the second submodule 232 comprises means for performing σ₀Sigma of the operation₀An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁Is inputted to sigma₀Operator, σ₀Output of arithmetic unit, intermediate data w_xAnd extension data w₉Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+σ₀(w₁)+w₉。

As further shown in FIG. 12, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 12, the number of operational logic stages experienced by the first sub-module 231 is 2 stages, and the number of operational logic stages experienced by the second sub-module 232 is 3 stages. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage ₁2 nd extended register R₂And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 9 th extension register R of the first arithmetic stage₉The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1). In particular, in some examples, intermediate data w in additional register X of operational stage 220-b_x' it is possible to process the 1 st extension register R of the operation stage 220-a by the first submodule 231₁Is stored in₁2 nd extended register R₂Is stored in₂And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operational stage 220-b is obtained₁₅Extended data w in (1)₁₅' intermediate data w stored in the additional register X of the operation stage 220-a can be processed by the second submodule 232_x9 th extended register R of the AND operation stage 220-a₉Is stored in₉Is obtained such that w_x′＝w₁+σ₀(w₂)+σ₁(w₁₅)，w₁₅′＝w_x+w₉。

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 1 st extension of the first operation stage₁10 th extended register R₁₀And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 1 st extension register R of the first arithmetic stage₁The extension data stored in (b) calculates extension data for storage into the 15 th extension register of the second arithmetic stage. In particular toIn some examples, intermediate data w in additional register X of operational stage 220-b_x' it is possible to process the 1 st extension register R of the operation stage 220-a by the first submodule 231₁Is stored in₁10 th extended register R₁₀Is stored in₁₀And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operational stage 220-b is obtained₁₅Extended data w in (1)₁₅' by processing the intermediate data w in the additional register X of the operational stage 220-a by the second submodule 232_xExtended register R of AND operation stage 220-a No. 1₁Is stored in₁Is obtained such that w_x′＝w₁+w₁₀+σ₁(w₁₅)，w₁₅′＝w_x+σ₀(w₁)。

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 2 nd of the first operation stage₂And 10 th extension register R₁₀Calculates intermediate data for storage into the additional register X of the second operation stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first operation stage based on the intermediate data stored in the additional register X of the first operation stage and the 0 th extension register R of the first operation stage₀And 14 th extension register R₁₄The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 13, intermediate data w in additional register X of operational stage 220-b_x' is performed by processing the 2 nd extension register R of the operation stage 220-a by the first submodule 231₂Is stored in₂And 10 th extension register R₁₀Is stored in₁₀And (4) obtaining the product. In particular, in this example, the first submodule 231 comprises means for performing σ₀Sigma of the operation₀An operator and an adder ADD1 for performing an addition operation in which the data w is expanded₂Is inputted to sigma₀Operator, σ₀Output sum of arithmetic unitExtension data w₁₀Is input to the adder ADD1, and the output of the adder ADD1 is provided to the additional register X of the arithmetic stage 220-b, so that w_x′＝σ₀(w₂)+w₁₀。

As further shown in FIG. 13, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_x0 th extended register R₀Is stored in₀And 14 th extension register R₁₄Is stored in₁₄And (4) obtaining the product. In particular, in this example, the second submodule 232 comprises means for performing σ₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD2 for performing an addition operation in which the data w are spread₁₄Is inputted to sigma₁Operator, σ₁Output of arithmetic unit, intermediate data w_xAnd extension data w₀Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+w₀+σ₁(w₁₄)。

As further shown in FIG. 13, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 13, the number of operational logic stages experienced by the first sub-module 231 is 2 stages, and the number of operational logic stages experienced by the second sub-module 232 is 3 stages. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 2 nd of the first operation stage₂10 th extended register R₁₀And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second operation stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first operation stage based on the intermediate data stored in the additional register X of the first operation stage and the 0 th extension register R of the first operation stage₀The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1).

For example, in some examples, as shown in FIG. 14, intermediate data w in additional register X of operational stage 220-b_x' is performed by processing the 2 nd extension register R of the operation stage 220-a by the first submodule 231₂Is stored in₂10 th extended register R₁₀Is stored in₁₀And 15 th extension register R₁₅Is stored in₁₅And (4) obtaining the product. In particular, in this example, the first submodule 231 comprises means for performing σ₀Sigma of the operation₀Arithmetic unit for performing sigma₁Sigma of the operation₁An operator and a full adder FAA and an adder ADD1 for performing an addition operation in which the data w are spread₂Is inputted to sigma₀Operator, extended data w₁₅Is inputted to sigma₁Operator, σ₀The sum σ₁The operations may be performed simultaneously. Then, σ₀Output of arithmetic unit, sigma₁Output of arithmetic unit and spread data w₁₀Is input to the full adder FAA, the output of the full adder FAA is input to the adder ADD1, the output of the adder ADD1 is supplied to the additional register X of the arithmetic stage 220-b, so that w_x′＝σ₀(w₂)+w₁₀+σ₁(w₁₅)。

As further shown in FIG. 14, the 15 th extended register R of the operational stage 220-b₁₅Extended data w in (1)₁₅' is performed by processing the intermediate data w stored in the additional register X of the operation stage 220-a by the second submodule 232_xAnd 0 th extension register R₀Is stored in₀And (4) obtaining the product. Specifically, in this example, the second sub-module 232 includes an adderA law tool ADD2 in which the intermediate data w_xAnd extension data w₀Is input to the adder ADD2, and the output of the adder ADD2 is supplied to the 15 th extension register R of the arithmetic stage 220-b₁₅So that w₁₅′＝w_x+w₀。

As further shown in FIG. 14, the extension data stored in the ith extension register of the operational stage 220-a is directly shifted into the (i-1) th extension register of the operational stage 220-b, where 1 ≦ i ≦ 15 and i is an integer.

In the example shown in fig. 14, the number of operational logic stages experienced by the first sub-module 231 is 3 stages, and the number of operational logic stages experienced by the second sub-module 232 is 1 stage. The first submodule 231 and the second submodule 232 can be operated independently and in parallel, so that the number of operational logic stages required to be undergone by finally calculating the extended data for the operational stage 220-b is reduced to 3 stages, the calculation delay is greatly reduced, and the operation speed of the pipeline structure is greatly improved.

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 2 nd of the first operation stage₂And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second arithmetic stage, and the second submodule may be configured to calculate intermediate data for storage into the additional register X of the first arithmetic stage based on the intermediate data stored in the additional register X of the first arithmetic stage and the 0 th extension register R of the first arithmetic stage₀And 9 th extension register R₉The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1). In particular, in some examples, intermediate data w in additional register X of operational stage 220-b_x' the 2 nd extension register R of the operation stage 220-a can be processed by the first submodule 231₂Is stored in₂And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operational stage 220-b is obtained₁₅Extended data w in (1)₁₅' by processing the intermediate data w in the additional register X of the operational stage 220-a by the second submodule 232_xAnd 0 th extension register of operation stage 220-aStorage device R₀Is stored in₀And 9 th extension register R₉Is stored in₉Is obtained such that w_x′＝σ₀(w₂)+σ₁(w₁₅)，w₁₅′＝w_x+w₀+w₉。

In some embodiments, the first submodule 231 may be configured to extend the register R based on the 10 th extension of the first operation stage₁₀And 15 th extension register R₁₅Calculates intermediate data for storage into the additional register X of the second operation stage, and the second submodule 232 may be configured to calculate intermediate data for storage into the additional register X of the first operation stage based on the intermediate data stored in the additional register X of the first operation stage and the 0 th extension register R of the first operation stage₀And 1 st extension register R₁The 15 th extension register R stored in (1) is calculated for storage to the second arithmetic stage₁₅The extension data of (1). In particular, in some examples, intermediate data w in additional register X of operational stage 220-b_x' the arithmetic stage 220-a can be processed by the 10 th extension register R of the first submodule 231₁₀Is stored in₁₀And 15 th extension register R₁₅Is stored in₁₅The 15 th extended register R of the operational stage 220-b is obtained₁₅Extended data w in (1)₁₅' by processing the intermediate data w in the additional register X of the operational stage 220-a by the second submodule 232_xAnd 0 th extension register R of the operation stage 220-a₀Is stored in₀And 1 st extension register R₁Is stored in₁Is obtained such that w_x′＝w₁₀+σ₁(w₁₅)，w₁₅′＝w_x+w₀+σ₀(w₁)。

Accordingly, the present disclosure also provides a method of computing expanded data in a circuit for performing a hash algorithm. Fig. 14 shows an exemplary flow diagram of a method 400 of computing expanded data in a circuit for performing a hash algorithm according to an embodiment of the present disclosure. Such a circuit may include an input module configured to receive data and an operation module configured to calculate a hash value based on the received data, wherein the operation module may include a plurality of operation stages arranged in a pipeline structure, each operation stage may include 0 th to 15 th extension registers, each of which may be configured to store extension data of a current operation stage, and an additional register, which may be configured to store intermediate data for calculating the extension data. In some embodiments, the intermediate data stored in the additional register of the most previous operation stage and the extension data stored in the 0 th extension register of the most previous operation stage may be the same. For two adjacent arithmetic stages of the plurality of arithmetic stages of the arithmetic module, including a first arithmetic stage and a second arithmetic stage subsequent to the first arithmetic stage, the method 400 may include: at S401, intermediate data for storage into an additional register of a second arithmetic stage is calculated based on extension data stored in an extension register of a first arithmetic stage; at S402, calculating extension data for storage into a 15 th extension register of the second arithmetic stage based on the intermediate data stored in the additional register of the first arithmetic stage; and at S403, the extension data stored in the ith extension register of the first arithmetic stage is taken as the extension data for storage into the (i-1) th extension register of the second arithmetic stage, wherein 1 ≦ i ≦ 15 and i is an integer. Note that S401-S403 need not be performed in sequential order, but may be performed in any order, or may be performed at least partially in parallel.

In some embodiments, the calculation of intermediate data for storage into the additional register of the second arithmetic stage and the calculation of extended data for storage into the 15 th extended register of the second arithmetic stage may be performed simultaneously.

The method 400 may also calculate the extension data in various manners described above with respect to the first sub-module 231 and the second sub-module 232, which are not described herein again. The method 400 may reduce computation delays caused by computing extended data in a circuit used to perform a hash algorithm, thereby substantially increasing the operational speed of the circuit and thus a computing chip incorporating the circuit, thereby achieving a lower power consumption computation ratio.

The present disclosure may also provide a computing chip comprising a circuit as described in any of the above embodiments. The present disclosure may also provide a cryptocurrency mining machine including one or more computing chips as described above. The cryptocurrency mining machine according to the present disclosure may have a power cost ratio that enables lower power consumption, thereby performing the excavation process at a lower cost and more efficiently.

The terms "left", "right", "front", "back", "top", "bottom", "upper", "lower", "high", "low", and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. For example, features described originally as "above" other features may be described as "below" other features when the device in the drawings is inverted. The device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the relative spatial relationships may be interpreted accordingly.

In the description and claims, an element being "on," "attached" to, "connected" to, "coupled" to, or "contacting" another element, etc., may be directly on, attached to, connected to, coupled to, or contacting the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly attached to," directly connected to, "directly coupled to" or "directly contacting" another element, there are no intervening elements present. In the description and claims, one feature may be "adjacent" another feature, and the portions of one feature that overlap or are above or below the adjacent feature may be referred to.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be reproduced exactly. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the technical field, background, utility model content, or the detailed description. As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in a practical implementation.

In addition, "first," "second," and like terms may also be used herein for reference purposes only and are thus not intended to be limiting. For example, the terms "first", "second", and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context. It will be further understood that the terms "comprises/comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof. In the present disclosure, the term "providing" is used in a broad sense to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" the object, and the like.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The aspects and elements of all embodiments disclosed above may be combined in any manner and/or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A circuit for performing a hash algorithm, the circuit comprising:

an input module configured to receive data; and

an operation module configured to calculate a hash value based on the received data, the operation module comprising:

a plurality of operation stages arranged in a pipeline structure, each operation stage of the plurality of operation stages including 0 th to 15 th extension registers, each extension register configured to store extension data of a current operation stage; and

a plurality of extended data arithmetic logic modules, each extended data arithmetic logic module disposed between a respective adjacent two of the plurality of arithmetic stages, the adjacent two arithmetic stages including a first arithmetic stage and a second arithmetic stage subsequent to the first arithmetic stage, each extended data arithmetic logic module comprising:

a first submodule configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register of the first operation stage; and

a second submodule configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register of the first operation stage,

wherein the extension data for storage into the (i-1) th extension register of the second arithmetic stage is the extension data stored in the ith extension register of the first arithmetic stage, where 2 ≦ i ≦ 15 and i is an integer.

2. The circuit according to claim 1, wherein the extension data stored in the 15 th extension register of the operation stage subsequent to the second operation stage is determined based on the extension data stored in the 1 st extension register, the 2 nd extension register, the 10 th extension register, and the 15 th extension register of the first operation stage.

3. The circuit of claim 1, wherein the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second arithmetic stage based on extension data stored in one or both of a 2 nd extension register, a 10 th extension register, a 15 th extension register of the first arithmetic stage and extension data stored in a 1 st extension register of the first arithmetic stage.

4. The circuit of claim 1, wherein the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on extension data stored in one or both of a 1 st extension register, a 9 th extension register, a 14 th extension register of the first arithmetic stage and extension data stored in a 0 th extension register of the first arithmetic stage.

5. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register and a 2 nd extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register, a 9 th extension register, and a 14 th extension register of the first operation stage.

6. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register and a 10 th extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register, a 1 st extension register, and a 14 th extension register of the first operation stage.

7. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register, a 2 nd extension register, and a 10 th extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register and a 14 th extension register of the first operation stage.

8. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register and a 15 th extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register, a 1 st extension register, and a 9 th extension register of the first operation stage.

9. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register, a 2 nd extension register, and a 15 th extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register and a 9 th extension register of the first operation stage.

10. The circuit according to any one of claims 1-4,

the first submodule is configured to calculate extension data for storage into a 0 th extension register of the second operation stage based on extension data stored in a 1 st extension register, a 10 th extension register, and a 15 th extension register of the first operation stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on extension data stored in a 0 th extension register and a 1 st extension register of the first operation stage.

11. A circuit for performing a hash algorithm, the circuit comprising:

an input module configured to receive data; and

a plurality of operation stages arranged in a pipeline structure, each of the operation stages including 0 th to 15 th extension registers each configured to store extension data of a current operation stage and an additional register configured to store intermediate data for calculating the extension data; and

a first submodule configured to calculate intermediate data for storage into an additional register of the second operation stage based on extension data stored in an extension register of the first operation stage; and

a second submodule configured to calculate extension data for storage into a 15 th extension register of the second operation stage based on intermediate data stored in an additional register of the first operation stage,

wherein the extension data for storage into the (i-1) th extension register of the second arithmetic stage is the extension data stored in the ith extension register of the first arithmetic stage, where 1 ≦ i ≦ 15 and i is an integer.

12. The circuit according to claim 11, wherein the extension data stored in the 15 th extension register of the operation stage subsequent to the second operation stage is determined based on the extension data stored in the 1 st extension register, the 2 nd extension register, the 10 th extension register, and the 15 th extension register of the first operation stage.

13. The circuit of claim 11, wherein the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in two or three of a 1 st extension register, a 2 nd extension register, a 10 th extension register, and a 15 th extension register of the first arithmetic stage.

14. The circuit of claim 11, wherein the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on extension data stored in one or both of a 0 th extension register, a 1 st extension register, a 9 th extension register, a 14 th extension register of the first arithmetic stage and intermediate data stored in an additional register of the first arithmetic stage.

15. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register and a 2 nd extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 9 th extension register and a 14 th extension register of the first arithmetic stage.

16. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register and a 10 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 1 st extension register and a 14 th extension register of the first arithmetic stage.

17. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register, a 2 nd extension register and a 10 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 14 th extension register of the first arithmetic stage.

18. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 1 st extension register and a 9 th extension register of the first arithmetic stage.

19. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register, a 2 nd extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 9 th extension register of the first arithmetic stage.

20. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 1 st extension register, a 10 th extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 1 st extension register of the first arithmetic stage.

21. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 2 nd extension register and a 10 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 0 th extension register and a 14 th extension register of the first arithmetic stage.

22. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 2 nd extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 0 th extension register and a 9 th extension register of the first arithmetic stage.

23. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 2 nd extension register, a 10 th extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 0 th extension register of the first arithmetic stage.

24. The circuit according to any of claims 11-14,

the first submodule is configured to calculate intermediate data for storage into an additional register of the second arithmetic stage based on extension data stored in a 10 th extension register and a 15 th extension register of the first arithmetic stage; and

the second submodule is configured to calculate extension data for storage into a 15 th extension register of the second arithmetic stage based on intermediate data stored in an additional register of the first arithmetic stage and extension data stored in a 0 th extension register and a 1 st extension register of the first arithmetic stage.

25. A computing chip, characterized in that it comprises a circuit according to any one of claims 1-24.

26. A cryptocurrency machine, comprising one or more computing chips according to claim 25.