CN213482862U - Out-of-order processor for scheduling out-of-order queues and determining queue kill - Google Patents
Out-of-order processor for scheduling out-of-order queues and determining queue kill Download PDFInfo
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Abstract
The utility model discloses an out-of-order treater that is used for dispatching out-of-order queue and judges that the queue gets the item of canceling, include: an instruction distribution circuit; the register and the disorder queue are respectively connected with the distribution circuit and used for recording all instructions in the disorder processor; the arbitration circuit is used for comparing the sizes of the age information of the instructions in the out-of-order queue of the out-of-order processor to judge whether the instructions are old or new, and when the out-of-order queue is scheduled, the effective and oldest instruction in the queue is selected to be executed; when judging the queue cancel item, an instruction causing cancel and an instruction older than the instruction causing cancel in the queue are selected for cancel. The out-of-order processor can improve the reliability of scheduling and queue cancellation judgment, reduce the judgment complexity, reduce the judgment delay and has the characteristics of low power consumption and small area.
Description
Technical Field
The utility model relates to an out-of-order treater technical field, in particular to an out-of-order treater that is used for dispatching out-of-order queue and judging the queue and gets the item that disappears.
Background
The instructions of the out-of-order processor flow in the processor according to the sequence specified in the program when entering the out-of-order queue, and the subsequent instructions can be executed before the previous instructions as long as the execution condition is met, so that the execution speed of the instructions is improved.
In the out-of-order queue scheduling of the out-of-order processor, when a plurality of instructions in the out-of-order queue are ready, the earliest instruction on a program is preferably selected to be executed, namely, an oldest-first strategy is adopted to carry out scheduling arbitration, so that the order of the instructions needs to be judged. This is because the older instruction is, the more instructions there are, so that the oldest instruction is executed preferentially, which can effectively improve the parallelism of the instructions executed by the processor, and the oldest instruction also occupies hardware resources in the processor, including other parts such as out-of-order queues, re-order caches, write buffers (storebuffers), etc., and the older the instruction is, the earlier the older the instruction is executed, the earlier the hardware resources are released for the use of the following instruction. The out-of-order queue in the out-of-order processor comprises a transmitting queue, an access queue of each level of cache, a cache access failure queue, a consistency request queue and the like.
When the out-of-order processor is re-executed due to a branch prediction error, a memory access correlation and the like, or is cancelled due to exception caused exceptions and the like, it needs to be judged which instructions in the instructions which are not submitted in the pipeline are behind the instructions which are subjected to the branch prediction error, the instructions which are subjected to the memory access correlation and cause the re-execution or the instructions which are subjected to the exception caused exceptions, belong to the instructions which need to be cancelled together with the instructions which cause the cancellation, and the instructions are cancelled in each stage of the pipeline, re-executed, or rolled back to a specific stage of the pipeline to start the execution. To identify which instructions in the out-of-order queue are the oldest instructions and belong to the instructions that need to be scheduled preferentially, or which instructions are behind instructions with a misprediction branch, instructions with access correlation causing re-execution, or instructions with exceptions causing exceptions and belong to the instructions that need to be cancelled together with the instructions causing cancellation, it is necessary to know age information of the instructions, wherein the age information represents the order of the instructions entering the pipeline.
In the related art, when instruction age information is judged, the problem of disorder of the instruction age is easy to occur, so that the reliability of scheduling and judging queue cancellation items is reduced; and because the essence of the judgment is realized by comparison of the comparators, if the judgment speed is to be improved and the problem of confusion of the instruction age is solved, a large number of comparators are required to be added, so that the complexity, the time delay, the area and the power consumption of the processor are greatly increased.
SUMMERY OF THE UTILITY MODEL
The present invention aims at solving at least one of the technical problems in the related art to a certain extent.
Therefore, the utility model aims at providing an out-of-order treater for dispatching out-of-order queue and judging queue cancellation item can improve the reliability that dispatch and queue cancellation item were judged, reduces and judges the complexity, reduces the time delay to have the characteristics that low-power consumption and area are little.
To achieve the above objects, the present invention provides an out-of-order processor for scheduling out-of-order queues and determining queue cancellation entries, comprising: an instruction distribution circuit; the out-of-order queue is connected with the distribution circuit and used for recording register queue addresses of all instructions in the out-of-order processor; the arbitration circuit is used for comparing the sizes of the age information of the instructions in the out-of-order queue of the out-of-order processor to judge whether the instructions are old or new, and when the out-of-order queue is scheduled, the effective and oldest instruction in the queue is selected to be executed; when judging the queue cancel item, an instruction causing cancel and an instruction older than the instruction causing cancel in the queue are selected for cancel.
According to the utility model discloses a disorderly order treater for dispatching out of order queue and judgement queue cancellation item, through the top bit that the exclusive OR gate exclusive OR register queue address that increases in front of the comparator increases and the top bit that the reading pointer of register queue increases, obtain the age information of every instruction to through the new and old of comparison acquisition age, avoid appearing the chaotic problem of instruction age size when judging, improve the reliability that dispatch and queue cancellation item judge; the increased exclusive-or gate can effectively reduce the comparison times, so that the number of required comparators can be directly reduced, the judgment complexity can be reduced, the judgment delay is reduced, and the characteristics of low power consumption and small area are realized.
Further, the arbitration circuit includes: and the exclusive-OR gates are connected with the register queue addresses for recording all instructions in the out-of-order processor, wherein one input end of each exclusive-OR gate is connected with the highest bit added in front of the register queue address, the other input end of each exclusive-OR gate is connected with the highest bit added by the read pointer of the register queue, and the address obtained after exclusive-OR is used as the age information of the instruction.
Further, the arbitration circuit further comprises: and the comparator component is connected with the plurality of exclusive-OR gates and is used for judging whether the instruction age is old or new according to the age information of the instruction.
Further, the comparator assembly includes: and two input ends of each first-stage comparator are respectively connected with the output ends of two adjacent exclusive-OR gates so as to compare the age information of two instructions and judge whether the instruction age is old or new.
Further, the comparator assembly further comprises: and two input ends of the comparator from the second stage to the Nth stage are respectively connected with the output ends of the two adjacent comparators in front so as to obtain the new and old of all the instruction ages through comparison, wherein N is more than or equal to 2.
Further, the arbitration circuit further comprises: and the scheduling component is respectively connected with the out-of-order queue and the comparator component, and when the out-of-order queue is scheduled, the scheduling component selects the effective instruction with the oldest age in the queue to execute.
Further, the arbitration circuit further comprises: and the cancellation component is respectively connected with the out-of-order queue and the comparator component and is used for selecting the instruction causing cancellation and the instruction older than the instruction causing cancellation in the queue to cancel when judging that the queue cancels the item.
Further, the register is a re-order buffer or a transfer re-order buffer.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of an out-of-order processor for scheduling out-of-order queues and determining queue cancellation entries according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an arbitration circuit according to an embodiment of the present invention;
fig. 3 is a diagram illustrating a partial structure of an arbitration circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an apparatus for comparing age addresses according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an arbitration circuit for executing an out-of-order queue selection instruction according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating address generation age (age) values in an out-of-order queue arbitrated instruction reorder buffer according to an embodiment of the present invention;
fig. 7 is a schematic diagram illustrating an instruction exception cancellation judgment according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating an instruction transfer cancellation judgment according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a determination that a fixed-point dispatch queue cancels an entry due to rollback according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.
The following describes an out-of-order processor with a scheduling and determining queue cancellation entry according to an embodiment of the present invention with reference to the drawings. Specifically, fig. 1 is a schematic structural diagram of an out-of-order processor for scheduling out-of-order queues and determining queue cancellation items according to an embodiment of the present invention.
As shown in FIG. 1, an out-of-order processor 10 for scheduling out-of-order queues and determining queue dequeue entries includes: instruction dispatch circuitry 100, registers 200, out-of-order queues 300, and arbitration circuitry 400.
Wherein, all instruction registers 200 and the out-of-order queue 300 in the processor for recording out-of-order are connected with the distribution circuit; the arbitration circuit 400 is respectively connected with the register 200 and the out-of-order queue 300, the arbitration circuit 400 is used for comparing the sizes of the age information of the instructions in the out-of-order queue of the out-of-order processor to judge whether the instructions are old or new, and when the out-of-order queue is scheduled, the effective and oldest instruction in the queue is selected to be executed; when judging the queue cancel item, selecting the instruction causing cancel and the instruction with the age value newer than that of the instruction causing cancel in the queue to cancel.
It can be understood that the embodiment of the utility model provides a realize the comparison of instruction age through increasing the exclusive-or gate, because the use of exclusive-or gate has reduced the use quantity of comparator to effectively reduced the complexity that the instruction age was judged, reduced and judged the time delay, effectively improved out of order treater performance, reduction consumption, practice thrift the area.
It should be noted that, when the read pointer and the write pointer of the register queue point to the next entry in the direction of address increase, the age value in the direction of address increase is small, where the smaller the age value is, the older the age is, and the larger the age value is, the newer the age is. When the read pointer and the write pointer of the register queue point to the next entry in the direction of address decrease, the age value in the direction of address decrease is large, wherein the larger the age value, the older the age, and the smaller the age value, the newer the age.
In one embodiment of the invention, the register queue may be a reorder buffer or a transfer reorder buffer.
Further, in an embodiment of the present invention, as shown in fig. 2, the arbitration circuit 400 includes: a plurality of exclusive or gates 410, a comparator component 420, a scheduling component 430, and a cancellation component 440.
The exclusive or gates 410 are connected with register queue addresses for recording all instructions in the out-of-order processor, wherein one input end of the exclusive or gate is connected with the highest bit added in front of the register queue address, the other input end of the exclusive or gate is connected with the highest bit added by a read pointer of the register queue, and the address obtained after exclusive or is used as the age information of the instruction; the comparator component 420 is connected with a plurality of exclusive-or gates, and the comparator component 430 is used for judging whether the instruction age is old or new according to the age information of the instruction; scheduler unit 440 is coupled to out-of-order queue 300 and comparator component 420, respectively, and scheduler unit 440 selects the oldest valid instruction in the queue for execution when scheduling the out-of-order queue.
Further, in an embodiment of the present invention, the comparator assembly 420 includes: and two input ends of each first-stage comparator are respectively connected with the output ends of two adjacent exclusive-OR gates so as to compare the age information of two instructions and judge whether the instruction age is old or new.
For example, as shown in fig. 3, two exclusive or gates and a first-stage comparator are taken as an example to compare the sizes of the age information of instruction 1 and instruction 2, specifically as follows: the two exclusive-OR gates are respectively a first exclusive-OR gate and a second exclusive-OR gate, one input ends of the two exclusive-OR gates are connected with the highest bit added by the read pointer of the register queue, the other input end of the first exclusive-OR gate is connected with the highest bit added in front of the address corresponding to the instruction 1, the other input end of the second exclusive-OR gate is connected with the highest bit added in front of the address corresponding to the instruction 2, and the address obtained after exclusive-OR is used as the age information of the two instructions to be compared in size so as to judge whether the age of the instructions is old or new.
Further, the embodiment of the present invention may be used to compare the age of the user with the age of the user by using the apparatus shown in fig. 4. For example, adding a highest bit before the addresses of the re-order cache and the transfer re-order cache, using the highest bit added by the read pointer of the re-order cache, XOR the highest bits of the two addresses of the re-order cache to be compared, and using the XOR obtained address as the age information of the instruction, that is,
roqid0_cmp＝{roqid0[highestbit]^roqhead[highestbit],roqid0[highestbit-1:0]}；
roqid1_cmp＝{roqid1[highestbit]^roqhead[highestbit],roqid1[highestbit-1:0]}；
and then the Roqid0_ cmp and the Roqid1_ cmp are used for comparing the address sizes to obtain the ages of the two instructions. Wherein, roqid0[ highhestbit ] and roqid1[ highhestbit ] represent the highest bit of the two re-sequencing caches or transfer re-sequencing caches needing to be compared, roqid [ highhestbit ] represents the highest bit of the read pointer of the re-sequencing caches or transfer re-sequencing caches needing to be compared, roqid0[ highhestbit-1: 0] and roqid1[ highhestbit-1: 0] represent the addresses of the two re-sequencing caches or transfer re-sequencing caches needing to be compared from 0 to the highest bit-1, roqid0_ cmp and roqid1_ cmp represent the addresses obtained after XOR, and in FIG. 4, roqid0_ cmp [ highhestbit ] and roqid [ highhestbit ] represent the addresses obtained after XOR, and roqid 5 _ hexhestbit [ highhestbit ] and roqid 3512 _ cmp [ highhestbit ] represent the addresses obtained after XOR from 0 to the highest bit-1, and roqid 350 to 35 _ cmbit ] and the same as the addresses of the roqid 350 to the read pointer of the re-sequencing caches needing to be compared, and transfer re-sequencing caches needing to be buffer.
Further, in an embodiment of the present invention, the comparator assembly 420 further includes: and two input ends of the comparator from the second stage to the Nth stage are respectively connected with the output ends of the two adjacent comparators in front so as to obtain the new and old of all the instruction ages through comparison, wherein N is more than or equal to 2.
It can be understood that two input ends of the second-stage comparator are respectively connected with the output ends of two adjacent first-stage comparators, two input ends of the third-stage comparator are respectively connected with the output ends of two adjacent second comparators, and so on, and the first-stage comparator to the N-stage comparator are connected. It should be noted that, a person skilled in the art may design the number of comparators in each stage and the number of stages of the comparators according to the design requirement, and is not limited herein.
Example 1
For the case of instruction scheduling in an out-of-order queue, taking an 8-entry out-of-order queue as an example, each entry in the queue includes information fields used by instructions such as a valid field, a rdy field, a roqid field, and a data field. The valid field records whether the item is valid (for example, defining valid as 1 indicates valid, and valid as 0 indicates invalid); the rdy field records whether the command and data are ready (e.g., defining rdy as 1 indicates ready, i.e., reaching an executable state; rdy as 0 indicates not ready); the roqid field records the reordering cache address of the instruction and is used for generating the age information of the instruction; the data field records the command, data and other information used by the command of the item. Roqhead represents the head pointer address of the reorder buffer.
Out-of-order queues, when executed, select the instruction execution of the oldest ready entry in the queue that is valid. The judgment of the instruction age uses the added highest position of the roqid or the highest position of the roqhead corresponding to each item to obtain the corresponding instruction age information, and the instruction age with the smaller age is the oldest. The first entry with the smallest age is selected as the out-of-order queue execution entry.
As shown in FIG. 5, for an 8-entry out-of-order queue, instructions A, B, C, D, E, F, G in the queue are all valid, i.e., the valid bits are all 1. An instruction with rdy bit 1 indicates ready, i.e., instruction B, C, D, F, H is in a ready, executable state. The Roqid is the address of the instruction in the reorder buffer, the state of the instruction in the reorder buffer is shown in FIG. 6, the highest bit added by the roqhead is 1, and the age information age of the instruction is obtained by using the highest bit added by the roqhead or the highest bit added by the instruction Roqid. Roqid in fig. 5 is the value after including the most significant bit added. By comparing the sizes of the instruction ages, the arbitration obtains the instruction B with the effective instruction, the ready instruction and the minimum age value of 4 for execution.
Example 2
As shown in fig. 7, for the case of Exception cancellation caused by Exception (Exception), each instruction in the pipeline has a reorder buffer address of the instruction, i.e. a roqid number, and the instruction in the pipeline compares the highest bit added by the roqid number of the instruction in the pipeline with the age value obtained by the highest bit of the pointer roqid of the reorder buffer head, and compares the age value with the age value obtained by the highest bit of the roqid number or the highest bit of the instruction caused by Exception, and if the age of the instruction is newer than that of the instruction caused by Exception, the instruction is cancelled.
Example 3
As shown in fig. 8, for the situation that a branch misprediction causes cancellation, each instruction in the pipeline has a branch reordering cache address of the instruction, i.e. a brqid number, and the age value obtained by comparing the highest bit added by the brqid number of the instruction in the pipeline with the highest bit added by the branch reordering cache head pointer brqhead of the instruction with the age value obtained by comparing the highest bit added by the brqid number of the instruction caused by a branch misprediction with the highest bit added by the branch reordering cache head pointer of the instruction, and if the age of the instruction is newer than the instruction caused by a branch misprediction, the instruction is cancelled.
Example 4
For the rollback case, if the replay caused by the access correlation occurs, namely the address-related fetching instruction (Load) between the next related storing instruction (Store) after the storing instruction (Store) is found to be written back, the fetching instruction (Load) and the following age are all rolled back, and the rolled-back fetching instruction and all the following instructions are re-executed in the dispatch queue. The judgment of the rollback instruction is also to judge which instructions are newer than the fetch instruction causing rollback according to the age value obtained by adding the highest bit of the roqid number of the instruction or adding the highest bit of the reordering cache head pointer roqhead, and then the instructions need to be executed again. As shown in fig. 9, in the fixed point dispatch queue, the information of the obtained cancel entry is calculated according to the highest bit added by the roqid number or the highest bit added by the roqhead as the age information for comparison, and it is seen that the fixed point dispatch queue needs to be cancelled and re-executed from the 3 rd entry.
According to the utility model discloses a be used for dispatching out of order queue and judge out of order treater of queue item of cancellation, through the top bit that increases before the exclusive OR gate exclusive OR register queue address that increases before the comparator and the top bit that the reading pointer of register queue increases, obtain the age information of every instruction to through the new and old of comparison acquisition age, avoid appearing the chaotic problem of instruction age size when judging, improve the reliability of dispatching and the judgement of queue item of cancellation; the added exclusive-OR gate can effectively reduce the comparison times, so that the number of required comparators can be directly reduced, the judgment complexity can be reduced, the judgment delay is reduced, the performance of the out-of-order processor is improved, the power consumption is reduced, and the area is saved.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.
Claims (8)
1. An out-of-order processor for scheduling out-of-order queues and determining queue eliminations, comprising:
an instruction distribution circuit;
the out-of-order queue is connected with the distribution circuit and used for recording register queue addresses of all instructions in the out-of-order processor;
the arbitration circuit is used for comparing the sizes of the age information of the instructions in the out-of-order queue of the out-of-order processor to judge whether the instructions are old or new, and when the out-of-order queue is scheduled, the effective and oldest instruction in the queue is selected to be executed; when judging the queue cancel item, an instruction causing cancel and an instruction older than the instruction causing cancel in the queue are selected for cancel.
2. The out-of-order processor of claim 1, wherein the arbitration circuit comprises:
and the exclusive-OR gates are connected with the register queue addresses for recording all instructions in the out-of-order processor, wherein one input end of each exclusive-OR gate is connected with the highest bit added in front of the register queue address, the other input end of each exclusive-OR gate is connected with the highest bit added by the read pointer of the register queue, and the address obtained after exclusive-OR is used as the age information of the instruction.
3. The out-of-order processor of claim 2, wherein the arbitration circuit further comprises:
and the comparator component is connected with the plurality of exclusive-OR gates and is used for judging whether the instruction age is old or new according to the age information of the instruction.
4. An out-of-order processor as claimed in claim 3, wherein said comparator component comprises:
and two input ends of each first-stage comparator are respectively connected with the output ends of two adjacent exclusive-OR gates so as to compare the age information of two instructions and judge whether the instruction age is old or new.
5. The out-of-order processor of claim 4, wherein the comparator component further comprises:
and two input ends of the comparator from the second stage to the Nth stage are respectively connected with the output ends of the two adjacent comparators in front so as to obtain the new and old of all the instruction ages through comparison, wherein N is more than or equal to 2.
6. The out-of-order processor of claim 3, wherein the arbitration circuit further comprises:
and the scheduling component is respectively connected with the out-of-order queue and the comparator component, and when the out-of-order queue is scheduled, the scheduling component selects the effective instruction with the oldest age in the queue to execute.
7. The out-of-order processor of claim 3, wherein the arbitration circuit further comprises:
and the cancellation component is respectively connected with the out-of-order queue and the comparator component and is used for selecting the instruction causing cancellation and the instruction older than the instruction causing cancellation in the queue to cancel when judging that the queue cancels the item.
8. An out-of-order processor as claimed in claim 1, wherein said registers are re-order caches or transfer re-order caches.
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| CN116483741B (en) * | 2023-06-21 | 2023-09-01 | 睿思芯科(深圳)技术有限公司 | Order preserving method, system and related equipment for multiple groups of access queues of processor |
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