CN213426138U - IO port multiplexing circuit and household appliance control equipment - Google Patents
IO port multiplexing circuit and household appliance control equipment Download PDFInfo
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- CN213426138U CN213426138U CN202022246170.1U CN202022246170U CN213426138U CN 213426138 U CN213426138 U CN 213426138U CN 202022246170 U CN202022246170 U CN 202022246170U CN 213426138 U CN213426138 U CN 213426138U
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Abstract
The utility model relates to a IO mouth multiplex circuit and household electrical appliances controlgear, this circuit includes first power supply circuit, second power supply circuit and conduction control circuit, first power supply circuit's input and first DC power supply are connected, first DC power supply circuit's output is used for exporting first DC voltage, second DC power supply circuit's input and second DC power supply are connected, second DC power supply circuit's output is used for exporting second DC voltage, conduction control circuit's first end is connected with first power supply circuit's control end, conduction control circuit's second end is connected with IO mouth and second power supply circuit's control end respectively, can control conduction control circuit's operating condition through the IO mouth, and then control first power supply circuit and second power supply circuit's output. Therefore, the output of the two power supply circuits can be controlled through one single IO port, the multiplexing of the IO port is realized, the IO port resource is saved, meanwhile, the wiring complexity is reduced, and the mutual interference between the circuits is reduced.
Description
Technical Field
The utility model relates to an IO mouth field especially relates to an IO mouth multiplex circuit and household electrical appliances controlgear.
Background
The large and small household appliances in the current shapes and colors have the tendency of scale and standardization, and household appliance products are deeply buried in thousands of households to become necessities of life of people. As is well known, in general, electric appliances such as refrigerators, air conditioners, washing machines, dish washing machines, etc. convert commercial power into low-frequency dc power and supply the low-frequency dc power to other circuits, and an IO port controls a power switch to drive a power supply, so as to supply power to a household appliance load or a chip in a household appliance circuit.
Along with the complexity of circuit design, diversified functional requirements are higher and higher, and under the condition of fixed cost, the total amount of IO ports is limited, and in the circuit with shortage of IO port resources, if the IO port resources are insufficient, a chip needs to be newly added or more IO port chips need to be replaced, so that great tests are performed on the aspects of cost and layout circuit.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a aim at providing an IO mouth multiplexing circuit and household electrical appliances controlgear, it can utilize two way power supply circuit of an IO mouth control, multiplexing IO mouth, and then saves IO mouth resource.
In order to solve the above technical problem, an embodiment of the present invention provides the following technical solution:
in a first aspect, an embodiment of the present invention provides an IO port multiplexing circuit, including: the power supply circuit comprises a first power supply circuit, a second power supply circuit and a conduction control circuit;
the input end of the first power supply circuit is connected with a first direct current power supply, and the output end of the first power supply circuit is used for outputting a first direct current voltage;
the input end of the second power supply circuit is connected with a second direct-current power supply, and the output end of the second power supply circuit is used for outputting a second direct-current voltage;
the first end of the conduction control circuit is connected with the control end of the first power supply circuit, the second end of the conduction control circuit is connected with the IO port and the control end of the second power supply circuit respectively, the IO port is used for outputting and controlling a control signal of the working state of the conduction control circuit to control the first power supply circuit to output the first direct current voltage and control the second power supply circuit to output the second direct current voltage.
In some embodiments, the first power circuit includes a first switch control circuit and a first voltage stabilizing circuit, an input terminal of the first switch control circuit is connected to the first dc power supply, an output terminal of the first switch control circuit is connected to one end of the first voltage stabilizing circuit, a control terminal of the first switch control circuit is connected to a first terminal of the conduction control circuit, when the first switch control circuit is in a conduction state, the first power circuit outputs the first dc voltage, another end of the first voltage stabilizing circuit is connected to ground, and the first voltage stabilizing circuit is configured to stabilize the first dc voltage.
In some embodiments, the first switch control circuit includes a first MOS transistor, a gate of the first MOS transistor is connected to the first end of the conduction control circuit, a source of the first MOS transistor is connected to the first dc power supply, and a drain of the first MOS transistor is configured to output the first dc voltage.
In some embodiments, the first voltage stabilizing circuit includes a first voltage regulator tube, a negative electrode of the first voltage regulator tube is connected to the drain electrode of the first MOS tube, and a positive electrode of the first voltage regulator tube is grounded.
In some embodiments, the second power circuit includes a second switch control circuit and a second voltage stabilizing circuit, an input terminal of the second switch control circuit is connected to the second dc power supply, an output terminal of the second switch control circuit is connected to one end of the second voltage stabilizing circuit, a control terminal of the second switch control circuit is respectively connected to the second terminal of the conduction control circuit and the IO port, when the second switch control circuit is in a conduction state, the second power circuit outputs the second dc voltage, another end of the second voltage stabilizing circuit is grounded, and the second voltage stabilizing circuit is configured to stabilize the second dc voltage.
In some embodiments, the second switch control circuit includes a second MOS transistor, a gate of the second MOS transistor is connected to the second end of the conduction control circuit and the IO port, a source of the second MOS transistor is connected to the second dc power supply, and a drain of the second MOS transistor is configured to output the second dc voltage.
In some embodiments, the second voltage stabilizing circuit includes a second voltage regulator tube, a negative electrode of the second voltage regulator tube is connected to the drain of the second MOS tube, and a positive electrode of the second voltage regulator tube is grounded.
In some embodiments, the conduction control circuit includes a transistor, a base of the transistor is connected to the second dc power supply, an emitter of the transistor is connected to the IO port and the control terminal of the second power supply circuit, respectively, and a collector of the transistor is connected to the control terminal of the first power supply circuit.
In some embodiments, the first power circuit further includes a first resistor and a second resistor, the first resistor is respectively connected to the gate of the first MOS transistor and the first dc power supply, and the second resistor is respectively connected to the gate of the first MOS transistor and the first end of the conduction control circuit.
In some embodiments, the second power circuit further includes a third resistor and a fourth resistor, the third resistor is respectively connected to the second dc power supply and the gate of the second MOS transistor, and the fourth resistor is respectively connected to the gate of the second MOS transistor and the second end of the conduction control circuit.
In a second aspect, the embodiment of the present invention provides a household electrical appliance control device, including as above IO port multiplexing circuit and control circuit, control circuit includes the IO port, the IO port with IO port multiplexing circuit connects, control circuit is used for passing through IO port output control IO port multiplexing circuit's operating condition's control signal.
In various embodiments of the present invention, the IO port multiplexing circuit includes a first power circuit, a second power circuit and a conduction control circuit, wherein an input terminal of the first power circuit is connected to a first dc power source, an output terminal of the first dc power circuit is used for outputting a first dc voltage, an input terminal of the second dc power circuit is connected to a second dc power source, an output terminal of the second dc power circuit is used for outputting a second dc voltage, a first terminal of the conduction control circuit is connected to a control terminal of the first power circuit, a second terminal of the conduction control circuit is respectively connected to an IO port and a control terminal of the second power circuit, an operating state of the conduction control circuit can be controlled through the IO port, and output of the first power circuit and the second power circuit can be controlled, therefore, output of two power circuits can be controlled through a single IO port, and multiplexing of the IO port is realized, for the circuit that every power supply circuit all needs an solitary IO mouth control, this IO mouth multiplexing circuit can practice thrift IO mouth resource, reduce cost, reduces the wiring complexity between the circuit simultaneously, and then reduces the mutual interference between the circuit.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of an IO port multiplexing circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an IO port multiplexing circuit according to another embodiment of the present invention;
fig. 3 is a schematic circuit diagram of an IO port multiplexing circuit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
The utility model provides a IO mouth multiplex circuit can be used in various household electrical appliances, for example refrigerator, air conditioner, washing machine and dish washer etc. the supply voltage of above-mentioned household electrical appliances is converted into low frequency DC power supply by the commercial power usually, and low frequency DC power supply supplies with other circuits again and uses. The IO port is used for controlling the power supply of the low-frequency direct-current power supply to other circuits, generally, the single IO port controls the output of a single power supply circuit, but along with the complexity of circuit design, in an era with diversified functional requirements being higher and higher, the IO port is used as an important ring of a driving power supply, and the problem of insufficient resources can occur. In the circuit with shortage of IO port resources, if the IO port resources are insufficient, a chip needs to be added or more chips of the IO port need to be replaced, and the cost and the layout of the circuit are greatly examined, so that the IO port multiplexing becomes more and more important.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an IO port multiplexing circuit 10 according to an embodiment of the present invention, as shown in fig. 1, the IO port multiplexing circuit 10 includes a first power circuit 11, a second power circuit 12 and a conduction control circuit 13, wherein an input end of the first power circuit 11 is connected to a first dc power supply 20, an output end of the first dc power supply 20 is used for outputting a first dc voltage, an input end of the second power circuit 12 is connected to a second dc power supply 30, an output end of the second power circuit 12 is used for outputting a second dc voltage, a first end of the conduction control circuit 13 is connected to a control end of the first power circuit 11, a second end of the conduction control circuit 13 is connected to an IO port 40 and a control end of the second power circuit 12, the IO port 40 is used for outputting a control signal for controlling an operating state of the conduction control circuit 13, and therefore, some control circuits or control chips may output corresponding control signals through the IO port 40 to control the operating state of the conduction control circuit 13, so as to control the outputs of the first power supply circuit 11 and the second power supply circuit 12.
The first dc power supply 20 and the second dc power supply 30 may be obtained by converting ac power, for example, rectifying, filtering, and reducing voltage, and then obtaining a stable dc power supply by a voltage regulator. The first dc power supply 20 and the second dc power supply 30 may be dc power supplies with the same voltage value, or dc power supplies with different voltage values, and when the first dc power supply 20 and the second dc power supply 30 are dc power supplies with different voltage values, the ac power supplies may be rectified, filtered, and processed by different voltage reduction circuits to obtain different dc voltages. In one example, the first dc voltage may power the appliance load 50 and the second dc voltage may power the chip 60 in the appliance circuitry.
The single IO port 40 outputs a corresponding control signal to act on the conduction control circuit 13, so as to control the operating state of the conduction control circuit 13, and can control the outputs of the first power supply circuit 11 and the second power supply circuit 12 at the same time, and can control the on/off of the two power supply circuits at the same time. Specifically, if the IO port 40 controls the conduction control circuit 13 to be in the conduction operating state, the conduction control circuit 13 controls the first power circuit 11 to be turned on through the first end thereof, and the first dc power supply 20 outputs the first dc voltage through the output end of the first power circuit 11, and similarly, the conduction control circuit 13 controls the second power circuit 12 to be turned on through the second end thereof, and the second dc power supply 30 outputs the second dc voltage through the output end of the second power circuit 12, and if the IO port 40 controls the conduction control circuit 13 to be in the cutoff operating state, the first power circuit 11 is turned off, and the second power circuit 12 is turned off, which are not output to the outside.
Therefore, the output of two power supply circuits can be controlled through a single IO port, the multiplexing of the IO port is realized, and compared with a circuit which needs to be controlled by an independent IO port for each power supply circuit, the IO port multiplexing circuit 10 can save IO port resources, reduce the cost, reduce the wiring complexity between the circuits and further reduce the mutual interference between the circuits.
Referring to fig. 2, fig. 2 is a schematic diagram of an IO port multiplexing circuit according to an embodiment of the present invention, as shown in fig. 2, a first power circuit 11 in the IO port multiplexing circuit 10 includes a first switch control circuit 111, an input end of the first switch control circuit 111 is connected to a first dc power supply 20, an output end of the first switch control circuit 111 is used for outputting a first dc voltage, and a control end of the first switch control circuit 111 is connected to a first end of a conduction control circuit 13. Corresponding control signals can be output through the IO port 40 and act on the conduction control circuit 13 to control the working state of the conduction control circuit 13, when the conduction control circuit 13 is in the conduction state, the conduction control circuit 13 controls the first switch control circuit 111 to be in the conduction state through the first end of the conduction control circuit, and then the first direct current power supply 20 outputs the first direct current voltage through the output end of the first switch control circuit 111.
The first power circuit 11 further includes a first voltage regulator circuit 112, one end of the first voltage regulator circuit 112 is connected to the output end of the first switch control circuit 111, and the other end is grounded, and the first voltage regulator circuit 112 is configured to stabilize the first dc voltage. When the first dc power supply 20 outputs the first dc voltage through the output terminal of the first switch control circuit 111, the first voltage stabilizing circuit 112 stabilizes the voltage output from the output terminal of the first switch control circuit 111 at the first dc voltage, so as to prevent the first dc voltage from fluctuating due to fluctuation of the first dc power supply 20, and ensure the stability of the output voltage.
In some embodiments, the second power circuit 12 includes a second switch control circuit 121, an input terminal of the second switch control circuit 121 is connected to the second dc power supply 30, an output terminal of the second switch control circuit 121 is used for outputting the second dc voltage, and the second switch control terminals are respectively connected to the second terminal of the conduction control circuit 13 and the IO port 40. The IO port 40 may control an operating state of the conduction control circuit 13, and when the conduction control circuit 13 is in the conduction state, the conduction control circuit 13 controls the second switch control circuit 121 to be in the conduction state through the second terminal thereof, so that the second dc power supply 30 outputs the second dc voltage through the output terminal of the second switch control circuit 121.
The second power circuit 12 further includes a second voltage stabilizing circuit 122, one end of the second voltage stabilizing circuit 122 is connected to the output end of the second switch control circuit 121, and the other end is grounded, and the second voltage stabilizing circuit 122 is configured to stabilize a second dc voltage. When the second dc power supply 30 outputs the second dc voltage through the output terminal of the second switch control circuit 121, the second voltage stabilizing circuit 122 stabilizes the voltage output from the output terminal of the second switch control circuit 121 at the second dc voltage, so as to prevent the second dc voltage from fluctuating due to the fluctuation of the second dc power supply 30, and ensure the stability of the output voltage.
To sum up, this IO mouth multiplexing circuit 10 can realize the multiplexing of IO mouth through the output of two power supply circuit of a single IO mouth control, all needs the circuit of an solitary IO mouth control for every power supply circuit, and this IO mouth multiplexing circuit 10 can practice thrift IO mouth resource, reduces the cost, reduces the wiring complexity between the circuit simultaneously, and then reduces the interference of each other between the circuit.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of an IO port multiplexing circuit according to an embodiment of the present invention, as shown in fig. 3, the conduction control circuit 13 includes a transistor Q1, a base of the transistor Q1 is connected to the second dc power supply 30 through a resistor, an emitter of the transistor Q1 is connected to the control terminals of the IO port 40 and the second power supply circuit 12, a collector of the transistor Q1 is connected to the control terminal of the first power supply circuit 11, and a base and an emitter of the transistor Q1 are connected through a resistor. Some control devices or control chips may output different level signals PWR _ OUT through the IO port 40 to act on the emitter of the transistor Q1, so as to control the transistor Q1 to be turned on or off.
In some embodiments, the first switch control circuit 111 includes a first MOS transistor Q2, a gate of the first MOS transistor Q2 is connected to a first end of the conduction control circuit 13, specifically to a collector of the transistor Q1, a source of the first MOS transistor Q2 is connected to the first dc power supply 20, and a drain of the first MOS transistor Q2 is configured to output a first dc voltage. When the first MOS transistor Q2 is turned on, the first dc power supply 20 outputs a first dc voltage through the drain of the first MOS transistor Q2, and the size of the first dc power supply 20 can be set according to requirements. The type of the first MOS transistor Q2 may also be set as required, and in this embodiment, the first MOS transistor Q2 is a PMOS transistor.
In some embodiments, the first regulator circuit 112 includes a first regulator tube D1, a negative electrode of the first regulator tube D1 is connected to the drain of the first MOS tube Q2, and a positive electrode of the first regulator tube D1 is grounded. The first regulator tube D1 is used for stabilizing the first dc voltage.
In some embodiments, the second switch control circuit 121 includes a second MOS transistor Q3, a gate of the second MOS transistor Q3 is connected to the second terminal of the conduction control circuit 13 and the IO port 40, specifically, a gate of the second MOS transistor Q3 is connected to an emitter of the transistor Q1, a source of the second MOS transistor Q3 is connected to the second dc power supply 30, and a drain of the second MOS transistor Q3 is configured to output the second dc voltage. When the second MOS transistor Q3 is turned on, the second dc power supply 30 outputs a second dc voltage through the drain of the second MOS transistor Q3, and the size of the second dc power supply 30 can be set according to the requirement, in this embodiment, the second dc power supply 30 is 5V, the second dc voltage is 5V, and the 5V voltage can supply power to the chip 60 in the circuit. The type of the second MOS transistor Q3 may also be set as required, and in this embodiment, the second MOS transistor Q3 is a PMOS transistor.
Preferably, the first MOS transistor Q2 and the second MOS transistor Q3 are of a type with a built-in protection diode, so as to avoid damage, improve stability, and reasonably select withstand voltage according to the voltage of the first dc power supply 20 and the second dc power supply 30.
In some embodiments, the second regulator circuit 122 includes a second regulator tube D2, a negative electrode of the second regulator tube D2 is connected to the drain of the second MOS tube Q3, and a positive electrode of the second regulator tube D2 is grounded. The second regulator tube D2 is used to stabilize the second dc voltage.
In some embodiments, the first power circuit 11 further includes a first capacitor C1, the first capacitor C1 is connected in parallel with the first voltage regulator D1, and the first capacitor C1 is used for filtering the output voltage of the first MOS transistor Q2. The first power circuit 11 further includes a third voltage regulator D3, a negative electrode of the third voltage regulator D3 is connected to the first dc power supply 20, a positive electrode of the third voltage regulator D3 is connected to a gate of the first MOS transistor Q2, and the third voltage regulator D3 is used for stabilizing voltage of the first dc power supply 20. The first power circuit 11 further includes a first resistor R1 and a second resistor R2, the first resistor R1 is respectively connected to the gate of the first MOS transistor Q2 and the first dc power supply 20, the second resistor R2 is respectively connected to the gate of the first MOS transistor Q2 and the first end of the conduction control circuit 13, specifically, to the collector of the transistor Q1, the first resistor R1 is a pull-up resistor, and the second resistor R2 is used to reduce interference.
In some embodiments, the second power circuit 12 further includes a second capacitor C2, the second capacitor C2 is connected in parallel with the second regulator D2, and the second capacitor C2 is used for filtering the output voltage of the second MOS transistor Q3. The second power circuit 12 further includes a third resistor R3 and a fourth resistor R4, the third resistor R3 is respectively connected to the second dc power supply 30 and the gate of the second MOS transistor Q3, the fourth resistor R4 is respectively connected to the gate of the second MOS transistor Q3 and the second end of the conduction control circuit 13, specifically, to the emitter of the transistor Q1, that is, to the IO port 40, the third resistor R3 is a pull-up resistor, and the fourth resistor R4 is used to reduce interference.
With reference to fig. 3, the operation principle of the IO port multiplexing circuit 10 can be described as follows:
when the output signal PWR _ OUT of the IO port 40 is a high level signal (e.g. 5V), and the voltage difference between the base and the emitter of the transistor Q1 is zero, the transistor Q1 is in a cut-off operating state, if the first dc power supply 20 is 12V and the second dc power supply 30 is 5V, the gate of the first MOS transistor Q2 is at a high potential, the potential is 12V, the gate of the second MOS transistor Q3 is at a high potential, the potential is 5V, and further the first MOS transistor Q2 and the second MOS transistor Q3 are simultaneously cut off, and neither the first power supply circuit 11 nor the second power supply circuit 12 outputs a dc voltage;
when the output signal PWR _ OUT of the IO port 40 is a low level signal, a voltage difference is formed between the base and the emitter of the transistor Q1, the transistor Q1 is in a conducting operating state, the potential at the gate of the first MOS transistor Q2 is pulled low, the potential at the gate of the second MOS transistor Q3 is also pulled low, the first MOS transistor Q2 and the second MOS transistor Q3 are simultaneously conducted, the first dc power supply 20 outputs a first dc voltage of 12V through the drain of the first MOS transistor Q2, and the second dc power supply 30 outputs a second dc voltage of 5V through the drain of the second MOS transistor Q3.
To sum up, this IO mouth multiplexing circuit 10 can realize the multiplexing of IO mouth through the output of two power supply circuit of a single IO mouth control, all needs the circuit of an solitary IO mouth control for every power supply circuit, and this IO mouth multiplexing circuit 10 can practice thrift IO mouth resource, reduces the cost, reduces the wiring complexity between the circuit simultaneously, and then reduces the interference of each other between the circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments can be combined, steps can be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. An IO port multiplexing circuit, comprising: the power supply circuit comprises a first power supply circuit, a second power supply circuit and a conduction control circuit;
the input end of the first power supply circuit is connected with a first direct current power supply, and the output end of the first power supply circuit is used for outputting a first direct current voltage;
the input end of the second power supply circuit is connected with a second direct-current power supply, and the output end of the second power supply circuit is used for outputting a second direct-current voltage;
the first end of the conduction control circuit is connected with the control end of the first power supply circuit, the second end of the conduction control circuit is connected with the I O port and the control end of the second power supply circuit respectively, the IO port is used for outputting a control signal of the working state of the conduction control circuit to control the first power supply circuit to output the first direct current voltage and control the second power supply circuit to output the second direct current voltage.
2. The IO port multiplexing circuit according to claim 1, wherein the first power supply circuit includes a first switch control circuit and a first voltage stabilizing circuit, an input terminal of the first switch control circuit is connected to the first dc power supply, an output terminal of the first switch control circuit is connected to one end of the first voltage stabilizing circuit, a control terminal of the first switch control circuit is connected to a first terminal of the conduction control circuit, when the first switch control circuit is in a conduction state, the first power supply circuit outputs the first dc voltage, another end of the first voltage stabilizing circuit is grounded, and the first voltage stabilizing circuit is configured to stabilize the first dc voltage.
3. The IO port multiplexing circuit according to claim 2, wherein the first switch control circuit includes a first MOS transistor, a gate of the first MOS transistor is connected to the first end of the conduction control circuit, a source of the first MOS transistor is connected to the first dc power supply, and a drain of the first MOS transistor is configured to output the first dc voltage.
4. The IO port multiplexing circuit of claim 3, wherein the first voltage regulator circuit comprises a first voltage regulator tube, a negative electrode of the first voltage regulator tube is connected to a drain electrode of the first MOS tube, and a positive electrode of the first voltage regulator tube is grounded.
5. The IO port multiplexing circuit according to claim 1, wherein the second power supply circuit includes a second switch control circuit and a second voltage stabilizing circuit, an input terminal of the second switch control circuit is connected to the second dc power supply, an output terminal of the second switch control circuit is connected to one end of the second voltage stabilizing circuit, a control terminal of the second switch control circuit is connected to the second terminal of the conduction control circuit and the IO port, respectively, when the second switch control circuit is in a conduction state, the second power supply circuit outputs the second dc voltage, another end of the second voltage stabilizing circuit is grounded, and the second voltage stabilizing circuit is configured to stabilize the second dc voltage.
6. The IO port multiplexing circuit according to claim 5, wherein the second switch control circuit includes a second MOS transistor, a gate of the second MOS transistor is connected to the second end of the conduction control circuit and the IO port, a source of the second MOS transistor is connected to the second dc power supply, and a drain of the second MOS transistor is configured to output the second dc voltage.
7. The IO port multiplexing circuit of claim 6, wherein the second voltage regulator circuit comprises a second voltage regulator tube, a negative electrode of the second voltage regulator tube is connected to a drain electrode of the second MOS tube, and a positive electrode of the second voltage regulator tube is grounded.
8. The IO port multiplexing circuit according to any one of claims 1 to 7, wherein the conduction control circuit comprises a triode, a base of the triode is connected to the second dc power supply, an emitter of the triode is connected to the IO port and the control terminal of the second power supply circuit, respectively, and a collector of the triode is connected to the control terminal of the first power supply circuit.
9. An electrical appliance control device, comprising the IO port multiplexing circuit and the control circuit according to any one of claims 1 to 8, wherein the control circuit comprises the IO port, the IO port is connected to the IO port multiplexing circuit, and the control circuit is configured to output a control signal for controlling the operating state of the IO port multiplexing circuit through the IO port.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022246170.1U CN213426138U (en) | 2020-10-10 | 2020-10-10 | IO port multiplexing circuit and household appliance control equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022246170.1U CN213426138U (en) | 2020-10-10 | 2020-10-10 | IO port multiplexing circuit and household appliance control equipment |
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| CN213426138U true CN213426138U (en) | 2021-06-11 |
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| CN202022246170.1U Active CN213426138U (en) | 2020-10-10 | 2020-10-10 | IO port multiplexing circuit and household appliance control equipment |
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