CN213426024U - Output device capable of controlling and stably outputting root mean square voltage - Google Patents
Output device capable of controlling and stably outputting root mean square voltage Download PDFInfo
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- CN213426024U CN213426024U CN202022200247.1U CN202022200247U CN213426024U CN 213426024 U CN213426024 U CN 213426024U CN 202022200247 U CN202022200247 U CN 202022200247U CN 213426024 U CN213426024 U CN 213426024U
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Abstract
The utility model relates to a steerable output device of stable output root mean square voltage, including power supply, power Switch (SW) and PWM signal generator (100), power Switch (SW) one end connects power supply (VDD), the other end are voltage output end (OUT), another termination resistance load (R)L) (ii) a The PWM signal generator (100) is used for generating square wave signalsControlling the power Switch (SW) to be closed in an attracting mode, and enabling the voltage output end OUT to output a constant root mean square voltage Vorms; the PWM signal generator comprises an analog-to-digital converter (101) and a duty ratio generator (102), wherein a signal output end of the analog-to-digital converter (101) is connected with a signal input end of the duty ratio generator (102). The utility model discloses can export stable root mean square voltage, the root mean square voltage of output does not change along with power supply voltage.
Description
Technical Field
The utility model relates to a steerable output device of stably outputting root mean square voltage.
Background
Some temperature controlled direct current heating products in the market, the load of which is the heating wire. In order to control the temperature of the heating wire, a constant power drive is applied to the heating wire, and in order to obtain the constant power drive, a constant root mean square voltage needs to be output, such as electronic cigarette products and the like. The existing direct-current voltage output device has the defects that under different power supply voltages, the output root-mean-square voltage fluctuates greatly along with the change of the power supply voltage, and constant power driving cannot be realized.
SUMMERY OF THE UTILITY MODEL
The present invention provides an output device capable of controlling and stably outputting root mean square voltage, which outputs stable root mean square voltage, and the output root mean square voltage is not changed along with the voltage of the power supply.
The technical scheme for realizing the purpose of the utility model is as follows:
an output device capable of controlling and stabilizing an output RMS voltage, comprising a power supply, a power Switch (SW) and a PWM signal generator (100), characterized in that:
one end of the power Switch (SW) is connected with the power supply (VDD), the other end is a voltage output end (OUT), and the other end is connected with a resistor load (R)L)；
The PWM signal generator (100) is used for generating a square wave signal to control the power Switch (SW) to be attracted, so that the voltage output end OUT outputs a constant root-mean-square voltage Vorms;
the PWM signal generator comprises an analog-to-digital converter (101) and a duty ratio generator (102), wherein a signal output end of the analog-to-digital converter (101) is connected with a signal input end of the duty ratio generator (102).
Further, the analog-to-digital converter comprises a programmable voltage division unit, a first voltage division resistor (R1) and a second voltage division resistor (R2), a comparator (201) and an accumulator (202); the inverting input end of the comparator is coupled with a band-gap reference source, the non-inverting input end of the comparator is coupled with the connection end between a first voltage-dividing resistor (R1) and a second voltage-dividing resistor (R2), and the other end of the second voltage-dividing resistor (R2) is coupled with the programmable voltage-dividing unit; the output of the comparator (201) controls the accumulator, the accumulator (202) is used for accumulating the value of the constant n, and the output of the accumulator (202) controls the programmable voltage division unit and the duty cycle generator.
Further, the programmable voltage division unit comprises a resistance series unit (203) and a switch array unit (204).
Further, the resistor series unit comprises a plurality of resistors (R01) which are connected in series and have the same resistance, the switch array unit comprises a plurality of switches corresponding to the resistors (R01), the on and off of the switches are controlled by the signal output by the accumulator (202), and the switches are used for controlling the corresponding resistors (R01) to be in a short circuit state or a voltage division state.
Further, when the voltage output device is in a state of outputting a constant rms voltage Vorms, the resistance of the resistance series unit is n × R01.
Further, when the voltage output device is in a state of outputting a constant RMS voltage Vorms, the resistance of the resistance series unit (203) is n × R01+ f (n, R01),
wherein f (n, R01) is an adjustment function for adjusting the error between the constant rms voltage Vorms and a preset rms output voltage Vref;
f(n,R01)＝-k×R01，
k denotes an adjustment coefficient obtained by calculation from the value of the constant n.
Further, f (n, R01) — R01 × (b × 0.2+ c × 0.4+ d × 0.8+ e × 1.6+ f × 3.2),
converting n to a six-bit binary number, b representing a second bit of the six-bit binary number, c representing a third bit of the six-bit binary number, d representing a fourth bit of the six-bit binary number, e representing a fifth bit of the six-bit binary number, and f representing a sixth bit of the six-bit binary number.
The utility model discloses beneficial effect who has:
the utility model comprises a power supply, a power switch and a PWM signal generator, wherein one end of the power switch is connected with the power supply, the other end is a voltage output end, and the other end is connected with a resistance load; the PWM signal generator is used for generating square wave signals, and the square wave signals are used for controlling the power switch to be attracted so that the voltage output end outputs constant root-mean-square voltage Vorms. The utility model discloses a PWM signal control power switch actuation, and then the stable root mean square voltage of control output, root mean square voltage output is irrelevant with the power supply voltage change, and then realizes stable power output.
The utility model discloses a PWM signal generator includes analog-to-digital converter and duty ratio generator, analog-to-digital converter is used for obtaining the value of constant n; and the duty ratio generator generates a square wave signal output by the PWM signal generator according to the obtained value of the constant n. The utility model discloses circuit design is simple reasonable, does not need complicated circuits such as multiplier, divider.
The analog-to-digital converter comprises a programmable voltage division unit, a first voltage division resistor (R1) and a second voltage division resistor (R2), a comparator and a +1/-1 accumulator; the inverting input end of the comparator is coupled with a band-gap reference source, the non-inverting input end of the comparator is coupled with the connection end between a first voltage-dividing resistor (R1) and a second voltage-dividing resistor (R2), and the other end of the second voltage-dividing resistor (R2) is coupled with the programmable voltage-dividing unit; the output of the comparator controls the +1/-1 accumulator, the +1/-1 accumulator can accumulate to obtain the value of the constant n, and the output of the +1/-1 accumulator controls the programmable voltage division unit and the duty ratio generator; the programmable voltage division unit can perform voltage division control based on a stepping value Vref/2N, and when the voltage output device is in a state of outputting a constant root-mean-square voltage Vorms, the voltage division value at two ends of the programmable voltage division unit is nVref/2N; the preset RMS output voltage Vref is (R1+ R2)/R1 times of the bandgap reference source. The utility model discloses analog-to-digital converter is including the partial pressure unit able to programme, comparator and +1/-1 accumulator, can obtain the value of constant n through above-mentioned unit, provides the duty cycle generator, and then makes the invariable root mean square voltage Vorms of output be similar to root mean square output voltage Vref all the time, and change irrelevantly with power supply voltage, and circuit design is simple reasonable.
The analog-to-digital converter comprises a programmable voltage division unit, a first voltage division resistor (R1) and a second voltage division resistor (R2), a comparator (201) and an accumulator (202); the inverting input end of the comparator is coupled with a band-gap reference source, the non-inverting input end of the comparator is coupled with the connection end between a first voltage-dividing resistor (R1) and a second voltage-dividing resistor (R2), and the other end of the second voltage-dividing resistor (R2) is coupled with the programmable voltage-dividing unit; the output of the comparator (201) controls the accumulator, the accumulator (202) is used for accumulating the value of the constant n, the output of the accumulator (202) controls the programmable voltage division unit and the duty cycle generator; the programmable voltage division unit comprises a resistor series unit (203) and a switch array unit (204), the resistor series unit comprises a plurality of resistors (R01) which are connected in series and have the same resistance, the switch array unit comprises a plurality of switches corresponding to the resistors (R01), the on-off of the switches is controlled by a signal output by the accumulator (202), and the switches are used for controlling the corresponding resistors (R01) to be in a short-circuit or voltage division state. The utility model discloses an effective design to programming partial pressure unit able to programme in the analog to digital converter has further guaranteed the reliability that duty ratio generator obtained constant n value.
Drawings
Fig. 1 is a schematic circuit diagram of an output device capable of controlling and stably outputting rms voltage according to the present invention;
fig. 2 is a schematic circuit diagram of the PWM signal generator of the present invention;
fig. 3 is a schematic diagram of an embodiment of the programmable voltage divider of the present invention.
Detailed Description
The present invention is described in detail below with reference to the embodiments shown in the drawings, but it should be noted that these embodiments are not intended to limit the present invention, and those skilled in the art should be able to make equivalent changes or substitutions of functions, methods, or structures according to the embodiments without departing from the scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, the output device capable of controlling and stably outputting rms voltage includes a power supply VDD, and further includes a power switch SW, one end of the power switch SW is connected to the power supply VDD, the other end is a voltage output end OUT, and the other end is connected to a resistor load RL(ii) a Also included is a PWM signal generator 100, thereforThe PWM signal generator 100 is configured to generate a square wave signal, and the square wave signal is configured to control the power switch SW to be closed, so that the voltage output terminal OUT outputs a constant root-mean-square voltage Vorms.
The square wave signal output by the PWM signal generator 100 has a pulse width of nxtCLKThe period is (N + N) multiplied by TCLK，TCLKIs a clock period, N and N are respectively constant, N is greater than or equal to 2N, and
n＝(Vop-Vref)/(Vref/2N)，
in the formula, Vop is the direct current voltage at the output end when the power switch SW is closed, and the voltage is the same as the amplitude of the square wave signal output by the PWM signal generator; vref is a preset root-mean-square output voltage; Vref/2N is the step value.
The PWM signal generator comprises an analog-to-digital converter 101 and a duty cycle generator 102, wherein the analog-to-digital converter 101 is configured to obtain a value of the constant n; the duty ratio generator 102 generates a square wave signal output by the PWM signal generator according to the obtained value of the constant n.
As shown in fig. 2, the analog-to-digital converter includes a programmable voltage dividing unit, a first voltage dividing resistor R1 and a second voltage dividing resistor R2, a comparator 201 and a +1/-1 accumulator 202; the inverting input terminal of the comparator 201 is coupled to a bandgap reference source, the non-inverting input terminal is coupled to a connection terminal between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the other terminal of the second voltage-dividing resistor R2 is coupled to the programmable voltage-dividing unit; the output of the comparator 201 controls the +1/-1 accumulator 202, the +1/-1 accumulator 202 can accumulate to obtain the value of the constant n, and the output of the +1/-1 accumulator 202 controls the programmable voltage division unit and the duty cycle generator 102.
As shown in fig. 2 and 3, the programmable voltage divider unit includes a resistor series unit 203 and a switch array unit 204, the resistor series unit is formed by connecting a plurality of identical resistors in series, that is, the resistances of the resistors R01 to ROX are identical, and R01 is (R1+ R2)/2N; the switch array unit 204 includes a plurality of switches corresponding to the resistors, i.e., switches SW1 to SWX, the on/off of which is controlled by the signal output from the +1/-1 accumulator 202, and the switches are used for controlling the corresponding resistors to be in a short-circuit or voltage-dividing state. The programmable voltage division unit can perform voltage division control based on a stepping value Vref/2N, and when an output device capable of controlling stable output of the root-mean-square voltage is in a state of outputting a constant root-mean-square voltage Vorms, the voltage division value at two ends of the programmable voltage division unit is nVref/2N. The preset root-mean-square output voltage Vref is (R1+ R2)/R1 times of the band gap reference source, R1 represents the resistance value of the resistor (R1), and R2 represents the resistance value of the resistor (R2). When the voltage output device is in a state of outputting a constant root mean square voltage Vorms, the resistance of the resistance series unit is n × R01. In this embodiment, N takes the value of 128 and N takes the value of 64.
The working principle of the present invention is further explained below.
Operating principle of (one) volt (approximately) equal to Vref
The output terminal OUT of the device is of pulse width NxTCLKPeriod (N + N) × TCLKA square wave is output and the pulse amplitude is Vop. The pulse amplitude Vop is smaller than the power supply VDD in consideration of the voltage drop at the closing of the power switch SW. At this time, the output root-mean-square voltage Vorms is:
Vorms＝Vop×[N/(N+n)]1/2 (1)
and the analog-to-digital converter converts (Vop-Vref) into a digital signal N by taking Vref/2N as a step, then:
n＝(Vop-Vref)/(Vref/2N) (2)
in this way,
Vop＝Vref×(1+n/2N) (3)
when formula (3) is substituted for formula (1), it is possible to obtain:
Vorms＝Vref×[(1+n/2N)2/(1+n/N)]1/2 (4)
finishing to obtain:
Vorms＝Vref×[1+(n2/4N(N+n)]1/2 (5)
when N < N, (N)21/4N (N + N). The following can be obtained:
Vorms＝Vref (6)
for example, when N is 2N, it can be obtained from formula (5): the Vorms is 1.0206 × Vref. It can be seen that the calculation error is only 2.06% when the Vorms is Vref. And the output root mean square voltage Vorms of the output end is not limited by the power supply. However, the Vop/Vref is not more than 1.22 due to the limitation of N.gtoreq.2N.
(II) working principle of analog-to-digital converter for obtaining value of constant n
When the comparator 201 outputs a high level, the +1/-1 accumulator 202 performs +1 operation; when the comparator 201 outputs a low level, the +1/-1 accumulator 202 operates as-1. Therefore, the resistors R1 and R2, the comparator 201, +1/-1 accumulator 202, the resistor series unit 203, and the switch array unit 204 constitute an analog-to-digital converter that converts (Vop-Vref) to a constant N in steps of Vref/2N.
When the output of the +1/-1 accumulator 202 is 0, the resistance across the resistor series unit 203 is 0 at this time. If Vop > Vref, the +1/-1 accumulator 202 is operated at +1 when the comparator 201 outputs high; if Vop < Vref, the comparator 201 outputs a low level, the +1/-1 accumulator 202 is operated as-1. When the circuit is balanced, Vop is Vref.
When the output of the +1/-1 accumulator 202 is 1, the resistance across the resistor series unit 203 is now R01. If Vop > Vref (1+1/2N), when the comparator 201 outputs high level, the +1/-1 accumulator 202 is operated as + 1; if Vop < Vref (1+1/2N), the comparator 201 outputs a low level, and the +1/-1 accumulator 202 is operated as-1. When the circuit is balanced, Vop becomes Vref (1+ 1/2N).
By analogy, when the output of the +1/-1 accumulator 202 is N, Vop is Vref (1+ N/2N) if the circuit is balanced.
The analog-to-digital converter can convert (Vop-Vref) into a constant N in Vref/2N steps.
Example two:
the second embodiment is different from the first embodiment only in that the resistance series unit of the analog-to-digital converter is different, and the rest circuit structure and the working principle are the same. When the voltage output device is in a state of outputting a constant root mean square voltage Vorms, the resistance of the resistance series unit is n multiplied by R01+ f (n, R01), and f (n, R01) is an adjusting function for adjusting an error between the constant root mean square voltage Vorms and a preset root mean square output voltage Vref.
f(n,R01)＝-k R01，
k denotes an adjustment coefficient obtained by calculation from the value of the constant n.
In this example, f (n, R01) ═ R01 × (a × R01+ b × 1.8+ c × 3.6+ d × 7.2+ e × 14.4+ f × 28.8) -R01 × (a × R01+ b × 2.0+ c × 4.0+ d × 8.0+ e × 16.0+ f × 32.0)
＝-R01×(b×0.2+c×0.4+d×0.8+e×1.6+f×3.2)
That is, k is b × 0.2+ c × 0.4+ d × 0.8+ e × 1.6+ f × 3.2
Converting the constant n into a six-bit binary number, b representing a second bit of the six-bit binary number, c representing a third bit of the six-bit binary number, d representing a fourth bit of the six-bit binary number, e representing a fifth bit of the six-bit binary number, and f representing a sixth bit of the six-bit binary number.
For example, if n is 10 and n is converted to a six-bit binary number 001010, i.e., a is 0, b is 1, c is 0, d is 1, e is 0, and f is 0, then f (n, R01) is:
R01×(a×R01+b×1.8+c×3.6+d×7.2+e×14.4+f×28.8)
＝R01×(0×R01+1×1.8+0×3.6+1×7.2+0×14.4+0×28.8)
＝9.0×R01
when N is 128, N is 64, Vref is 3.30V, Vop is 3.30 to 4.03V, and load resistance RL is 1 Ω, it can be obtained:
in the above table, n represents the n value of R01 × (a × R01+ b × 2.0+ c × 4.0+ d × 8.0+ e × 16.0+ f × 32.0) corresponding to binary fedcba;
n 'represents the value of n' for R01 × (a × R01+ b × 1.8+ c × 3.6+ d × 7.2+ e × 14.4+ f × 28.8) corresponding to binary fedcba.
Po is the power generated by the output square wave under the load of 1 ohm, VoAV represents the average voltage of the output square wave
The above table gives: when the series resistance is not corrected, the relative error of the output power is 4.04%, and after the series resistance is corrected, the relative error of the output power is 1.21%.
The above list of details is only for the practical implementation of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent implementations or modifications that do not depart from the technical spirit of the present invention should be included in the scope of the present invention.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (5)
1. An output device capable of controlling and stabilizing an output RMS voltage, comprising a power supply, a power Switch (SW) and a PWM signal generator (100), characterized in that:
one end of the power Switch (SW) is connected with the power supply (VDD), the other end is a voltage output end (OUT), and the other end is connected with a resistor load (R)L)；
The PWM signal generator (100) is used for generating a square wave signal to control the power Switch (SW) to be attracted, so that the voltage output end (OUT) outputs a constant root-mean-square voltage Vorms;
the PWM signal generator comprises an analog-to-digital converter (101) and a duty ratio generator (102), wherein a signal output end of the analog-to-digital converter (101) is connected with a signal input end of the duty ratio generator (102).
2. The output device according to claim 1, wherein: the analog-to-digital converter comprises a programmable voltage division unit, a first voltage division resistor (R1) and a second voltage division resistor (R2), a comparator (201) and an accumulator (202); the inverting input end of the comparator is coupled with a band-gap reference source, the non-inverting input end of the comparator is coupled with the connection end between a first voltage-dividing resistor (R1) and a second voltage-dividing resistor (R2), and the other end of the second voltage-dividing resistor (R2) is coupled with the programmable voltage-dividing unit; the output of the comparator (201) controls the accumulator, the accumulator (202) is used for accumulating the value of a constant n, and the output of the accumulator (202) controls the programmable voltage division unit and the duty cycle generator.
3. The output device according to claim 2, wherein: the programmable voltage division unit comprises a resistance series unit (203) and a switch array unit (204).
4. The output device according to claim 3, wherein: the resistor series unit comprises a plurality of resistors (R01) which are connected in series and have the same resistance, the switch array unit comprises a plurality of switches corresponding to the resistors (R01), the on and off of the switches are controlled by signals output by the accumulator (202), and the switches are used for controlling the corresponding resistors (R01) to be in a short-circuit or voltage division state.
5. The output device according to claim 4, wherein: when the voltage output device is in a state of outputting a constant root mean square voltage Vorms, the resistance of the resistance series unit is n × R01.
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Address after: No. 5, Xijin Road, Xinwu District, Wuxi City, Jiangsu Province, 214028 Patentee after: Wuxi Jingyuan Microelectronics Co.,Ltd. Address before: 214028 room 209, building a, block 106-c, Xinwu District, Wuxi City, Jiangsu Province Patentee before: Wuxi Jingyuan Microelectronics Co.,Ltd. |