CN213402961U

CN213402961U - IGBT drive circuit and power conversion equipment

Info

Publication number: CN213402961U
Application number: CN202022904704.5U
Authority: CN
Inventors: 杨博; 黄猛; 王京; 俞贤桥; 张珊; 方明照
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2021-06-08
Anticipated expiration: 2030-12-07

Abstract

The present disclosure relates to an IGBT drive circuit and power conversion apparatus, wherein the IGBT drive circuit includes: a driving chip (10) having a first driving signal port (Vo); the driving resistance adjusting circuit (20) is connected between the first driving signal port (Vo) and the grid electrode (G) of the IGBT, and the size of a driving resistance formed by the driving resistance adjusting circuit (30) is adjustable; a spike voltage detection circuit (30) connected to a gate (G) of the IGBT that is turned on with the first drive signal port (Vo), the spike voltage detection circuit (20) being configured to monitor whether a spike voltage occurs when the IGBT is turned off; and a resistance adjustment control circuit (40) connected between the peak voltage detection circuit (20) and the driving resistance adjustment circuit (30) and configured to reduce the resistance formed by the driving resistance adjustment circuit (30) when the peak voltage is monitored by the IGBT turning-off.

Description

IGBT drive circuit and power conversion equipment

Technical Field

The disclosure relates to the technical field of power equipment, in particular to an IGBT driving circuit and power conversion equipment.

Background

In a power conversion apparatus, an Insulated Gate Bipolar Transistor (IGBT) is one of the most core devices, and determines whether or not power conversion is performed normally. However, in the turn-off process of the IGBT, the gate is often influenced by other parasitic capacitances and stray inductances to accumulate charges to form a peak voltage, and there is a risk of misconduction, that is, if the peak voltage exceeds a voltage threshold value for turning on the IGBT, the IGBT is turned on during the turn-off process, and at this time, the IGBT is turned on simultaneously with other working IGBTs of the same bridge arm, so that a short circuit is caused and the IGBT is damaged.

Therefore, in order to ensure the normal operation of the IGBT, the gate peak voltage is suppressed, and the problem of false turn-on is eliminated.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present disclosure provide an IGBT drive circuit and a power conversion apparatus capable of preventing the IGBT drive circuit from turning on during turn-off.

According to a first aspect of the present disclosure, there is provided an IGBT driving circuit including:

the driving chip is provided with a first driving signal port;

the driving resistance adjusting circuit is connected between the first driving signal port and the grid electrode of the IGBT, and the size of a driving resistance formed by the driving resistance adjusting circuit is adjustable;

a spike voltage detection circuit connected to a gate of the IGBT that is in conduction with the first drive signal port, the spike voltage detection circuit configured to monitor whether a spike voltage occurs when the IGBT is turned off; and

and the resistance regulation control circuit is connected between the peak voltage detection circuit and the driving resistance regulation circuit and is configured to reduce the resistance formed by the driving resistance regulation circuit when the IGBT is switched off and the peak voltage is monitored.

In some embodiments, the driving resistance adjustment circuit includes: the driving circuit comprises a first driving resistor, a first MOS (metal oxide semiconductor) transistor, a second driving resistor and a third anti-reflection diode;

the first end of the first driving resistor is conducted with the first driving signal port, the second end of the first driving resistor is conducted with the grid electrode of the IGBT, and the first MOS tube, the second driving resistor and the third anti-reverse diode are connected in series and then connected in parallel with the first driving resistor.

In some embodiments, the driving chip has a forward bias output port, and the first gate of the first MOS transistor is connected to the forward bias output port and the resistance adjustment control circuit;

the resistance adjusting control circuit is configured to enable a first grid electrode of the first MOS tube to be grounded and turned off under the condition that the voltage is normal after the IGBT is turned off, and enable the driving resistor to be a first driving resistor; and when the peak voltage is monitored, the voltage at the connection part of the first grid electrode of the first MOS tube and the resistance regulation control circuit is lower than the voltage of the forward bias output port, so that the first MOS tube is switched on to enable the driving resistance to be the resistance formed by the first driving resistance and the second driving resistance in parallel.

In some embodiments, the driving chip has a forward bias output port, and the first gate of the first MOS transistor is connected to the forward bias output port through a first protection resistor.

In some embodiments, the spike voltage detection circuit comprises: the PNP type triode, the breakdown diode, the first anti-reverse diode, the second protection resistor and the third protection resistor;

the breakdown diode, the first anti-reverse diode and the second protection resistor are sequentially connected in series, the second protection resistor is connected with the resistor adjusting control circuit, the emitting electrode of the PNP type triode is connected with the breakdown diode, the collecting electrode of the PNP type triode is directly connected with the grid electrode of the IGBT, and the base electrode of the PNP type triode is connected with the grid electrode of the IGBT through the third protection resistor.

In some embodiments, the driving chip has a second driving signal port conducting with the emitter of the IGBT, and the connection between the spike voltage detection circuit and the resistance adjustment control circuit is connected to the second driving signal port through a fourth protection resistor.

In some embodiments, the driving chip has a second driving signal port conducting with the emitter of the IGBT, and the resistance adjustment control circuit includes:

the second anti-reverse diode and the follow current capacitor are connected in series, the anode of the second anti-reverse diode is connected to a circuit of the first driving signal port connected with the grid electrode of the IGBT, the connection point is located between the driving resistance adjusting circuit and the peak voltage detection circuit, and one end of the follow current capacitor is connected with the second driving signal port;

a second source electrode of the second MOS tube is connected with the driving resistance adjusting circuit, a second drain electrode of the second MOS tube is connected with a second driving signal port, and a second grid electrode of the second MOS tube is connected between the second anti-reverse diode and the follow current capacitor; and

and the NPN type triode has a collector connected with the second grid, an emitter connected with the second driving signal port, and a base connected with one end of the peak voltage detection circuit connected with the emitter of the IGBT.

In some embodiments, the driving resistance adjustment circuit includes: the driving circuit comprises a first driving resistor, a first MOS (metal oxide semiconductor) transistor, a second driving resistor and a third anti-reflection diode; the first end of the first driving resistor is conducted with the first driving signal port, the second end of the first driving resistor is conducted with the grid electrode of the IGBT, and the first MOS tube, the second driving resistor and the third anti-reverse diode are connected in series and then connected in parallel with the first driving resistor;

and the first grid electrode of the first MOS tube is connected with the second drain electrode of the second MOS tube.

In some embodiments, the resistance adjustment control circuit further comprises:

the fifth protective resistor is connected between the driving resistor adjusting circuit and the second grid;

the sixth protection resistor is connected between the second grid and the collector of the NPN type triode; and/or

And one end of the seventh protection resistor is connected between the second anti-reverse diode and the freewheeling capacitor, and the other end of the seventh protection resistor is connected between the second grid and the collector of the NPN type triode.

According to a second aspect of the present disclosure, there is provided a power conversion apparatus including the IGBT drive circuit of the above-described embodiment.

The IGBT driving circuit of the embodiment of the disclosure monitors whether the peak voltage exists or not through the peak voltage detection circuit 30 when the IGBT is turned off, so as to select the resistance value of the driving resistor reduced relative to the normal working state, when the peak voltage exists, the driving resistor when the IGBT is turned off is reduced to provide an extra rapid discharging channel for the accumulated charges of the grid electrode of the IGBT, thereby inhibiting the peak voltage of the grid electrode, ensuring that the IGBT is not conducted by mistake, and realizing the function of protecting the IGBT when the IGBT is turned off.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the disclosure and not to limit the disclosure. In the drawings:

fig. 1 is a schematic block composition diagram of some embodiments of an IGBT driver circuit of the present disclosure;

fig. 2 is a circuit schematic of some embodiments of the IGBT drive circuits of the present disclosure.

Detailed Description

The present disclosure is described in detail below. In the following paragraphs, different aspects of the embodiments are defined in more detail. Aspects so defined may be combined with any other aspect or aspects unless clearly indicated to the contrary. In particular, any feature considered to be preferred or advantageous may be combined with one or more other features considered to be preferred or advantageous.

As shown in fig. 1 and 2, the present disclosure provides an IGBT driving circuit including: the driving circuit comprises a driving chip 10, a driving resistance adjusting circuit 20, a peak voltage detection circuit 30 and a resistance adjusting control circuit 40.

The driving chip 10 has a first driving signal port Vo and a second driving signal port V_EAnd a forward bias output port Vcc, a first drive signal port Vo is conducted with the gate G of the IGBT, and a second drive signal port V_EAnd is conducted with the emitter E of the IGBT. A first driving signal port Vo and a second driving signal portV_EFor outputting a drive signal and a forward bias output port Vcc for outputting a forward voltage.

And the driving resistance adjusting circuit 20 is connected between the first driving signal port Vo and the gate G of the IGBT, and the driving resistance formed by the driving resistance adjusting circuit 20 is adjustable in size.

And a spike voltage detection circuit 30 connected to the gate G of the IGBT turned on with the first driving signal port Vo, the spike voltage detection circuit 30 being configured to monitor whether a spike voltage occurs when the IGBT is turned off.

And the resistance adjustment control circuit 40 is connected between the peak voltage detection circuit 30 and the driving resistance adjustment circuit 20, and is configured to reduce the resistance formed by the driving resistance adjustment circuit 20 when the peak voltage is detected by the IGBT turn-off.

The misleading is that two IGBTs connected to the same bridge arm of the positive and negative poles of the bus are simultaneously conducted, which is equivalent to the short circuit of the positive and negative poles of the bus, so that a large amount of current passes through the IGBTs to cause short circuit damage, the power conversion equipment stops working, the misleading is prevented, the IGBT is prevented from being damaged by the short circuit, and the normal operation of the equipment is ensured.

In some embodiments, as shown in fig. 2, the driving resistance adjusting circuit 20 includes: the driving circuit comprises a first driving resistor R1, a first MOS transistor Q1, a second driving resistor R2 and a third anti-reflection diode D3. The first driving resistor R1 and the second driving resistor R2 are used for driving the IGBT switch and controlling the current.

The first end of the first driving resistor R1 is connected to the first driving signal port Vo, the second end of the first driving resistor R1 is connected to the gate G of the IGBT, and the first MOS transistor Q1, the second driving resistor R2, and the third anti-diode D3 are connected in series and then connected in parallel to the first driving resistor R1. The anode of the third anti-reflection diode D3 is connected to the first driving resistor R1, and the cathode is connected to the second driving resistor R2. The MOS transistor is an insulated gate field effect transistor, and is called a metal oxide semiconductor in english.

In this embodiment, when the IGBT is turned off, if the voltage of the gate G of the IGBT is normal, the resistance adjustment control circuit 40 turns off the first gate G1 of the first MOS transistor Q1, so that the driving resistor is the first driving resistor R1; if the peak voltage is monitored by the peak voltage detection circuit 30, the first MOS transistor Q1 is turned on by the resistance adjustment control circuit 40, so that the driving resistance is formed by connecting the first driving resistance R1 and the second driving resistance R2 in parallel, and the resistance after the parallel connection is smaller than that of the R1, thereby providing an extra rapid discharge channel for the accumulated charges of the gate G of the IGBT, suppressing the gate peak voltage, ensuring that the IGBT is not turned on by mistake, and realizing the function of protecting the IGBT when turned off.

In some embodiments, as shown in fig. 2, the driver chip 10 has a forward biased output terminal Vcc, and the first gate g1 of the first MOS transistor Q1 is connected to the forward biased output terminal Vcc and the resistance adjustment control circuit 40.

The resistance adjustment control circuit 40 is configured to, in a case where the voltage is normal after the IGBT is turned off, ground the first gate g1 of the first MOS transistor Q1 to turn off, so that the driving resistance is the first driving resistance R1; when the peak voltage is detected, the voltage at the connection position of the first gate g1 of the first MOS transistor Q1 and the resistance adjustment control circuit 40 is lower than the voltage of the forward bias output port Vcc, so as to turn on the first MOS transistor Q1, and the driving resistor is a resistor formed by connecting the first driving resistor R1 and the second driving resistor R2 in parallel.

This embodiment can control the voltage applied to the first gate G1 of the first MOS transistor Q1 by the resistance adjustment control circuit 40 to control the on/off of the first MOS transistor Q1, so that when there is a spike voltage after the IGBT is turned off, the driving resistance is a resistance formed by connecting the first driving resistance R1 and the second driving resistance R2 in parallel by turning on the first MOS transistor Q1, and the driving resistance is reduced compared with the normal gate G voltage of the IGBT. Therefore, an extra rapid discharging channel can be provided for accumulated charges of the grid G of the IGBT, so that grid peak voltage is restrained, the IGBT is guaranteed not to be conducted mistakenly, and the function of protecting the IGBT when the IGBT is turned off is achieved.

In some embodiments, the driver chip 10 has a forward bias output port Vcc, and the first gate g1 of the first MOS transistor Q1 is connected to the forward bias output port Vcc through a first protection resistor R3. This embodiment can play a role of current limiting when the first gate g1 of the first MOS transistor Q1 is grounded, and prevent the forward bias output port Vcc from applying too large voltage to the first MOS transistor Q1, so as to avoid damaging the driver chip 10 or the first MOS transistor Q1.

In some embodiments, as shown in fig. 2, the spike voltage detection circuit 30 includes: the circuit comprises a PNP type triode Q4, a breakdown diode Z1, a first anti-reflection diode D1, a second protection resistor R7 and a third protection resistor R9. If the voltage of the grid G of the IGBT exceeds the IGBT turn-on threshold value, the breakdown diode Z1 is conducted; the first anti-reverse diode D1 is configured to allow only the accumulated charges of the gate G of the IGBT to be discharged outward, preventing the charges from flowing reversely toward the gate G of the IGBT. The anode of the first anti-reverse diode D1 is connected with the breakdown diode Z1, and the cathode is connected with the second protection resistor R7. The second protection resistor R7 can prevent the gate G and the emitter E of the IGBT from being short-circuited; the third protection resistor R9 is used to prevent the gate G of the IGBT from being over-voltage and damaging the PNP transistor Q4.

The breakdown diode Z1, the first anti-reverse diode D1 and the second protection resistor R7 are sequentially connected in series, and the second protection resistor R7 is connected with the resistance regulation control circuit 40 and the emitter E of the IGBT. An emitting electrode of the PNP type triode Q4 is connected with a breakdown diode Z1, a collecting electrode of the PNP type triode Q4 is directly connected with a grid G of the IGBT, and a base electrode of the PNP type triode Q4 is connected with the grid G of the IGBT through a third protection resistor R9.

This embodiment can reliably detect when there is a spike voltage after the IGBT is turned off by providing the breakdown diode Z1 in the spike voltage detection circuit 30, so as to reduce the drive resistance in time to discharge excess charges.

In some embodiments, as shown in fig. 2, the driving chip 10 has a second driving signal port V conducting with the emitter E of the IGBT_EThe junction of the peak voltage detection circuit 30 and the resistance adjustment control circuit 40 passes through the fourth protection resistor R8 and the second driving signal port V_EAnd (4) connecting. By providing the fourth protection resistor R8, the spike voltage detection circuit 30 and the resistance adjustment control circuit 40 can be protected, and particularly, the NPN transistor Q3 in the adjustment control circuit 40 is prevented from being damaged by an excessive voltage. Also, the fourth protection resistor R8 may prevent the gate G and the emitter E of the IGBT from being short-circuited.

In some embodiments, as shown in fig. 2, the driving chip 10 has a second driving signal port V conducting with the emitter E of the IGBT_EThe resistance adjustment control circuit 40 includes: the second anti-reverse diode D2 and the free-wheeling capacitor C1, the second MOS pipe Q2 and the NPN type triode Q3 are connected in series.

Wherein, the anode of the second anti-reverse diode D2 is connected to the circuit where the first driving signal port Vo is connected to the gate G of the IGBT, the connection point is located between the driving resistance adjusting circuit 20 and the peak voltage detecting circuit 30, and the end of the freewheeling capacitor C1 far away from the second anti-reverse diode D2 and the second driving signal port V_EAnd (4) connecting.

The second source s2 of the second MOS transistor Q2 is connected to the driving resistance adjusting circuit 20, and specifically, the second source s2 is connected to the first gate g1 of the first MOS transistor Q1; the second drain d2 of the second MOS transistor Q2 and the second driving signal port V_EIn addition, the second gate g2 of the second MOS transistor Q2 is connected between the second anti-reverse diode D2 and the freewheeling capacitor C1.

An NPN transistor Q3, having a collector connected to the second gate g2, an emitter connected to the second drive signal port V_EThe base is connected to the peak voltage detection circuit 30 and the end of the IGBT connected to the emitter E.

According to the embodiment, when the peak voltage detection circuit 30 detects a peak voltage, the voltage at the joint of the first gate g1 of the first MOS transistor Q1 and the resistance adjustment control circuit 40 is adjusted through the cooperation of all the parts to control the on-off of the first MOS transistor Q1, so that a peak appears after the IGBT is turned off and different driving resistors are adopted under a normal voltage, and the IGBT driving circuit can reliably work.

In some embodiments, the driving resistance adjustment circuit 20 includes: the driving circuit comprises a first driving resistor R1, a first MOS transistor Q1, a second driving resistor R2 and a third anti-reflection diode D3; the first end of the first driving resistor R1 is connected to the first driving signal port Vo, the second end of the first driving resistor R1 is connected to the gate G of the IGBT, and the first MOS transistor Q1, the second driving resistor R2, and the third anti-diode D3 are connected in series and then connected in parallel to the first driving resistor R1. The first gate g1 of the first MOS transistor Q1 is connected to the second drain d2 of the second MOS transistor Q2.

In some embodiments, as shown in fig. 2, the resistance adjustment control circuit 40 further includes:

a fifth protection resistor R4 connected between the driving resistance adjusting circuit 20 and the second gate g 2;

a sixth protection resistor R6 connected between the second gate g2 and the collector of the NPN transistor Q3; and/or

One end of the seventh protection resistor R5 is connected between the second anti-reverse diode D2 and the freewheeling capacitor C1, and the other end is connected between the second gate g2 and the collector of the NPN transistor Q3.

In this embodiment, the fifth protection resistor R4 and the first protection resistor R3 both play a role of current limiting protection when the second MOS transistor Q2 is turned on and the gate g1 of the first MOS transistor Q1 is grounded, so as to prevent the first MOS transistor Q1, the second MOS transistor Q2 or the driver chip 10 from being damaged by an excessive current. The seventh protection resistor R5 and the sixth protection resistor R6 can be connected to one end of the freewheeling capacitor C1 at the second gate g1 of the second MOS transistor Q2 or pass through the second gate g1, and play a role of current limiting protection after the gate g2 of the Q2 is connected to one end of the capacitor C1 or grounded through the NPN type transistor Q3.

The specific structure of the IGBT driving circuit of the present disclosure is described below with reference to fig. 2.

The driver chip 10 has a first driving signal port Vo and a second driving signal port V_EAnd a forward biased output port Vcc, the IGBT having a gate G and an emitter E. The first driving signal port Vo is conducted with the gate G of the IGBT, and the second driving signal port V is conducted with the gate G of the IGBT_EAnd is conducted with the emitter E of the IGBT.

The used devices comprise a first driving resistor R1, a second driving resistor R2, a breakdown diode Z1, a first anti-reflection diode D1, a second anti-reflection diode D2, a third anti-reflection diode D3, a freewheeling capacitor C1, protection resistors R3, R4, R5, R6, R7, R8 and R9, an N-type first MOS transistor Q1, an N-type second MOS transistor Q2, an NPN-type triode Q3 and a PNP-type triode Q4.

As shown in fig. 2, a first driving resistor R1 is disposed between the first driving signal port Vo and the gate G of the IGBT, and the second driving resistor R2, the N-type first MOS transistor Q1, and the third anti-diode D3 are connected in series and then connected in parallel with two ends of the first driving resistor R1.

The first drain d1 of the first MOS transistor Q1 and one end of the first driving resistor R1 are connected to the first driving signal port Vo, and the first source s1 of the first MOS transistor Q1 is connected to the second driving resistor R2. The first gate g1 of the first MOS transistor Q1 is connected to the forward bias output port Vcc, the first gate g1 of the first MOS transistor Q1 is connected to the second source s2 of the N-type second MOS transistor Q2 through a fifth protection resistor R4, and the second drain d2 of the second MOS transistor Q2 is connected to the second driving signal port V_EA second gate g2 of the second MOS transistor Q2 is connected between the freewheeling capacitor C1 and the second backward diode D2 through a seventh protection resistor R5, and an anode of the second backward diode D2 is connected to the first driving signal port Vo and the second driving signal port V_EAnd between the third backward diode D3 and the connection point of the collector of the PNP transistor Q4 and the gate G of the IGBT. One end of the current capacitor C1 far away from the second backward diode D2 and the second driving signal port V_EAnd (4) connecting.

The collector of the NPN transistor Q3 passes through the sixth protection resistor R6 and the second gate g2 of the second MOS transistor Q2, and one end of the seventh protection resistor R5 is connected between the second gate g2 and the sixth protection resistor R6. An emitter of the NPN transistor Q3 is connected to the second drive signal port V_EAnd an emitter E of the IGBT, and is located between the flywheel capacitor C1 and a connection point of the fourth protection resistor R8 and the communication line. The base electrode of the NPN type triode Q3 is connected with the emitting electrode of the PNP type triode Q4 after being sequentially connected in series through a second protection resistor R7, a first anti-reverse diode D1 and a breakdown diode Z1, the collecting electrode of the PNP type triode Q4 is directly connected and conducted with the grid electrode G of the IGBT, and the base electrode of the PNP type triode Q4 is connected with the grid electrode G of the IGBT through a third protection resistor R9The pole G is connected, and the voltage of the gate G can be monitored in real time when the IGBT is turned off.

The operating principle of the IGBT driving circuit is as follows:

1. gate G voltage of IGBT is normal

When the first driving signal port Vo outputs the turn-on signal Von, the PNP transistor Q4 does not operate, so the NPN transistor Q3 is not turned on, the second anti-reverse diode D2 is turned on, the freewheeling capacitor C1 is charged, and meanwhile, a voltage is applied to the second MOS transistor Q2 through the seventh protection resistor R5 to turn on the second MOS transistor Q2, the front end potential of the fifth protection resistor R4 is pulled low, the voltage of the first gate g1 of the first MOS transistor Q1 is grounded and turned off, and at this time, the driving resistor resistance is the resistance of R1.

When Vo outputs a turn-off signal-Voff, the PNP type triode Q4 is conducted to start working, the breakdown diode Z1 is not broken because the voltage of the grid G of the IGBT is normal, the NPN type triode Q3 is not conducted, the second backward diode D2 does not work at the moment, the voltage is applied to the second MOS transistor Q2 by the freewheeling capacitor C1 to be conducted, the voltage of the first grid G1 of the first MOS transistor Q1 is grounded to be turned off, and the resistance value of the driving resistor is the resistance value of the R1 at the moment.

2. When the IGBT is turned off, voltage peak appears on the grid

When the first driving signal port Vo outputs a negative voltage turn-off signal-Voff and a peak voltage appears at the gate, if the peak voltage exceeds an IGBT turn-on threshold, the breakdown diode Z1 is broken down, the first anti-blocking diode D1 and the NPN transistor Q3 start to operate, and a front end potential of the sixth protection resistor R6 is pulled down, so that a second gate G2 of the second MOS transistor Q2 is grounded and turned off, therefore, the forward bias output port Vcc continuously applies a forward bias to the first MOS transistor Q1, so that the first MOS transistor Q1 is turned on, the second driving resistor R2 is connected to the line and connected in parallel with R1, at this time, the driving resistor has a resistance value of R1 · R2/(R1+ R2), the driving resistor has a resistance value that becomes small, at this time, the charge of the gate G of the IGBT is rapidly discharged through the low impedance driving circuit, and the voltage peak is suppressed.

Secondly, this disclosure also provides a power conversion device, including the IGBT drive circuit of the above-mentioned embodiment. The power conversion equipment converts direct current into alternating current to be an inversion process, converts alternating current into direct current to be a rectification process, and the two processes are realized by the alternate switching of a plurality of IGBTs, namely the IGBTs are always switched on and off no matter which working state is adopted.

Therefore, through adopting the IGBT drive circuit of this disclosure, when the IGBT shuts down, when sharp peak voltage appears, drive resistance when reducing to turn off provides extra rapid discharge channel for the accumulated electric charge of IGBT grid to restrain grid peak voltage, guarantee that the IGBT is not switched on by mistake, realize the function of protection IGBT when the shutoff, prevent that the IGBT from being damaged by the short circuit, thereby guarantee power conversion equipment's normal operating.

It should also be noted that the functional blocks, components, systems, devices, or circuits described herein may be implemented using hardware, software, or a combination of hardware and software. For example, the disclosed embodiments may be implemented using one or more integrated circuits programmed to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The one or more integrated circuits may comprise, for example, one or more processors or Configurable Logic Devices (CLDs), or a combination thereof. The one or more processors may be, for example, one or more Central Processing Units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, ASICs (application specific integrated circuits), or other integrated processing devices. One or more CLDs may be, for example, one or more CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), PLAs (programmable logic arrays), reconfigurable logic circuits, or other integrated logic devices. Additionally, an integrated circuit comprising one or more processors may be programmed to execute software, firmware, code, or other program instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. An integrated circuit comprising one or more CLDs may also be programmed with logic code, logic definitions, hardware description languages, configuration files, or other logic instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, acts, or other operational features described herein for the disclosed embodiments. Further, the one or more non-transitory tangible computer-readable media may include, for example, one or more data storage devices, memory devices, flash memory, random access memory, read only memory, programmable memory devices, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable media. Other variations may also be implemented while still utilizing the techniques described herein.

Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other priority of such elements.

The IGBT driving circuit and the power conversion device provided by the present disclosure are described in detail above. The principles and embodiments of the present disclosure are explained herein using specific examples, which are set forth only to help understand the method and its core ideas of the present disclosure. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present disclosure without departing from the principle of the present disclosure, and such improvements and modifications also fall within the scope of the claims of the present disclosure.

Claims

1. An IGBT driving circuit characterized by comprising:

a driving chip (10) having a first driving signal port (Vo);

the driving resistance adjusting circuit (20) is connected between the first driving signal port (Vo) and the grid electrode (G) of the IGBT, and the driving resistance formed by the driving resistance adjusting circuit (20) is adjustable in size;

a spike voltage detection circuit (30) connected to a gate (G) of the IGBT conducting with the first drive signal port (Vo), the spike voltage detection circuit (30) configured to monitor whether a spike voltage occurs when the IGBT is turned off; and

and the resistance regulation control circuit (40) is connected between the peak voltage detection circuit (30) and the driving resistance regulation circuit (20) and is configured to reduce the resistance formed by the driving resistance regulation circuit (20) when the IGBT turns off and monitors the peak voltage.

2. The IGBT drive circuit according to claim 1, wherein the drive resistance adjustment circuit (20) includes: the driving circuit comprises a first driving resistor (R1), a first MOS (Q1), a second driving resistor (R2) and a third anti-reflection diode (D3);

the first end of the first driving resistor (R1) is conducted with the first driving signal port (Vo), the second end of the first driving resistor (R1) is conducted with the gate (G) of the IGBT, and the first MOS transistor (Q1), the second driving resistor (R2) and the third anti-diode (D3) are connected in series and then are connected in parallel with the first driving resistor (R1).

3. The IGBT driver circuit according to claim 2, wherein the driver chip (10) has a forward bias output port (Vcc), and the first gate (g1) of the first MOS transistor (Q1) is connected with the forward bias output port (Vcc) and the resistance adjustment control circuit (40);

wherein, the resistance adjustment control circuit (40) is configured to make the first gate (g1) of the first MOS tube (Q1) grounded and turn off when the voltage is normal after the IGBT is turned off, so that the driving resistance is the first driving resistance (R1); and when the peak voltage is monitored, the voltage at the connection position of the first grid (g1) of the first MOS transistor (Q1) and the resistance regulation control circuit (40) is lower than the voltage of the forward bias output port (Vcc), so that the first MOS transistor (Q1) is switched on to enable the driving resistance to be the resistance formed by the first driving resistance (R1) and the second driving resistance (R2) in parallel.

4. The IGBT driver circuit according to claim 2, wherein the driver chip (10) has a forward bias output port (Vcc), and the first gate (g1) of the first MOS transistor (Q1) is connected with the forward bias output port (Vcc) through a first protection resistor (R3).

5. The IGBT driver circuit according to claim 1, wherein the spike voltage detection circuit (30) comprises: the circuit comprises a PNP type triode (Q4), a breakdown diode (Z1), a first anti-reflection diode (D1), a second protection resistor (R7) and a third protection resistor (R9);

wherein, the breakdown diode (Z1), the first anti-reverse diode (D1) and the second protection resistor (R7) are sequentially connected in series, the second protection resistor (R7) is connected with the resistance adjustment control circuit (40), the emitter of the PNP type triode (Q4) is connected with the breakdown diode (Z1), the collector of the PNP type triode (Q4) is directly connected with the grid (G) of the IGBT, and the base of the PNP type triode (Q4) is connected with the grid (G) of the IGBT through the third protection resistor (R9).

6. The IGBT drive circuit according to claim 1, characterized in that the drive chip (10) has a second drive signal port (V) conducting with the emitter (E) of the IGBT_E) The connection part of the spike voltage detection circuit (30) and the resistance regulation control circuit (40) is connected with the second driving signal port (V) through a fourth protection resistor (R8)_E) And (4) connecting.

7. The IGBT drive circuit according to claim 1, characterized in that the drive chip (10) has a second drive signal port (V) conducting with the emitter (E) of the IGBT_E) The resistance adjustment control circuit (40) includes:

a second anti-reverse diode (D2) and a free-wheeling capacitor (C1) which are connected in series, wherein the anode of the second anti-reverse diode (D2) is connected with a circuit that the first driving signal port (Vo) is connected with the grid electrode (G) of the IGBT, the connection point is positioned between the driving resistance adjusting circuit (20) and the spike voltage detection circuit (30), and one end of the free-wheeling capacitor (C1) is connected with the second driving signal port (V1)_E) Connecting;

second MOS transistor (Q)2) A second source (s2) connected to the driving resistance adjustment circuit (20), and a second drain (d2) connected to the second driving signal port (V)_E) A second gate (g2) connected between the second anti-reverse diode (D2) and the free-wheeling capacitor (C1); and

an NPN transistor (Q3) having a collector connected to the second gate (g2) and an emitter connected to a second drive signal port (V)_E) And the base electrode is connected with one end of the peak voltage detection circuit (30) connected with the emitter (E) of the IGBT.

8. The IGBT drive circuit according to claim 7, wherein the drive resistance adjustment circuit (20) includes: the driving circuit comprises a first driving resistor (R1), a first MOS (Q1), a second driving resistor (R2) and a third anti-reflection diode (D3); a first end of the first driving resistor (R1) is conducted with the first driving signal port (Vo), a second end of the first driving resistor (R1) is conducted with a gate (G) of the IGBT, and the first MOS transistor (Q1), the second driving resistor (R2) and the third anti-reverse diode (D3) are connected in series and then are connected in parallel with the first driving resistor (R1);

wherein, the first gate (g1) of the first MOS transistor (Q1) is connected with the second drain (d2) of the second MOS transistor (Q2).

9. The IGBT drive circuit according to claim 7, wherein the resistance adjustment control circuit (40) further includes:

a fifth protection resistor (R4) connected between the drive resistance adjustment circuit (20) and the second gate (g 2);

a sixth protection resistor (R6) connected between the second gate (g2) and the collector of the NPN transistor (Q3); and/or

And a seventh protection resistor (R5), one end of which is connected between the second anti-reverse diode (D2) and the free-wheeling capacitor (C1), and the other end of which is connected between the second grid (g2) and the collector of the NPN type triode (Q3).

10. A power conversion apparatus comprising the IGBT drive circuit according to any one of claims 1 to 9.