CN213277410U - Equalizer drive circuit and display device - Google Patents
Equalizer drive circuit and display device Download PDFInfo
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- CN213277410U CN213277410U CN202022259487.9U CN202022259487U CN213277410U CN 213277410 U CN213277410 U CN 213277410U CN 202022259487 U CN202022259487 U CN 202022259487U CN 213277410 U CN213277410 U CN 213277410U
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Abstract
The utility model discloses an equalizer drive circuit and display device, this equalizer drive circuit includes: the first input end of the inverting adder is connected with the reference voltage signal input end, the second input end of the inverting adder is connected with the bias voltage signal input end, and the output end of the inverting adder outputs a driving signal; and the input end of the switch module receives power supply voltage, the output end of the switch module is connected with the power supply end of the reverse phase adder, and the control end of the switch module receives a control signal. The utility model discloses can avoid exporting the drive signal of balanced device unusual, and then avoided appearing twinkling when the switching on and shutting down, improved product quality.
Description
Technical Field
The utility model relates to a show technical field, concretely relates to balanced device drive circuit and display device.
Background
With the rapid development of electronic products toward light weight, thinness and miniaturization, liquid crystal displays are used as display terminals in most of various portable electronic products, and are important components in video cameras, notebook computers, desktop computers, smart televisions, mobile terminals or personal digital processors.
The liquid crystal display device generally includes a liquid crystal display panel including a plurality of rows of gate lines and a plurality of columns of data lines, and a driving integrated circuit for driving the liquid crystal display panel to perform a picture display, the driving integrated circuit including a timing controller, a plurality of gate drivers, and a plurality of source drivers. The time sequence controller is used for controlling the grid driver and the source driver; the gate driver is used for providing scanning voltage to a plurality of rows of gate lines of the liquid crystal display panel; the source driver is used for supplying data voltages to a plurality of rows of data lines of the liquid crystal display panel. Meanwhile, a Backlight (BL for short) and an Equalizer (EQ for short) are also disposed on the liquid crystal display panel, the Backlight is used to provide Backlight brightness to the liquid crystal display panel, and the Equalizer is used to adjust the gain value of each frequency band signal input to the liquid crystal display panel, so as to reduce the power consumption of the system.
Fig. 1 shows a schematic circuit structure of an existing equalizer drive circuit, and fig. 2a and 2b show waveforms of signals in the existing equalizer drive circuit when power is on and off, respectively. With reference to fig. 1, 2a and 2b, an equalizer driver circuit targeted to drive the operation of an equalizer includes an operational amplifier U1, the operational amplifier U1 includes a plurality of pins 1-5, and the operational amplifier U1 is configured as an inverting adder to provide a driving signal FB03 based on an input reference voltage signal FB01 and an offset voltage signal FB 02. The power supply pins 2 and 4 of the operational amplifier U1 respectively receive a second power supply voltage VS-and a first power supply voltage VS + (the first power supply voltage VS + is provided by a power supply voltage AVDD output by the power chip based on the input voltage VIN), and operate according to the first power supply voltage VS + and the second power supply voltage VS-to generate the driving signal FB 03.
However, referring to fig. 2a and fig. 2b, after practical tests, in the current equalizer driving circuit, due to the difference between the power-on speed and the power-off speed of the input reference voltage signal FB01 and the bias voltage signal FB02, the output driving signal FB03 has an abnormal condition (e.g., a spike, a bump, etc.) and further affects the deflection driving of the equalizer on the liquid crystal in the liquid crystal display panel, so that the display device has a screen flashing phenomenon during the power-on and power-off operations. Meanwhile, experiments also find that more screen flashing can be caused when the backlight source and the equalizer are not started or closed synchronously.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides an equalizer drive circuit, display panel and display device can avoid exporting the drive signal of equalizer to appear unusually, and then has avoided appearing the scintillation when the switching on and shutting down, has improved product quality.
In one aspect, according to the present invention, an equalizer driving circuit includes: the first input end of the inverting adder is connected with the reference voltage signal input end, the second input end of the inverting adder is connected with the bias voltage signal input end, and the output end of the inverting adder outputs a driving signal; the input end of the switch module receives power supply voltage, the output end of the switch module is connected with the power supply end of the reverse phase adder, and the control end of the switch module receives a control signal.
Optionally, the switch module comprises: a first switch, a first end of which receives a first supply voltage, a second end of which is connected to a first supply end of the inverting adder, and a control end of which receives the control signal; and a first end of the second switch receives a second power supply voltage, a second end of the second switch is connected with a second power supply end of the inverting adder, and a control end of the second switch receives the control signal.
Optionally, the first switch and the second switch are both NMOS transistors or both NPN triodes.
Optionally, the equalizer driving circuit further comprises: the power supply module comprises a first output end for providing a second power supply voltage and a second output end for providing a third power supply voltage; a first end of the reference voltage generating unit is connected with the second output end of the power supply module, and a second end of the reference voltage generating unit is connected with the reference voltage signal input end; and a first end of the bias voltage generating unit is connected with a first output end of the power supply module, and a second end of the bias voltage generating unit is connected with the bias voltage signal input end.
Optionally, the equalizer driving circuit further comprises: the first operational amplifier is connected between the second end of the reference voltage generating unit and the reference voltage signal input end; and the second operational amplifier is connected between the second end of the bias voltage generating unit and the bias voltage signal input end.
Optionally, the equalizer driving circuit further comprises: and the input end of the voltage division unit receives the third power supply voltage, and the output end of the voltage division unit outputs the first power supply voltage.
Optionally, the inverting adder comprises: a third operational amplifier; the first resistor is connected between the inverting input end of the third operational amplifier and the reference voltage signal input end; a second resistor connected between the inverting input terminal of the third operational amplifier and the bias voltage signal input terminal; the third resistor is connected between the non-inverting input end and the grounding end of the third operational amplifier; a fourth resistor connected between the inverting input terminal of the third operational amplifier and the output terminal of the third operational amplifier; the fifth resistor is connected between the first power supply end and the grounding end of the inverting adder; and a sixth resistor connected between the second power supply terminal and the ground terminal of the inverting adder.
On the other hand, according to the present invention, a display device includes a display panel, a backlight source, an equalizer and the equalizer driving circuit as described above, wherein the backlight source is connected to the display panel, and the backlight source provides backlight brightness to the display panel; the equalizer is connected with the display panel; the equalizer driving circuit is connected to the equalizer for receiving a control signal and outputting a driving signal to the equalizer.
Optionally, the control signal received by the equalizer driving circuit is an enable signal of the backlight source.
The utility model has the advantages that: the utility model discloses an equalizer drive circuit and display device sets up switch module in the power supply department of the required drive signal's of production equalizer opposition adder, and the switching on/off and then control through control signal control switch module provide to the last electric time sequence of the supply voltage of opposition adder, the unusual condition appears in the drive signal's of having avoided the opposition adder output wave form, so, has avoided appearing the scintillation when the switch on/off machine, has improved product quality.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram showing an equalizer drive circuit;
fig. 2a and 2b are schematic diagrams showing waveforms of signals when power is on and off in a conventional equalizer driving circuit, respectively;
FIGS. 3a and 3b are diagrams illustrating simulation results of waveforms of respective signals in the case of powering on and powering off an operational amplifier in accordance with a model in an equalizer driving circuit, respectively;
fig. 4a and 4b are diagrams showing simulation results of waveforms of respective signals in the case where the operational amplifier is continuously supplied with power in the equalizer drive circuit, respectively;
fig. 5 illustrates a system block diagram of an equalizer drive circuit provided in accordance with an embodiment of the present disclosure;
fig. 6 shows a circuit configuration schematic diagram of an equalizer drive circuit provided according to an embodiment of the present disclosure;
fig. 7a and 7b are schematic diagrams illustrating simulation structures of waveforms of signals of an equalizer driving circuit according to an embodiment of the disclosure when the equalizer driving circuit is turned on and turned off, respectively.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 3a and 3b respectively show simulation results of waveforms of signals in the case where the operational amplifier is powered on and off by model in the equalizer drive circuit, and fig. 4a and 4b respectively show simulation results of waveforms of signals in the case where the operational amplifier is continuously powered on in the equalizer drive circuit.
Based on the above technical problem, through simulation, when the timing of the input reference voltage signal FB01 and the offset voltage signal FB02 is not changed, and the power supply timing of the operational amplifier in the equalizer driving circuit is changed by the control signal EN to power up the operational amplifier according to the power-up timing of the model, i.e., the display device, with reference to fig. 2a and 3a, the timing waveform of the driving signal FB03 finally output by the equalizer driving circuit is also changed accordingly. On the other hand, under the condition that the timing of the control input reference voltage signal FB01 and the bias voltage signal FB02 is not changed, in combination with fig. 2b and fig. 3b, if the power supply timing to the operational amplifier in the equalizer driving circuit is changed by the control signal EN so as to power down the operational amplifier according to the model, that is, the power down timing of the display device, the timing waveform of the driving signal FB03 finally output by the equalizer driving circuit is also changed correspondingly.
Based on a similar principle, through simulation, under the condition that the timing of the control input reference voltage signal FB01 and the offset voltage signal FB02 is not changed, in combination with fig. 2a and fig. 4a, if the power supply timing of the operational amplifier in the equalizer driving circuit is changed by the control signal EN so that the operational amplifier is in a state of continuously supplying power, the timing waveform of the driving signal FB03 finally output by the equalizer driving circuit is also changed correspondingly. Under the condition that the timing of the control input reference voltage signal FB01 and the bias voltage signal FB02 is not changed, with reference to fig. 2b and fig. 4b, if the power supply timing to the operational amplifier in the equalizer driving circuit is changed by the control signal EN so that the equalizer driving circuit is in a state of continuous power-down, the timing waveform of the driving signal FB03 finally output by the equalizer driving circuit is also changed accordingly.
Therefore, it can be concluded that different power supply timings of the operational amplifiers in the equalizer driving circuit have an effect on the driving signal FB03 output by the equalizer driving circuit to the equalizer. The utility model discloses an improved equalizer drive circuit structure based on above-mentioned principle to this improves the switching on and shutting down scintillation problem. Further description is provided below with reference to specific examples.
Fig. 5 shows a system block diagram of an equalizer driving circuit provided according to an embodiment of the present disclosure, fig. 6 shows a circuit structure schematic diagram of the equalizer driving circuit provided according to the embodiment of the present disclosure, and fig. 7a and 7b respectively show simulation structure schematic diagrams of waveforms of signals of the equalizer driving circuit provided according to the embodiment of the present disclosure when the equalizer driving circuit is turned on and turned off.
As shown in fig. 5, in the present embodiment, the equalizer drive circuit includes: inverting adder 400 and switching module 500.
Wherein a first input of the inverting adder 400 is coupled to the reference voltage signal input to receive the reference voltage signal FB01, a second input of the inverting adder 400 is coupled to the offset voltage signal input to receive the offset voltage signal FB02, and an output of the inverting adder 400 outputs the driving signal FB 03. The inverting adder 400 is used for performing reverse bias amplification on the received reference voltage signal FB01 and the bias voltage signal FB02 to output a driving signal FB03 to the equalizer 600, and the equalizer 600 drives liquid crystal in the display panel to deflect according to the driving signal FB 03. Further, by adjusting the magnitude of the bias voltage signal FB02, the deflection angle of the liquid crystal in the display panel driven by the equalizer 600 can be adjusted.
Further, referring to fig. 6, inverting adder 400 includes: a third operational amplifier U2, a first resistor R1 through a sixth resistor R6. The first resistor R1 is connected between the inverting input terminal of the third operational amplifier U2 and the reference voltage signal input terminal, the second resistor R2 is connected between the inverting input terminal of the third operational amplifier U2 and the bias voltage signal input terminal, the third resistor R3 is connected between the non-inverting input terminal of the third operational amplifier U2 and the ground terminal, the fourth resistor R4 is connected between the inverting input terminal of the third operational amplifier U2 and the output terminal of the third operational amplifier U2, the fifth resistor R5 is connected between the first power supply terminal (i.e., the first power supply terminal of the third operational amplifier U2) and the ground terminal of the inverting adder 400, and the sixth resistor R6 is connected between the second power supply terminal (i.e., the second power supply terminal of the third operational amplifier U2) and the ground terminal of the inverting adder 400.
The input terminal of the switch module 500 receives a supply voltage (including a first supply voltage VS + and a second supply voltage VS-), the output terminal of the switch module 500 is connected to the power supply terminal of the inverting adder 400, and the control terminal of the switch module 500 receives a control signal EN.
Further, referring to fig. 6, in the present embodiment, the switch module 500 includes: a first switch S1 and a second switch S2. A first terminal of the first switch S1 receives the first supply voltage VS +, a second terminal of the first switch S1 is connected to the first supply terminal of the inverting adder 400, and a control terminal of the first switch S1 receives the control signal EN. A first terminal of the second switch S2 receives the second supply voltage VS-, a second terminal of the second switch S2 is connected to the second supply terminal of the inverting adder 400, and a control terminal of the second switch S2 receives the control signal EN. The first switch S1 and the second switch S2 are single-pole single-throw switches. Illustratively, the first switch S1 and the second switch S2 are both NMOS transistors or both NPN transistors. The first switch S1 and the second switch S2 are disposed in the switch module 500 to respectively control the positive and negative power supply voltages required by the inverting adder 400, and are simultaneously turned on/off based on the same control signal EN, so that the control effect and the adjustable range of the power supply timing sequence of the equalizer driving circuit can be enhanced. The first switch and the second switch are arranged in the switch module to respectively control the positive power supply voltage and the negative power supply voltage required by the inverting adder, and meanwhile, the switching-on and the switching-off are controlled simultaneously based on the same control signal, so that the control effect and the adjustable range are enhanced.
Alternatively, in other embodiments of the present invention, the switch module 500 may be a double-pole double-throw switch, receiving the control signal EN, and simultaneously connecting/disconnecting the first power supply terminal of the inverting adder 400 to the first power supply voltage VS + input terminal and the second power supply terminal of the inverting adder 400 to the second power supply voltage VS-input terminal according to the control signal EN.
When the control signal EN is not powered on, the control switch module 500 is turned off, the power supply terminal of the inverting adder 400 does not receive the first power supply voltage VS + and the second power supply voltage VS-, the inverting adder 400 is in the non-operating state, and no driving signal FB03 is output at this time. Referring to fig. 7a, when the power is turned on, the control signal EN powers up, so as to control the switch module 500 to be turned on, the first power supply voltage VS + and the second power supply voltage VS-are respectively provided to the first power supply terminal and the second power supply terminal of the inverting adder 400, the inverting adder 400 is in a normal working state, and then the inverting adder 400 performs reverse bias amplification on the received reference voltage signal FB01 and the bias voltage signal FB02, so as to achieve normal output of the driving signal FB 03; at the time of shutdown, referring to fig. 7b, the control signal EN is powered down first, so that the inverting adder 400 is in an inactive state, and no driving signal FB03 is output at the time of shutdown. Therefore, the abnormal condition of the driving signal output by the inverting adder is avoided, the flicker is avoided when the power is turned on and turned off, and the product quality is improved.
Further, as shown in fig. 5, the equalizer drive circuit further includes: a power module 100, a reference voltage generating unit 200, and a bias voltage generating unit 300. The power supply module 100 comprises a first output providing a second supply voltage VS-and a second output providing a third supply voltage AVDD. A first terminal of the reference voltage generating unit 200 is connected to the second output terminal of the power module 100 to receive the third supply voltage AVDD, and a second terminal of the reference voltage generating unit 200 is connected to the reference voltage signal input terminal. A first terminal of the bias voltage generating unit 300 is connected to the first output terminal of the power module 100 to receive the second supply voltage VS-, and a second terminal of the bias voltage generating unit 300 is connected to the bias voltage signal input terminal. That is, the reference voltage generating unit 200 is configured to generate the reference voltage signal FB01 according to the third supply voltage AVDD and provide the reference voltage signal FB01 to the first input terminal of the inverting adder 400, and the offset voltage generating unit 300 is configured to generate the offset voltage signal FB02 according to the second supply voltage VS-and provide the offset voltage signal FB02 to the second input terminal of the inverting adder 400.
Further, the equalizer drive circuit further includes: a first operational amplifier and a second operational amplifier. The first operational amplifier is connected between the second end of the reference voltage generating unit 200 and the reference voltage signal input end, and the second operational amplifier is connected between the second end of the bias voltage generating unit 300 and the bias voltage signal input end. The first operational amplifier and the second operational amplifier can respectively amplify and output the output signals of the reference voltage generating unit 200 and the bias voltage generating unit 300, thereby improving the signal quality of the reference voltage signal FB01 and the bias voltage signal FB02 output to the inverting adder 400, and simultaneously reducing the requirement on the output voltage of the power module 100 to a certain extent.
The first power supply voltage VS + is provided by a third power supply voltage AVDD. That is, in one embodiment of the present disclosure, the first supply voltage VS + is acted upon by the third supply voltage AVDD. In another embodiment of the present disclosure, the first supply voltage VS + is generated by the third supply voltage AVDD being divided by the voltage dividing unit, in this embodiment, the input terminal of the voltage dividing unit receives the third supply voltage AVDD, and the output terminal of the voltage dividing unit outputs the first supply voltage VS +.
On the other hand, the utility model also discloses a display device, this display device include the backlight and the balanced device be connected with display panel respectively to and be connected with the balanced device as above-mentioned balanced device drive circuit, this balanced device drive circuit is used for receiving control signal, and according to control signal output drive signal to balanced device.
The control signal received by the equalizer driving circuit is an enable signal for realizing the on and off functions of the backlight source. Therefore, synchronous opening and synchronous closing of the equalizer and the backlight source can be realized, the problem of startup and shutdown flickering is further solved, and the product quality is better improved.
To sum up, the utility model discloses power supply department at the required drive signal's of production balanced device inverting adder sets up switch module, and the switching on/off and then control through control signal control switch module provide to inverting adder's power supply voltage's last electric time sequence, the unusual condition appears in the drive signal's of having avoided inverting adder output waveform, so, has avoided appearing the scintillation when the switching on and shutting down, has improved product quality.
On the other hand, the enabling signal for realizing the on-off function of the backlight source is used as the control signal for controlling the switch module in the equalizer driving circuit, so that the synchronous on-off and synchronous off of the equalizer and the backlight source can be realized, the problem of on-off flicker is further improved, and the product quality is better improved.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.
Claims (9)
1. An equalizer drive circuit, comprising:
the first input end of the inverting adder is connected with the reference voltage signal input end, the second input end of the inverting adder is connected with the bias voltage signal input end, and the output end of the inverting adder outputs a driving signal;
the input end of the switch module receives power supply voltage, the output end of the switch module is connected with the power supply end of the reverse phase adder, and the control end of the switch module receives a control signal.
2. The equalizer drive circuit of claim 1, wherein the switching module comprises:
a first switch, a first end of which receives a first supply voltage, a second end of which is connected to a first supply end of the inverting adder, and a control end of which receives the control signal;
and a first end of the second switch receives a second power supply voltage, a second end of the second switch is connected with a second power supply end of the inverting adder, and a control end of the second switch receives the control signal.
3. The equalizer drive circuit of claim 2, wherein the first switch and the second switch are both NMOS transistors or are both NPN transistors.
4. The equalizer drive circuit according to claim 2, further comprising:
a power module including a first output terminal providing the second supply voltage and a second output terminal providing a third supply voltage;
a first end of the reference voltage generating unit is connected with the second output end of the power supply module, and a second end of the reference voltage generating unit is connected with the reference voltage signal input end;
and a first end of the bias voltage generating unit is connected with a first output end of the power supply module, and a second end of the bias voltage generating unit is connected with the bias voltage signal input end.
5. The equalizer drive circuit according to claim 4, further comprising:
the first operational amplifier is connected between the second end of the reference voltage generating unit and the reference voltage signal input end;
and the second operational amplifier is connected between the second end of the bias voltage generating unit and the bias voltage signal input end.
6. The equalizer drive circuit according to claim 5, further comprising:
and the input end of the voltage division unit receives the third power supply voltage, and the output end of the voltage division unit outputs the first power supply voltage.
7. The equalizer drive circuit of claim 1, wherein the inverting adder comprises:
a third operational amplifier;
the first resistor is connected between the inverting input end of the third operational amplifier and the reference voltage signal input end;
a second resistor connected between the inverting input terminal of the third operational amplifier and the bias voltage signal input terminal;
the third resistor is connected between the non-inverting input end and the grounding end of the third operational amplifier;
a fourth resistor connected between the inverting input terminal of the third operational amplifier and the output terminal of the third operational amplifier;
the fifth resistor is connected between the first power supply end and the grounding end of the inverting adder; and
and the sixth resistor is connected between the second power supply end of the inverting adder and the grounding end.
8. A display device, comprising: a display panel, a backlight, an equalizer, and an equalizer drive circuit according to any one of claims 1 to 7;
the backlight source is connected with the display panel to provide backlight brightness for the display panel;
the equalizer is connected with the display panel;
the equalizer drive circuit is connected with the equalizer and used for receiving a control signal and outputting a drive signal to the equalizer.
9. The display device according to claim 8, wherein the control signal received by the equalizer drive circuit is an enable signal of the backlight source.
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| CN202022259487.9U CN213277410U (en) | 2020-10-12 | 2020-10-12 | Equalizer drive circuit and display device |
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| CN202022259487.9U CN213277410U (en) | 2020-10-12 | 2020-10-12 | Equalizer drive circuit and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114822402A (en) * | 2022-06-30 | 2022-07-29 | 惠科股份有限公司 | Drive circuit, display module and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114822402A (en) * | 2022-06-30 | 2022-07-29 | 惠科股份有限公司 | Drive circuit, display module and display device |
| CN114822402B (en) * | 2022-06-30 | 2022-09-20 | 惠科股份有限公司 | Drive circuit, display module and display device |
| US11749209B1 (en) | 2022-06-30 | 2023-09-05 | HKC Corporation Limited | Drive circuit, display assembly, and display device |
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