CN213186079U - Locking detection circuit of phase-locked loop - Google Patents
Locking detection circuit of phase-locked loop Download PDFInfo
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- CN213186079U CN213186079U CN202021744434.XU CN202021744434U CN213186079U CN 213186079 U CN213186079 U CN 213186079U CN 202021744434 U CN202021744434 U CN 202021744434U CN 213186079 U CN213186079 U CN 213186079U
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Abstract
The utility model provides a locking detection circuitry of phase-locked loop mainly includes locking detection main circuit and input circuit, input detection circuitry is used for detecting the frequency range of the input clock signal of phase-locked loop, with the output characterization the mode signal of input signal frequency range, the locking detection main circuit basis the different count modes of mode signal's state selection are right phase-locked loop and input clock signal and output feedback clock signal count to count result output locking detection signal under every count mode, with the instruction current whether the phase-locked loop is in the lock state. The utility model provides a locking detection circuitry detection error is low locking time difference of the different input clock frequency of phase-locked loop is less, circuit structure is simple and easily realize.
Description
Technical Field
The utility model belongs to the technical field of the phase-locked loop, specifically relate to a locking detection circuitry of phase-locked loop.
Background
With the development of integrated circuits, phase-locked loops are widely used in chips in various fields to provide accurate and stable clock signals. The accuracy and stability of the output clock signal of the phase-locked loop have a great influence on the application of the next stage, and therefore, it is necessary to detect the frequency locking state of the phase-locked loop.
The frequency lock detection of the phase-locked loop can be realized by various methods, such as a lock detection method based on a PFD circuit and an analog circuit. Lock detection based on PFD circuits may result in false positives due to the fact that narrow pulses generated at high input frequencies may not be detected correctly. The detection based on the analog circuit needs to carefully calculate the filter capacitor and the pull-up and series resistors in the circuit, the detection mode is complex, and in addition, the detection result is more easily influenced by the process temperature through the detection realized by the analog circuit, so that the method has high requirement on the process temperature.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a detection circuitry of phase-locked loop to solve the problem that the detection that current locking detection circuitry exists is inflexible, the error is great, high, difficult realization are required to the process temperature.
A lock detection circuit for a phase locked loop, comprising: a lock detection main circuit and an input detection circuit,
the input detection circuit is configured to receive an input clock signal of a phase locked loop to output a mode signal, a state of the mode signal representing a frequency range of the input clock signal,
the lock detection main circuit is configured to receive the input clock signal, a feedback clock signal and the mode signal output lock detection signal, the feedback clock signal is an output clock feedback signal of the phase-locked loop, the output clock signal is fed back to an input end through a frequency divider,
the locking detection main circuit selects different counting modes according to different states of the mode signal, counts the input clock signal and the feedback clock signal respectively in each counting mode, calculates a difference value between a count value of the feedback clock signal and a count value of the input clock signal in a counting time period according to a counting result, indicates that the phase-locked loop is currently in a locking state when the difference value is smaller than or equal to a preset difference value, and indicates that the phase-locked loop is currently in an unlocking state when the difference value is larger than the preset difference value.
Preferably, the lock detection main circuit has a reset receiving port configured to receive a reset signal, where the reset signal is a system reset signal of a system in which the lock detection circuit is located.
Preferably, the input detection circuit divides a frequency range of the input clock signal into a first range and a second range such that a state of the mode signal has a first state corresponding to the first range and a second state corresponding to the second range, the lock detection main circuit counts the input clock signal and the feedback clock signal in a first count mode when the mode signal is in the first state, and counts the input clock signal and the feedback clock signal in a second count mode when the mode signal is in the second state.
Preferably, the first range is a range in which the frequency of the input clock signal is higher than a preset frequency value, the second range is a range in which the frequency of the clock signal is lower than the preset frequency value,
the first counting mode is a mode of counting the number of cycles of the input clock signal and the feedback clock signal by using a first digit counter, the second counting mode is a mode of counting the number of cycles of the input clock signal and the feedback clock signal by using a second digit counter, and the second digit is greater than the first digit.
Preferably, the second number of bits is twice the first number of bits.
Preferably, the first state is a high level, the second state is a low level,
the lock detection being high indicating that the phase locked loop is currently in a locked state,
and when the locking detection is low level, indicating that the phase-locked loop is in the unlocking state currently.
Preferably, the phase lock detection main circuit includes: a first counter, a second counter and a first comparison circuit,
the first counter receives the mode signal, the reset signal, and an input clock signal, the second counter receives the mode signal, the reset signal, and a feedback clock signal,
the first counter and the second counter select different counting digits according to different states of the mode signal, so that after the reset signal resets the first counter and the second counter, the input clock signal and the feedback clock signal are respectively counted to respectively output a first counting value and a second counting value,
the first comparison circuit is used for receiving the first count value and the second count value, and comparing whether the difference value between the first count value and the second count value is smaller than a preset difference value or not so as to output the locking detection signal.
Preferably, the input detection circuit includes: a clock circuit and a second comparison circuit, the clock circuit is used for generating a reference clock signal, so that the frequency of the reference clock signal is the preset frequency value,
the second comparison circuit is used for comparing the frequency of the input clock signal with the frequency of the reference clock signal and outputting the mode signal according to the comparison result.
Preferably, the clock circuit is a clock oscillator,
the frequency value of the clock signal generated by the clock oscillator is the middle value of the frequency range of the input clock signal.
Preferably, the phase locked loop comprises a phase detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider,
the phase detector compares phases of the input clock signal and the feedback clock signal to output an up control signal and a down control signal,
the upper control signal and the lower control signal respectively control the charge pump to add charges and subtract charges on the output line of the charge pump,
the voltage on the output line of the charge pump is filtered by the low-pass filter to output a control voltage,
the control voltage is used for controlling the voltage-controlled oscillator to output the output clock signal,
and the frequency divider divides the frequency of the output clock signal and outputs the feedback clock signal.
The utility model discloses beneficial effect: the frequency range of an input clock signal of the phase-locked loop is detected through the input detection circuit so as to output a mode signal representing the frequency range of the input signal, the phase-locked loop, the input clock signal and the output feedback clock signal are counted in different counting modes selected by the locking detection main circuit according to the state of the mode signal, and a locking detection signal is output according to a counting result in each counting mode so as to indicate whether the phase-locked loop is in a locking state or not at present, the detection error of the locking detection circuit is low, the locking time difference of different input clock frequencies of the phase-locked loop is small, and the circuit structure is simple and easy to realize.
Drawings
Fig. 1 is a block diagram of a lock detection circuit for a phase-locked loop according to the present invention,
fig. 2 is a schematic circuit structure diagram of a specific implementation manner of the lock detection main circuit according to the present invention;
fig. 3 is a schematic circuit diagram of an embodiment of an input detection circuit according to the present invention;
fig. 4 is a block diagram of a phase-locked loop circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments generated by the ordinary skilled in the art without creative work all belong to the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only intended to indicate technical belongings or features of the present invention.
Fig. 1 is a block diagram illustrating a lock detection circuit for a phase-locked loop according to the present invention, and fig. 2 is a schematic circuit diagram illustrating a specific implementation of a main lock detection circuit according to the present invention; fig. 3 is a schematic circuit diagram of an embodiment of an input detection circuit according to the present invention; fig. 4 is a block diagram of a phase-locked loop circuit according to the present invention. The present invention provides a lock detection circuit for a phase-locked loop, which will be described in detail with reference to fig. 1 to 4.
In the embodiment of the present invention, the structure of the phase-locked loop is as shown in fig. 4, and the phase-locked loop includes: the device comprises a phase discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider. The phase discriminator compares the phases of the input clock signal IN _ CK and the feedback clock signal FB _ CK to output an upper control signal UP and a lower control signal DN, the upper control signal UP and the lower control signal DN respectively control the charge pump to add charges and subtract charges on an output line of the charge pump, the voltage on the output line of the charge pump is filtered by the low-pass filter to output a control voltage, the control voltage is used for controlling the voltage-controlled oscillator to output the output clock signal OUT _ CK, and the frequency divider divides the frequency of the output clock signal and outputs the feedback clock signal FB _ CK. In other embodiments, the structure of the phase-locked loop is not limited to the structure shown in fig. 4.
As shown in fig. 1, the lock detection circuit of the phase-locked loop provided by the present invention mainly comprises: a lock detection main circuit and an input detection circuit. The input detection circuit is configured to receive an input clock signal IN _ CK of a phase-locked loop to output a MODE signal MODE, a state of the MODE signal MODE representing a frequency range of the input clock signal, and the lock detection main circuit is configured to receive the input clock signal INT _ CK, the feedback clock signal FB _ CK and the MODE signal MODE to output a lock detection signal DLK.
The lock detection main circuit selects different counting MODEs according to different states of the MODE signal MODE, counts the input clock signal IN _ CK and the feedback clock signal FB _ CK respectively IN each counting MODE, calculates a difference value between a count value of the feedback clock signal and a count value of the input clock signal IN a counting time period according to a counting result, indicates that the phase-locked loop is currently IN a lock state when the difference value is smaller than or equal to a preset difference value, and indicates that the phase-locked loop is currently IN an unlock state when the difference value is larger than the preset difference value. As shown in fig. 1, the lock detection main circuit has a RESET receiving port configured to receive a RESET signal RESET for resetting the lock detection main circuit, the RESET signal being a system RESET signal of a system in which the lock detection circuit is located.
In an embodiment of the present invention, the input detection circuit divides the frequency range of the input clock signal into a first range and a second range, so that the state of the mode signal has a first state corresponding to the first range and a second state corresponding to the second range, when the mode signal is in the first state, the lock detection main circuit counts the input clock signal and the feedback clock signal respectively with a first count mode, and when the mode signal is in the second state, the lock detection main circuit counts the input clock signal and the feedback clock signal respectively with a second count mode. The first range is a range in which the frequency of the input clock signal is higher than a preset frequency value, and the second range is a range in which the frequency of the clock signal is lower than the preset frequency value. The first counting mode is a mode in which the number of cycles of the input clock signal and the feedback clock signal is counted by using a first-digit counter, and the second counting mode is a mode in which the number of cycles of the input clock signal and the feedback clock signal is counted by using a second-digit counter, where the second digit is greater than the first digit, for example, when the first digit is N digits, the second digit is 2N digits. Since the frequency of the input clock signal IN _ CK is divided into two ranges IN this embodiment, that is, the frequency of the input clock signal IN _ CK only needs to be compared with a reference preset frequency value, the MODE signal MODE is a one-bit binary number, and thus the first state of the MODE signal MODE is one of a high level and a first level, and the second state is the other of the high level and the low level. In this embodiment, the first state is set to be a high level, the second state is a low level, the lock detection is a high level, which indicates that the phase-locked loop is currently in a locked state, and the lock detection is a low level, which indicates that the phase-locked loop is currently in an unlocked state.
Specifically, as shown in fig. 2, the utility model provides a lock-in detection main circuit includes: the device comprises a first counter, a second counter and a first comparison circuit. The first counter receives the MODE signal MODE, the RESET signal RESET, and an input clock signal IN _ CK, and the second counter receives the MODE signal MODE, the RESET signal RESET, and a feedback clock signal FB _ CK. The first and second counters select different numbers of counting bits according to different states of the MODE signal MODE to count the input clock signal and the feedback clock signal, respectively, after the reset signal resets the first and second counters, to output a first count value C1 and a second count value C2, respectively. The first comparison circuit is configured to receive the first count value C1 and the second count value C2, and compare whether a magnitude of a difference between the first count value C1 and the second count value C2 is smaller than a preset difference to output the lock detection signal DLK. In this embodiment, the counting refers to counting the number of cycles of the signal, and may count sequentially when the rising edge of each signal arrives. When the first count value C1 reaches a predetermined value, the first counter sends the first count value C1 to the first comparison circuit, and after the first count value C1 of the first comparison circuit, the first comparison circuit is configured to compare whether a difference between a last second count value C2 output by the second comparator and the first count value C1 reaching the predetermined value is within a preset difference range, if so, the lock detection signal indicates that the current phase-locked loop is IN a locked state, that is, the feedback clock signal FB _ CK is locked to the input clock signal IN _ CK, otherwise, the phase-locked loop is IN an unlocked state. Here, for example, if the predetermined value of the first count value C1 is set to 18 cycles, i.e., C1 is 18, and the value of the last count signal received by the second counter is 17 cycles, i.e., the second count value is C2 is 17, since the difference between C2 and C1 is smaller than a preset difference, e.g., the preset difference is 2, the first comparing circuit outputs the lock detection signal DLK at a high level for 17 cycles. The preset difference value needs to be selected and set correspondingly according to the number of cycles of the input clock signal IN _ CK IN the counting period. If the second count value C2 is 16 cycles and the first count value C1 is 18 cycles, then the lock detection signal output by the first comparison circuit indicates "out-of-lock".
As shown IN fig. 3, a clock circuit for generating a reference clock signal such that the frequency of the reference clock signal REF _ CK is the preset frequency value, and a second comparison circuit for comparing the frequency of the input clock signal IN _ CK and the frequency of the reference clock signal REF _ CK and outputting the MODE signal MODE according to the comparison result. The clock circuit is a clock oscillator, and the frequency value of the clock signal generated by the clock oscillator is the middle value of the frequency range of the input clock signal.
IN this embodiment, according to a frequency range of an input clock signal of a phase-locked loop, a frequency of a reference clock signal RFE _ CK generated by a clock circuit IN the input detection circuit is set to be a middle value of a frequency of the input clock signal IN _ CK, when the frequency of IN _ CK is greater than the frequency of the reference clock signal REF _ CK, the frequency of the input clock signal is greater, and a lock time may be faster during the period, so that the lock time needs to be increased.
On the contrary, when the frequency of the IN _ CK is smaller than that of the reference clock signal REF _ CK, the frequency of the input clock signal is smaller, and the lock time may be slower during this period, so we need to reduce the lock time, MODE is low, the lock detection main circuit is controlled to adopt an N-bit counter MODE, the lock frequency count time is R × N tin _ CK, R is any integer period, N is the number of counter bits, tin _ CK is the period of the input signal IN _ CK, at this time, the overall lock time is reduced, and the output delay of the lock signal DLK is reduced. It is apparent that the present invention is advantageous to reduce the frequency lock time difference in the case of a wide input range by selecting a corresponding count mode according to the frequency range of the input clock signal. In addition, the clock circuit may employ a mode generating multi-step reference frequency signal such that the mode signal has more than two states, and perform the lock detection in a manner of selecting more than two counting modes, so as to more accurately compensate for the lock frequency time.
To sum up, the utility model provides a locking detection circuitry, the frequency range through the input clock signal of input detection circuitry detection phase-locked loop, with the output characterization the mode signal of input signal frequency range is detecting the main circuit basis through the locking different count modes of mode signal's state selection are right phase-locked loop and input clock signal and output feedback clock signal count to count according to the count result output locking detection signal under every count mode, with indicate current whether the phase-locked loop is in the lock state, locking detection circuitry detection error is low the locking time difference of the different input clock frequencies of phase-locked loop is less, circuit structure is simple and easily realize.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A lock detection circuit for a phase locked loop, comprising: a lock detection main circuit and an input detection circuit,
the input detection circuit is configured to receive an input clock signal of a phase locked loop to output a mode signal, a state of the mode signal representing a frequency range of the input clock signal,
the lock detection main circuit is configured to receive the input clock signal, a feedback clock signal and the mode signal output lock detection signal, the feedback clock signal is an output clock feedback signal of the phase-locked loop, the output clock signal is fed back to an input end through a frequency divider,
the locking detection main circuit selects different counting modes according to different states of the mode signal, counts the input clock signal and the feedback clock signal respectively in each counting mode, calculates a difference value between a count value of the feedback clock signal and a count value of the input clock signal in a counting time period according to a counting result, indicates that the phase-locked loop is currently in a locking state when the difference value is smaller than or equal to a preset difference value, and indicates that the phase-locked loop is currently in an unlocking state when the difference value is larger than the preset difference value.
2. The lock detection circuit according to claim 1, wherein the lock detection main circuit has a reset receiving port configured to receive a reset signal, and the reset signal is a system reset signal of a system in which the lock detection circuit is located.
3. The lock detection circuit of claim 2,
the input detection circuit divides a frequency range of the input clock signal into a first range and a second range such that a state of the mode signal has a first state corresponding to the first range and a second state corresponding to the second range, the lock detection main circuit counts the input clock signal and the feedback clock signal in a first count mode when the mode signal is in the first state, and counts the input clock signal and the feedback clock signal in a second count mode when the mode signal is in the second state.
4. The lock detection circuit according to claim 3, wherein the first range is a range in which the frequency of the input clock signal is higher than a preset frequency value, the second range is a range in which the frequency of the clock signal is lower than the preset frequency value,
the first counting mode is a mode of counting the number of cycles of the input clock signal and the feedback clock signal by using a first digit counter, the second counting mode is a mode of counting the number of cycles of the input clock signal and the feedback clock signal by using a second digit counter, and the second digit is greater than the first digit.
5. The lock detection circuit of claim 4, wherein the second number of bits is twice the first number of bits.
6. The lock detection circuit according to claim 4, wherein the first state is a high level, the second state is a low level,
the lock detection being high indicating that the phase locked loop is currently in a locked state,
and when the locking detection is low level, indicating that the phase-locked loop is in the unlocking state currently.
7. The lock detection circuit according to claim 3, wherein the lock detection main circuit comprises: a first counter, a second counter and a first comparison circuit,
the first counter receives the mode signal, the reset signal, and an input clock signal, the second counter receives the mode signal, the reset signal, and a feedback clock signal,
the first counter and the second counter select different counting digits according to different states of the mode signal, so that after the reset signal resets the first counter and the second counter, the input clock signal and the feedback clock signal are respectively counted to respectively output a first counting value and a second counting value,
the first comparison circuit is used for receiving the first count value and the second count value, and comparing whether the difference value between the first count value and the second count value is smaller than a preset difference value or not so as to output the locking detection signal.
8. The lock detection circuit according to claim 4, wherein the input detection circuit comprises: a clock circuit and a second comparison circuit, the clock circuit is used for generating a reference clock signal, so that the frequency of the reference clock signal is the preset frequency value,
the second comparison circuit is used for comparing the frequency of the input clock signal with the frequency of the reference clock signal and outputting the mode signal according to the comparison result.
9. The lock detection circuit of claim 8, wherein the clock circuit is a clock oscillator,
the frequency value of the clock signal generated by the clock oscillator is the middle value of the frequency range of the input clock signal.
10. The lock-in detection circuit of claim 1, wherein the phase-locked loop includes a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider,
the phase detector compares phases of the input clock signal and the feedback clock signal to output an up control signal and a down control signal,
the upper control signal and the lower control signal respectively control the charge pump to add charges and subtract charges on the output line of the charge pump,
the voltage on the output line of the charge pump is filtered by the low-pass filter to output a control voltage,
the control voltage is used for controlling the voltage-controlled oscillator to output the output clock signal,
and the frequency divider divides the frequency of the output clock signal and outputs the feedback clock signal.
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| CN202021744434.XU CN213186079U (en) | 2020-08-19 | 2020-08-19 | Locking detection circuit of phase-locked loop |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115361015A (en) * | 2022-10-14 | 2022-11-18 | 成都本原聚能科技有限公司 | Phase-locked loop circuit, control method thereof and phase-locked loop chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115361015A (en) * | 2022-10-14 | 2022-11-18 | 成都本原聚能科技有限公司 | Phase-locked loop circuit, control method thereof and phase-locked loop chip |
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