CN213149744U - POE circuit convenient to management - Google Patents
POE circuit convenient to management Download PDFInfo
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- CN213149744U CN213149744U CN202022260585.4U CN202022260585U CN213149744U CN 213149744 U CN213149744 U CN 213149744U CN 202022260585 U CN202022260585 U CN 202022260585U CN 213149744 U CN213149744 U CN 213149744U
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- poe
- chip
- control unit
- management
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Abstract
The utility model belongs to the technical field of the POE power supply technique and specifically relates to indicate a POE circuit convenient to management, including switch owner chip U1, little the control unit U11 and POE chip SU2, little the control unit U11 is used for storing switch owner chip U1's configuration data and POE chip SU 2's configuration data, and switch owner chip U1's control end is connected with little the control unit U11's first output, and POE chip SU 2's control end is connected with little the control unit U11's second output. The utility model discloses an utilize little the control unit to store the configuration data of switch owner chip and POE chip SU 2's configuration data to utilize little the control unit to dispose switch owner chip and POE chip SU2 respectively, thereby when making the user manage switch owner chip and POE chip SU2, need not to burn the software many times, simplified the management step and reached the effect of the management of being convenient for.
Description
Technical Field
The utility model relates to a POE power supply technical field especially indicates a POE circuit convenient to management.
Background
The core chips in the POE circuit are a switch main chip and a POE chip SU 2. To set the configuration of the switch master chip, an EEPROM storing configuration data of the switch master chip is often provided in the circuit. In order to set the configuration of the POE chip SU2, a micro control unit storing configuration data of the POE chip SU2 is often provided in the circuit. This leads to the user to need to burn EEPROM and little the control unit respectively when managing switch main chip and POE chip SU2, leads to POE circuit's management loaded down with trivial details.
Disclosure of Invention
The utility model discloses problem to prior art provides a POE circuit that can simplify the management step and be convenient for manage.
The utility model adopts the following technical scheme: the utility model provides a POE circuit convenient to management, includes switch main chip U1, little the control unit U11 and POE chip SU2, little the control unit U11 is used for storing switch main chip U1's configuration data and POE chip SU 2's configuration data, switch main chip U1's control end with little the control unit U11's first output is connected, POE chip SU 2's control end with little the control unit U11's second output is connected.
Preferably, the model of the switch master chip U1 is IP 178G.
Preferably, the model of the POE chip SU2 is IP 804A.
Preferably, the POE circuit convenient to manage further includes an SMI bus, and the micro control unit U11 is connected to the POE chip SU2 through the SMI bus.
Preferably, the POE circuit for facilitating management further includes an I2C communication line, and the micro control unit U11 is connected to the switch master chip U1 through an I2C communication line.
Preferably, the POE circuit for facilitating management further includes an analog power supply port AVCC connected to an anode of the diode SS34, and a diode SS34, wherein a cathode of the diode SS34 is connected to a power supply terminal of the micro control unit U11.
Preferably, the POE circuit convenient to manage further includes a resistor RP1 and a digital power supply port DVCC connected to the power supply terminal of the switch main chip U1, the analog power supply port AVCC is connected to the digital power supply port DVCC through a resistor RP1, and the resistor RP1 is a 0 ohm resistor.
Preferably, a register is arranged inside the switch master chip U1, and a control terminal of the switch master chip U1 is connected with an input terminal of the register.
The utility model has the advantages that: through the configuration data that utilizes little the control unit to store switch owner chip and POE chip SU 2's configuration data to utilize little the control unit to dispose switch owner chip and POE chip SU2 respectively, thereby when making the user manage switch owner chip and POE chip SU2, need not to burn the software many times, simplified the management step and reached the effect of the management of being convenient for.
Drawings
Fig. 1 is a circuit diagram of the switch main chip U1 of the present invention.
Fig. 2 is a circuit diagram of the POE chip SU2 of the present invention.
Fig. 3 is a circuit diagram of the micro control unit U11 according to the present invention.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present invention will be further described with reference to the following examples and drawings, which are not intended to limit the present invention. The present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1 to 3, a POE circuit convenient to manage, including switch main chip U1, microcontrol unit U11 and POE chip SU2, microcontrol unit U11 is used for storing switch main chip U1's configuration data and POE chip SU 2's configuration data, switch main chip U1's control end with microcontrol unit U11's first output is connected, POE chip SU 2's control end with microcontrol unit U11's second output is connected.
Through getting rid of EEPROM, utilize microcontrol unit U11 to store switch main chip U1's configuration data and POE chip SU 2's configuration data, and utilize microcontrol unit U11 to dispose switch main chip U1 and POE chip SU2 respectively, thereby when making the user manage switch main chip and POE chip SU2, need not to burn the software many times, simplified the management step and reached the effect of the management of being convenient for.
Specifically, the model of the switch master chip U1 is IP 178G.
Specifically, the model of the POE chip SU2 is IP 804A.
As shown in fig. 2 and fig. 3, the POE circuit for facilitating management further includes an SMI bus, and the mcu U11 is connected to the POE chip SU2 through the SMI bus, so as to implement communication between the mcu U11 and the POE chip SU 2.
As shown in fig. 1 and 3, the POE circuit for facilitating management further includes an I2C communication line, and the mcu U11 is connected to the switch main chip U1 through an I2C communication line. Thereby realizing the communication between the micro control unit U11 and the switch main chip U1.
As shown in fig. 3, the POE circuit for facilitating management further includes an analog power supply port AVCC connected to an anode of the diode SS34, and a diode SS34, wherein a cathode of the diode SS34 is connected to a power supply terminal of the micro control unit U11. Thereby preventing the current from flowing backwards.
As shown in fig. 1, the POE circuit convenient for management further includes a resistor RP1 and a digital power supply port DVCC connected to a power supply terminal of the switch main chip U1, the analog power supply port AVCC is connected to the digital power supply port DVCC through a resistor RP1, and the resistor RP1 is a 0 ohm resistor. Therefore, the digital power supply port DVCC and the analog power supply port AVCC are prevented from influencing each other under the condition of ensuring the connection of the digital power supply port DVCC and the analog power supply port AVCC.
Specifically, a register is arranged inside the switch main chip U1, and a control end of the switch main chip U1 is connected with an input end of the register.
The above description is only for the preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention is disclosed in the preferred embodiment, it is not limited to the above description, and any person skilled in the art can make some changes or modifications to equivalent embodiments without departing from the scope of the present invention, but all the technical solutions of the present invention are within the scope of the present invention.
Claims (8)
1. A POE circuit convenient to management which characterized in that: including switch main chip U1, little the control unit U11 and POE chip SU2, little the control unit U11 is used for storing switch main chip U1's configuration data and POE chip SU 2's configuration data, switch main chip U1's control end with little the control unit U11's first output is connected, POE chip SU 2's control end with little the control unit U11's second output is connected.
2. The POE circuit facilitating management of claim 1, wherein: the model of the switch main chip U1 is IP 178G.
3. The POE circuit facilitating management of claim 1, wherein: the POE chip SU2 is IP 804A.
4. The POE circuit facilitating management of claim 1, wherein: the POE circuit convenient to manage further comprises an SMI bus, and the micro control unit U11 is connected with the POE chip SU2 through the SMI bus.
5. The POE circuit facilitating management of claim 1, wherein: the POE circuit convenient to manage further comprises an I2C communication line, and the micro control unit U11 is connected with the switch main chip U1 through an I2C communication line.
6. The POE circuit facilitating management of claim 1, wherein: the POE circuit convenient to manage further comprises an analog power supply port AVCC and a diode SS34, the analog power supply port AVCC is connected with the anode of a diode SS34, and the cathode of the diode SS34 is connected with the power supply end of the micro-control unit U11.
7. The POE circuit facilitating management of claim 6, wherein: POE circuit convenient to management still includes resistance RP1 and the digital power supply port DVCC who is connected with the supply terminal of switch main chip U1, analog power supply port AVCC passes through resistance RP1 and is connected with digital power supply port DVCC, resistance RP1 is 0 ohm resistance.
8. The POE circuit facilitating management of claim 1, wherein: the switch main chip U1 is internally provided with a register, and the control end of the switch main chip U1 is connected with the input end of the register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022260585.4U CN213149744U (en) | 2020-10-12 | 2020-10-12 | POE circuit convenient to management |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022260585.4U CN213149744U (en) | 2020-10-12 | 2020-10-12 | POE circuit convenient to management |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213149744U true CN213149744U (en) | 2021-05-07 |
Family
ID=75719907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022260585.4U Active CN213149744U (en) | 2020-10-12 | 2020-10-12 | POE circuit convenient to management |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213149744U (en) |
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2020
- 2020-10-12 CN CN202022260585.4U patent/CN213149744U/en active Active
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