CN213072460U - Synchronous rectification control circuit and voltage converter - Google Patents
Synchronous rectification control circuit and voltage converter Download PDFInfo
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- CN213072460U CN213072460U CN202022150023.4U CN202022150023U CN213072460U CN 213072460 U CN213072460 U CN 213072460U CN 202022150023 U CN202022150023 U CN 202022150023U CN 213072460 U CN213072460 U CN 213072460U
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Abstract
The synchronous rectification control circuit provides a synchronous rectifier tube preparation conduction signal and a synchronous rectifier tube conduction control signal, the two signals jointly act on conduction control of the synchronous rectifier tube, the synchronous rectifier tube conduction control signal forbids conduction of the synchronous rectifier tube in parasitic oscillation time, false conduction of the synchronous rectifier tube in the parasitic oscillation time can be avoided, the synchronous rectification effect is improved, and the power efficiency of the voltage converter is improved.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to synchronous rectification control circuit and voltage converter.
Background
As shown in fig. 1, the flyback voltage converter (power converter) includes a primary circuit and a secondary circuit, the primary circuit and the secondary circuit are isolated by a transformer T, the primary circuit includes a primary switch Q on an electrical loop, energy can be transferred to the secondary circuit by switching of the primary switch Q, the secondary circuit includes an output capacitor C0 connected in series with a secondary side of the transformer T and a synchronous rectifier SR disposed between the secondary side of the transformer T and the output capacitor C0, and two ends of the output capacitor are connected to a load. In order to improve the power efficiency, the synchronous rectifier on the secondary side usually uses a synchronous rectifier with lower resistance than a diode or a body diode and low synchronous conduction state loss, and the high-efficiency rectification function is realized by timely controlling the conduction and the disconnection of the synchronous rectifier.
In the voltage-controlled synchronous rectifier, the conduction time of the synchronous rectifier is generally determined by detecting the drain-source voltage Vds of the synchronous rectifier SR, and as shown in fig. 2, when Vds is detected to be smaller than the second threshold voltage Vth2, the body diode of the synchronous rectifier is considered to be turned on, and the synchronous rectifier can be controlled to be turned on.
In the prior art, when the circuit operates in a DCM (Discontinuous Conduction Mode), the circuit may generate parasitic oscillation, which may also cause the body diode of the synchronous rectifier SR to be turned on, and further erroneously turn on the synchronous rectifier SR under the parasitic oscillation, as shown in fig. 2, in the prior art, a PWM (Pulse Width Modulation) signal correspondingly controls the synchronous rectifier SR to be turned on, and a Blank signal follows the PWM signal, and the Blank signal corresponds to the parasitic oscillation time, and controls the synchronous rectifier SR to be kept off, so as to prevent erroneous Conduction of the synchronous rectifier SR. However, if the power supply needs to be compatible with CCM (Continuous Conduction Mode), QR (quadrature-resonance) Mode, and DCM operation, the Blank time of the Blank signal may prevent the synchronous rectifier SR from normally conducting in the QR and CCM operation modes, thereby reducing the power supply efficiency.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a synchronous rectification control circuit and a voltage converter, so as to improve the synchronous rectification effect and improve the power efficiency.
According to the utility model discloses an aspect provides a synchronous rectification control circuit, including synchronous rectifier tube drain-source voltage incoming end and synchronous rectifier tube grid control signal output, a serial communication port, include:
the synchronous rectifier tube ready-conducting signal generating circuit comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a third reference signal input end and a synchronous rectifier tube ready-conducting signal output end;
the first comparator comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a first reference signal input end and a first comparison signal output end;
the logic circuit comprises a first input end, a second input end and a synchronous rectifier tube conduction control signal output end, wherein the first input end and the second input end are connected with the first comparison signal output end;
the second comparator comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a second reference signal input end and a second comparison signal output end;
a delay nulling circuit comprising an input connected to the first comparison signal and an output;
the first logic gate circuit comprises a first input end connected with the output end of the delay ineffectiveness circuit, a second input end connected with the second comparison signal output end and an output end connected with the reset end of the second trigger;
and the second logic gate circuit comprises a first input end connected with the preparatory conduction signal output end of the synchronous rectifier tube, a second input end connected with the conduction control signal output end of the synchronous rectifier tube and an output end connected to the grid control signal output end of the synchronous rectifier tube.
Optionally, the logic circuit comprises:
the pulse generator comprises an input end and an output end which are connected with the first comparison signal output end;
the second trigger, the position end of second trigger with impulse generator's output is connected, the output of second trigger is connected to the second input of second logic gate circuit, the output of second trigger is synchronous rectifier tube conduction control signal output.
Optionally, the synchronous rectifier tube ready-to-turn-on signal generating circuit includes:
the third comparator comprises a non-inverting input end connected with the drain-source voltage access end of the synchronous rectifier tube, an inverting input end connected with the third reference signal input end and a third comparison signal output end;
the first trigger is a reset leading trigger, the reset end of the first trigger is connected with the third comparison signal output end, the position end of the first trigger is connected with the first comparison signal output end, and the output end of the first trigger is the prepared conduction signal output end of the synchronous rectifier tube.
Optionally, the delay nullification circuit includes:
a capacitor including a first terminal connected to the positive output terminal of the current source and a second terminal connected to ground;
a switch connected in parallel with both ends of the capacitor, the switch including a switch control terminal connected with the first comparison signal output terminal;
and the fourth comparator comprises an input end connected with the first end of the capacitor, a fourth reference signal input end and an output end, and the output end of the fourth comparator is the output end of the delay ineffectiveness circuit.
Optionally, the delay ineffectiveness circuit further includes an inverter connected in series between the first comparison signal output terminal and the switch control terminal;
the switch is an NMOS tube, and the grid electrode of the NMOS tube is the switch control end.
Optionally, the fourth reference signal input terminal is connected to a fourth reference signal output terminal of an external fourth reference signal configuration circuit.
According to another aspect of the present invention, there is provided a voltage converter, comprising:
the transformer comprises a primary side circuit and a secondary side circuit, wherein the secondary side circuit comprises a synchronous rectifier tube;
according to the utility model provides a synchronous rectification control circuit, synchronous rectifier tube grid control signal output with the grid of synchronous rectifier tube is connected.
The utility model provides a synchronous rectification control circuit provides synchronous rectifier and prepares turn-on signal and synchronous rectifier conduction control signal, wherein, delay circuit, second comparator and first logic gate circuit judge synchronous rectifier leakage source level reducing rate according to the big or small relation of time and delay time of synchronous rectifier leakage source voltage reduction to second reference signal level, and then judge the conduction reason of the body diode of synchronous rectifier, it allows the detected signal to provide synchronous rectifier conduction, the rethread logic circuit provides synchronous rectifier conduction control signal, prepare the conduction of turn-on signal control synchronous rectifier through second logic gate circuit and synchronous rectifier, can effectively detect out the conduction reason of synchronous rectifier, forbid the mistake of synchronous rectifier in parasitic oscillation time and switch on.
The utility model provides a voltage converter includes the utility model provides a synchronous rectification control circuit, this synchronous rectification control circuit control voltage converter's vice limit circuit's synchronous rectifier tube switch on and turn-off, can avoid synchronous rectifier tube to be in the mistake of parasitic oscillation time at voltage converter's vice limit circuit and switch on, improve power efficiency.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic diagram of a flyback voltage converter according to the prior art;
FIG. 2 shows a timing diagram of control signals for a synchronous rectifier according to the prior art;
fig. 3 shows a schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention;
fig. 4 shows a timing diagram of the operation of the pulse generator according to an embodiment of the invention;
fig. 5 shows a timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The term "connected" in the specification includes both direct connection and indirect connection. An indirect connection is a connection made through an intermediate medium, such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or through an intermediate circuit or component as described in the embodiments in the specification; indirect connections may also include connections through other active or passive devices that perform the same or similar function, such as connections through circuitry or components, such as signal amplification circuitry.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 3 shows a schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
As shown in fig. 3, the synchronous rectification control circuit 100 of the embodiment of the present invention includes a first comparator COMP1, a second comparator COMP2, a third comparator COMP3, a fourth comparator COMP4, a first flip-flop T1, a second flip-flop T2, a pulse generator 101, a first logic gate circuit 102, a second logic gate circuit 103, an inverter 104, a capacitor C1, a switch S1, a current source I1, an external reference value configuration circuit 105, a resistor Rcf, and a synchronous rectifier drain-source voltage access terminal (not shown in the figure) for providing a synchronous rectifier drain-source voltage Vds. The first flip-flop T1 and the second flip-flop T2 may be reset dominant flip-flops, i.e., their output states may be set only when their reset terminals are inactive as 0.
An inverting input end of the first comparator COMP1 is connected with a drain-source voltage access end of the synchronous rectifier tube and receives a drain-source voltage Vds of the synchronous rectifier tube, a non-inverting input end of the first comparator COMP1 receives a first reference signal Vth1, and an output end of the first comparator COMP 3538 outputs a first comparison signal CU 1.
An inverting input end of the second comparator COMP2 is connected to the drain-source voltage access end of the synchronous rectifier tube, receives the drain-source voltage Vds of the synchronous rectifier tube, a non-inverting input end of the second comparator COMP2 receives the second reference signal Vth2, and an output end of the second comparator COMP2 outputs a second comparison signal CU.
The non-inverting input terminal of the third comparator COMP3 is connected to the drain-source voltage access terminal of the synchronous rectifier, receives the drain-source voltage Vds of the synchronous rectifier, the inverting input terminal receives the third reference signal Vth3, and the output terminal is connected to the set terminal S of the first flip-flop, so as to provide the first reset signal T1R (third comparison signal).
Wherein Vth1>0> Vth3> Vth 2.
The set terminal S of the first flip-flop T1 is connected to the output terminal of the first comparator COMP1, the reset terminal R is connected to the output terminal of the third comparator COMP3, and the output terminal Q provides the first control signal T1U (a synchronous rectifier ready-to-turn-on signal, which is effectively a necessary condition for turning on the synchronous rectifier).
The pulse generator 101 has an input end connected to the output end of the first comparator COMP1, and an output end connected to the set end S of the second flip-flop T2, and outputs a narrow pulse when the first comparison signal CU1 is asserted, and the set initializes the output state of the second flip-flop T2.
The reset terminal R of the second flip-flop T2 receives the second reset signal T2R, and the output terminal Q outputs the second control signal T2U (the synchronous rectifier tube turns on the control signal, which corresponds to the turn-off of the synchronous rectifier tube when active, in this embodiment, the synchronous rectifier tube turns on the control signal to control the turn-on and turn-off of the synchronous rectifier tube, that is, when the synchronous rectifier tube turns on the control signal, the synchronous rectifier tube is turned off regardless of whether the synchronous rectifier tube prepares to turn on the signal or not.
The first trigger T1 and the third comparator COMP3 form a synchronous rectifier ready-to-conduct signal generating circuit, and output a synchronous rectifier ready-to-conduct signal, which corresponds to a signal for controlling the conduction of a synchronous rectifier by a conventional synchronous rectifier control circuit, and which may erroneously conduct the synchronous rectifier during a parasitic oscillation time. The utility model discloses synchronous rectification control circuit 100 provides synchronous rectifier tube switch-on control signal simultaneously, prepares switch-on signal to synchronous rectifier tube and restricts, can forbid switching on of synchronous rectifier tube in parasitic oscillation time.
In this embodiment, the second flip-flop T2 and the pulse generator 101 form a logic circuit, a first input terminal of the logic circuit is connected to an output terminal of the first comparator COMP1, a second input terminal of the logic circuit is connected to an output terminal of the first logic gate circuit 102, and the output terminal provides a synchronous rectifier conduction control signal.
The inverter 104 has an input terminal connected to the output terminal of the first comparator COMP1, and receives the first comparison signal CU1, and an output terminal connected to the switch control terminal of the switch S1, and controls the switch S1 to be turned on and off. In this embodiment, the switch S1 can be an NMOS (N-Metal-Oxide-Semiconductor) transistor, and the switching response speed is fast.
The first end of the capacitor C1 is connected to the positive output end of the current source I1, the second end is grounded, the switch S1 is connected in parallel to the two ends of the capacitor C1, the charging and discharging of the capacitor C1 are controlled by controlling the on and off of the switch S1, and the ramp voltage Vramp is provided at the first end of the capacitor C1.
A first terminal of the capacitor C1 is connected to an inverting input terminal of the fourth comparator COMP4, a non-inverting input terminal of the fourth comparator COMP4 is connected to the reference value configuration circuit 105, receives the fourth reference signal Vth _ conf, and an output terminal of the fourth comparator COMP4 provides the fourth comparison signal CU 4.
The external reference value configuration circuit 105 may include a variable resistor, which is connected in series with the resistor Rcf between a voltage source and ground, and the intermediate node of the variable resistor and the resistor Rcf provides the fourth reference signal Vth _ conf, which may adjust the level of the fourth reference signal Vth _ conf, may change the active time node of the fourth comparison signal CU4 in comparison with the ramp voltage Vramp, and may change the delay time of the delay disable circuit (the output signal is disabled after the delay time is 0) formed by the switch S1, the capacitor C1, the current source I1, the inverter 104, and the fourth comparator COMP 4.
The output terminals of the fourth comparator COMP4 and the second comparator COMP2 are connected to the first input terminal and the second input terminal of the first logic gate circuit 102 (first and logic gate circuit), respectively, the output terminal of the first logic gate circuit 102 is connected to the reset terminal R of the second flip-flop T2, and the second reset signal T2R (i.e., synchronous rectifier conduction enable detection signal) is provided. In this embodiment, the first logic gate 102 is an and gate, when the fourth comparison signal CU4 and the second comparison signal CU2 are both 1, the second reset signal T2R is asserted, and the second control signal T2U provided at the output terminal of the second flip-flop T2 is at a high level 1. Herein, a high level may be represented as 1 (active) and a low level may be represented as 0 (inactive).
The output end Q of the first flip-flop T1 is connected to a first input end of a second logic Gate circuit 103 (a second and logic Gate circuit), the output end Q of the second flip-flop T2 is connected to a second input end of the second logic Gate circuit 103 after being inverted (the inverted input end, the inverted input signal performs and logic with the input signal of the first input end), the output end of the second logic Gate circuit 103 is connected to the Gate of the synchronous rectifier SR to provide a synchronous rectifier Gate control signal SR Gate, in this embodiment, the second logic Gate circuit 103 is an and Gate, when the first control signal T1U is 1 and the second control signal T2U is 0, the synchronous rectifier Gate control signal SR Gate is 1, and the synchronous rectifier SR is turned on.
Fig. 4 shows a timing diagram of the operation of the pulse generator according to an embodiment of the present invention.
As shown in fig. 4, the pulse generator 101 of the embodiment of the present invention outputs a narrow pulse at the rising edge of its input signal, wherein the width of the narrow pulse is smaller than the delay time.
Fig. 5 shows a timing diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
As shown in fig. 5, t1 to t3 are the first time during which the body diode of the synchronous rectifier is normally turned on, and Vds is reduced from Vth1 to Vth 2; t 8-t 11 are the second time, in which the body diode of the synchronous rectifier is conducted by parasitic oscillation, Vds is decreased from Vth1 to Vth 2; the time t1 to t4 is the same as the time t8 to t10, which is the delay time.
Vds is less than Vth3 during time T2-T6 and time T9-T13, the T1R signal is inactive as 0, and the T1R signal is active as 1 during other times; in the time from t1 to t7 and the time from t8 to t13, Vds is less than Vth1, CU1 signal is active as 1. The first flip-flop T1 may be a reset master flip-flop, and when the T1R signal is inactive and the CU1 is active, the first control signal T1U at the output terminal is active as 1, that is, the first control signal T1U is active as 1 during the time T2 to T6 and the time T9 to T13, so as to control the conduction of the synchronous rectifier.
At time T1, the CU1 signal rises to 1, the pulse generator 101 outputs a narrow pulse, the output terminal of the second flip-flop T2 is set to 1, and the second control signal T2U is 1; the capacitor C1 starts to charge, and by the time point t4, the capacitor C1 charges to make the ramp voltage Vramp provided at the first end reach the level value of the fourth reference signal Vth _ conf, and the CU4 signal changes from 1 to 0; vds is reduced to Vth2 at a time T3, a CU2 signal is changed to 1 at a time T3, 1 is obtained from the time T3 to T5, a T3 signal is obtained before the time T4, so that the first input end and the second input end of the first logic gate circuit are simultaneously 1 at the time T3 to T4, a T2R signal is 1 at the time T3 to T4, the output end of the second flip-flop T2 can be reset to 0, that is, in the time period from T3 to T4, the second control signal T2U is reset to 0, the state is maintained until the time point T8, the CU1 signal generates a rising edge, the T2S signal is asserted, the second control signal T2U is reset to 1 again, the second control signal T2U is inverted and then connected to the two input terminals of the second logic gate circuit with the first control signal T1U, the two input terminals of the second logic gate circuit are simultaneously asserted in the time period from T3 to T6, and the output is 1 effective grid control signal SR Gate of the synchronous rectifier, controlling the synchronous rectifier to be conducted from t3 to t 6.
At time t7, the CU1 signal becomes 0, switch S1 is turned on, the first terminal of capacitor C1 is grounded through turned-on switch S1, ramp voltage Vramp becomes 0, and the CU4 signal becomes 1.
At time T8, Vds is in a parasitic oscillation state, Vds is lowered to Vth1, CU1 is changed to 1, the pulse generator outputs a narrow pulse, switch S1 is turned off, capacitor C1 starts to charge, Vramp voltage starts to rise, meanwhile T2S signal is temporarily set to 1, and second control signal T2U at the output end of second flip-flop T2 is set to 1.
After a delay time, at time T, Vramp rises to the level of the fourth reference signal Vth _ conf, CU changes to 0, which is a parasitic oscillation time, Vds is reduced to Vth from Vth slowly, i.e. at time T, Vds is not reduced to Vth yet, CU signal is 0, to time T, Vds is reduced to Vth, CU is 1, to time T, Vds is raised to Vth, CU changes to 0, which is 1 in time T to T of CU signal, CU is 1 in time T to T, CU and CU are not simultaneously 1, T2 signal is 0 in time T to T, second control signal T2 is not reset to 0 in time T to T and is maintained to 1, further, the inverted signal of second control signal T2 is 0 in time T to T and is not simultaneously 1 in time T to T, and the Gate control signal SR is not simultaneously 1 in time T to T, and is not maintained to be in off state with the first control signal T1 in time T to T, the misconduction of the synchronous rectifier tube in the parasitic oscillation time is avoided.
The synchronous rectification control circuit of the embodiment of the utility model provides a first control signal T1U, which corresponds to the conduction time of a conventional synchronous rectification tube when the first control signal T1U is effective; providing a second control signal T2U, and correspondingly controlling the synchronous rectifier tube to be turned off when the second control signal T2U is effective; the inverted signals of the first control signal T1U and the second control signal T2U are connected to two input ends of the and Gate, and when the first control signal T1U is active and the second control signal T2U is inactive, the Gate control signal SR Gate of the synchronous rectifier tube with high level is output to turn on the synchronous rectifier tube; a delay time is set that begins with Vds dropping to Vth1 and Vramp rising to the fourth reference signal Vth _ conf level. When the delay starts, the second control signal T2U is initialized to 1 (active), if Vds is reduced to Vth2 within the delay time, the body diode of the synchronous rectifier is judged to be normally conductive, and the first control signal T1U is reset to 0 (inactive) at the time when Vds is reduced to Vth2, and the synchronous rectifier is turned on; if Vds is not reduced to Vth2 within the delay time, the body diode of the synchronous rectifier is judged to be parasitic oscillation conduction, the second control signal T2U is initialized to 1 at the beginning of the delay time, the second control signal T2U is not reset and is maintained to 1 before the end of the delay time, and the delay starting time is between the reduction of Vds to Vth3, namely before the effective time of the first control signal T1U in the parasitic oscillation time, the false conduction of the synchronous rectifier within the parasitic oscillation time can be avoided.
In the time delay, when the fourth comparison signal CU4 is 1 and Vds is less than Vth2, the second comparison signal CU2 is 1, and the fourth comparison signal CU4 and the second comparison signal CU2 are and-connected through the first logic gate circuit 102 to obtain the second reset signal T2R, where Vds is decreased to Vth2 in the time delay, the second reset signal T2R is asserted, the second control signal T2U is reset to 0, Vds is decreased to Vth2 after the time delay, the second reset signal T2R is continuously deasserted to 0, the second control signal T2U is maintained to 1 for initialization, and the provision of the second control signal T2U is implemented. The second control signal is firstly set to be 1 in the delay time, then the detection of the conduction reason of the body diode tube of the synchronous rectifier tube is completed in the delay time, and whether the second control signal is reset to be 0 is judged according to the detection result.
The synchronous rectification control circuit of the utility model detects the time of the synchronous rectification tube from the first reference signal to the second reference signal, sets the delay time as the threshold time of the synchronous rectification tube from the first reference signal to the second reference signal, when the drain-source voltage of the synchronous rectifier tube is reduced to the first reference signal, a narrow pulse is provided to initialize the second control signal to 1, when the drain-source voltage of the synchronous rectifier tube is less than the second reference signal, the second comparison signal is 1, during the delay time, the fourth comparison signal is 1, and the second comparison signal and the fourth comparison signal are performed with logic to provide a second reset signal, when the valid time of the second comparison signal and the valid time of the fourth comparison signal intersect, the body diode corresponding to the synchronous rectifier tube is normally conducted to enable the second control signal to be invalid, and the synchronous rectifier tube can be conducted within the valid time of the first control signal within the invalid time of the second control signal; when the effective time of the second comparison signal and the effective time of the fourth comparison signal are not intersected, the body diode corresponding to the synchronous rectifier tube is conducted due to parasitic oscillation, so that the second control signal is kept effective, the synchronous rectifier tube is kept turned off within the time when the first control signal is effective and the second control signal is effective, and the error conduction of the synchronous rectifier tube within the parasitic oscillation time is avoided.
Those skilled in the art should understand that the logic controls of "high" and "low", "set" and "reset", "and" or "," in-phase "and" reverse "in the above logic controls can be interchanged or changed, and the subsequent logic controls can be adjusted to achieve the same functions or purposes as those of the above embodiments.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (7)
1. The utility model provides a synchronous rectification control circuit, includes synchronous rectifier tube drain-source voltage incoming end and synchronous rectifier tube grid control signal output part, its characterized in that includes:
the synchronous rectifier tube ready-conducting signal generating circuit comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a third reference signal input end and a synchronous rectifier tube ready-conducting signal output end;
the first comparator comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a first reference signal input end and a first comparison signal output end;
the logic circuit comprises a first input end, a second input end and a synchronous rectifier tube conduction control signal output end, wherein the first input end and the second input end are connected with the first comparison signal output end;
the second comparator comprises an input end connected with the drain-source voltage access end of the synchronous rectifier tube, a second reference signal input end and a second comparison signal output end;
a delay nulling circuit comprising an input connected to the first comparison signal and an output;
the first logic gate circuit comprises a first input end connected with the output end of the delay ineffectiveness circuit, a second input end connected with the second comparison signal output end and a synchronous rectifier tube conduction permission detection signal output end, and the synchronous rectifier tube conduction permission detection signal output end is connected with the second input end of the logic circuit;
and the second logic gate circuit comprises a first input end connected with the preparatory conduction signal output end of the synchronous rectifier tube, a second input end connected with the conduction control signal output end of the synchronous rectifier tube and an output end connected to the grid control signal output end of the synchronous rectifier tube.
2. The synchronous rectification control circuit of claim 1, wherein the logic circuit comprises:
the pulse generator comprises an input end and an output end which are connected with the first comparison signal output end;
the second trigger, the position end of second trigger with impulse generator's output is connected, the end that resets of second trigger with synchronous rectifier switches on and allows the detection signal output to connect, the output of second trigger is connected to the second input of second logic gate circuit, the output of second trigger is synchronous rectifier switches on the control signal output.
3. The synchronous rectification control circuit of claim 1, wherein the synchronous rectification tube preparation conducting signal generating circuit comprises:
the third comparator comprises a non-inverting input end connected with the drain-source voltage access end of the synchronous rectifier tube, an inverting input end connected with the third reference signal input end and a third comparison signal output end;
the first trigger is a reset leading trigger, the reset end of the first trigger is connected with the third comparison signal output end, the position end of the first trigger is connected with the first comparison signal output end, and the output end of the first trigger is the prepared conduction signal output end of the synchronous rectifier tube.
4. The synchronous rectification control circuit of claim 1, wherein the delay nulling circuit comprises:
a capacitor including a first terminal connected to the positive output terminal of the current source and a second terminal connected to ground;
a switch connected in parallel with both ends of the capacitor, the switch including a switch control terminal connected with the first comparison signal output terminal;
and the fourth comparator comprises an input end connected with the first end of the capacitor, a fourth reference signal input end and an output end, and the output end of the fourth comparator is the output end of the delay ineffectiveness circuit.
5. The synchronous rectification control circuit of claim 4,
the delay ineffectiveness circuit further comprises an inverter, and the inverter is connected in series between the first comparison signal output end and the switch control end;
the switch is an NMOS tube, and the grid electrode of the NMOS tube is the switch control end.
6. The synchronous rectification control circuit of claim 4,
and the fourth reference signal input end is connected with a fourth reference signal output end of an external fourth reference signal configuration circuit.
7. A voltage converter, comprising:
the transformer comprises a primary side circuit and a secondary side circuit, wherein the secondary side circuit comprises a synchronous rectifier tube;
the synchronous rectification control circuit of any one of claims 1 to 6, wherein the synchronous rectifier gate control signal output is connected to the gate of the synchronous rectifier.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112134467A (en) * | 2020-09-27 | 2020-12-25 | 深圳市必易微电子股份有限公司 | Synchronous rectification control circuit and voltage converter |
| CN117155136A (en) * | 2023-10-27 | 2023-12-01 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification control circuit and method for inhibiting ringing false turn-on of rectifier tube |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112134467A (en) * | 2020-09-27 | 2020-12-25 | 深圳市必易微电子股份有限公司 | Synchronous rectification control circuit and voltage converter |
| CN117155136A (en) * | 2023-10-27 | 2023-12-01 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification control circuit and method for inhibiting ringing false turn-on of rectifier tube |
| CN117155136B (en) * | 2023-10-27 | 2024-01-26 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification control circuit and method for inhibiting ringing false turn-on of rectifier tube |
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