CN213071106U - Semiconductor packaging structure - Google Patents

Abstract

The embodiment of the application relates to a semiconductor packaging structure. A semiconductor package structure according to an embodiment includes: a carrier, a first semiconductor die, an underfill, and a coating. The first semiconductor die is located on the carrier and has a first surface facing the carrier and a second surface opposite the first surface. The underfill is positioned between the carrier and the first surface. The coating is on the second surface and is configured to de-wet the underfill. The semiconductor packaging structure provided by the embodiment of the application can ensure that no undesirable underfill exists on the back surface of the flip chip, so that the product quality of the semiconductor packaging structure is improved.

Description

Semiconductor packaging structure

Technical Field

The embodiment of the application relates to the field of semiconductors, in particular to a semiconductor packaging structure.

Background

Existing semiconductor package structures typically include a multi-layer chip stack structure. In a structure having a multi-layered chip stack, a main chip is generally bonded to a surface of a substrate (e.g., a PCB board) through a flip-chip process, and a plurality of additional chips are sequentially stacked on a back surface of the main chip. However, during bonding of the main chip to the substrate, it is often necessary to use an underfill (e.g., a thermosetting epoxy) to protect the conductive bumps of the main chip from external pressure.

However, if the thickness of the main chip is too thin (e.g., less than about 100 μm), the underfill tends to creep (cross) to the back side of the main chip during application of the underfill, resulting in contamination and topographical changes to the back side of the main chip. More particularly, to avoid the underfill from contaminating bond pads on the PCB adjacent to the underfill, it is often necessary to limit the area where the underfill is applied to be relatively close to the main chip, resulting in the underfill being more prone to creep to the back side of the main chip. For example, when the distance of the bonding pad from the side wall of the main chip in the lateral direction is less than 500 μm, a case where the underfill easily creeps to the back surface of the main chip is particularly easily generated.

If the underfill creeps into the backside of the primary chip, causing the backside topography of the primary chip to change, a series of problems can occur during subsequent chip stacking. In particular, high pressure is applied during the chip stacking operation, and since the surface of the back surface of the main chip is not flat, the pressure cannot be uniformly applied to the back surface of the main chip, and stress concentration occurs at one or more positions where the topography of the back surface of the main chip is more prominent, thereby causing the stacked chips to crack. Therefore, the creep of the underfill agent to the back surface of the main chip is not favorable for the manufacture of the multi-stacked semiconductor package structure, and also degrades the product quality of the multi-stacked semiconductor package structure.

Therefore, there are many technical problems to be solved in the industry regarding how to avoid the underfill from creeping into the back side of the main chip.

SUMMERY OF THE UTILITY MODEL

An object of the embodiments of the present application is to provide a semiconductor package structure, which can ensure that there is no undesired underfill on the back side of a flip chip, thereby improving the product quality of the semiconductor package structure.

According to an embodiment of the present application, a semiconductor package structure is provided, which includes: a carrier, a first semiconductor die, an underfill, and a coating. A first semiconductor die is on the carrier and has a first surface facing the carrier and a second surface opposite the first surface. An underfill is positioned between the carrier and the first surface. A coating is on the second surface and is configured to de-wet the underfill.

In some embodiments of the present application, the semiconductor package structure further includes a second semiconductor die and an adhesive layer. A second semiconductor die is located over the second surface of the first semiconductor die. An adhesive layer is located between the first semiconductor die and the second semiconductor die.

In some embodiments of the present application, the adhesive layer is laminated on the coating.

In some embodiments of the present application, the first semiconductor die is flip chip bonded to the carrier.

In some embodiments of the present application, the underfill is absent from the second surface of the first semiconductor die.

In some embodiments of the present application, the first semiconductor die has a thickness equal to or less than about 100 μm.

In some embodiments of the present application, further comprising bond pads on the carrier, a lateral distance between the bond pads and sidewalls of the first semiconductor die being less than about 500 μm.

In some embodiments of the present application, it further comprises bond wires connecting the bond pads with a second semiconductor die located over the second surface of the first semiconductor die.

In some embodiments of the present application, a width of the coating is narrower than a width of the second semiconductor die.

In some embodiments of the present application, further comprising a spacer on the carrier, the spacer supporting the second semiconductor die from an edge of the second semiconductor die, a top surface of the spacer being substantially coplanar with a top surface of the coating.

In some embodiments of the present application, a width of the coating is substantially the same as a width of the second semiconductor die.

In some embodiments of the present application, it further comprises an encapsulant encapsulating the underfill, the first semiconductor die, and the coating.

In some embodiments of the present application, sidewalls of the coating are substantially aligned with sidewalls of the first semiconductor die.

In some embodiments of the present application, the coating has a thickness of less than about 5 μm.

In some embodiments of the present application, the coating comprises silicone, polyurethane, or a combination of silicone and polyurethane.

The semiconductor packaging structure provided by the embodiment of the application can ensure that no undesirable underfill exists on the back surface of the flip chip, so that the semiconductor packaging structure has good product quality.

Drawings

The drawings necessary for describing the embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

FIG. 1 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to an embodiment of the present application

FIG. 2 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to another embodiment of the present application

FIG. 3 is a schematic longitudinal cross-sectional view of a semiconductor package structure according to yet another embodiment of the present application

FIGS. 4A, 4B', 4C, 4D, 4E, and 4F are schematic flow diagrams of a method for fabricating a semiconductor package according to an embodiment of the present application, which can be used to fabricate the semiconductor package of FIG. 1

FIGS. 5A, 5B, 5C', 5D, 5E, 5F, 5G, and 5H are schematic flow diagrams of a method for fabricating a semiconductor package according to another embodiment of the present application, which can be used to fabricate the semiconductor package of FIG. 1

Fig. 6 is a schematic top view of a plurality of semiconductor packages mounted on a carrier according to an embodiment of the present application

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

Fig. 1 is a schematic longitudinal cross-sectional view of a semiconductor package structure 100 according to an embodiment of the present application.

As shown in fig. 1, a semiconductor package structure 100 according to an embodiment of the present application may include: a carrier 101, a first semiconductor die 103, an underfill 105, a coating 107, and an encapsulant 109.

The carrier 101 may be a substrate that carries a first semiconductor die 103. The carrier 101 has a top surface 101a and a bottom surface 101b opposite the top surface 101 a. The top surface 101a and the bottom surface 101b may be substantially flat surfaces. In some embodiments, the top surface 101a and/or the bottom surface 101b may include recessed structures disposed as desired. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the top surface 101a for electrical connection with the first semiconductor die 103 and/or other electronic elements carried by the carrier 101. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the bottom surface 101b for electrical connection with other electronic components located outside the semiconductor package structure 100. In some embodiments, the carrier 101 may comprise a plurality of layers, which may include dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. In certain embodiments, the carrier 101 may be composed of any suitable type of substrate material.

A first semiconductor die 103 is located on the carrier 101. The first semiconductor die 103 has a first surface 103a facing the carrier 101, a second surface 103b opposite the first surface 103a, and a sidewall 103c connecting the first surface 103a and the second surface 103 b. The first surface 103a and the second surface 103b may be substantially flat surfaces. The sidewall 103c may be substantially perpendicular to the first surface 103a and the second surface 103 b. The first semiconductor die 103 further includes a conductor bump 103d disposed on the first surface 103 a. The material of the conductor bump 103d may be any suitable material in the art with good support and electrical conductivity, such as, but not limited to, copper, lead-tin alloy, or a combination thereof. The first semiconductor die 103 may be a flip chip configured to be electrically connected to the carrier 101 through the conductor bumps 103d by a flip chip bonding process. The first semiconductor die 103 may have a width W1 along the X-direction and a thickness H1 along the Y-direction. The thickness H1 may be equal to or less than about 100 μm, such as, but not limited to, about 95 μm, about 90 μm, about 80 μm, about 75 μm, about 50 μm. In some embodiments of the present application, the first semiconductor die 103 may be any type of die or chip.

The underfill 105 is located between the carrier 101 and the first surface 103a of the first semiconductor die 103 to encapsulate each of the conductive bumps 103d to provide sufficient supporting force for the conductive bumps 103d to prevent the possibility of deformation of the conductive bumps 103d in the presence of a large pressure. For example, when the encapsulation material is injection molded to form the encapsulation body, the flow of the encapsulation material may impact the conductor bump 103d to some extent. As another example, if one or more semiconductor dies or other types of electronic elements need to be stacked on the first semiconductor die 103, the conductor bumps 103d need to withstand greater pressure. Therefore, disposing underfill 105 to cover each conductive bump 103d helps the conductive bump 103d bear a greater pressure and prevents deformation of the conductive bump 103 d. The underfill 105 as shown in fig. 1 also coats a portion of the sidewalls 103c of the first semiconductor die 103, but the underfill 105 does not contact the second surface 103b of the first semiconductor die 103 at all. In some embodiments of the present application, the underfill 105 may only be located between the carrier 101 and the first surface 103a of the first semiconductor die 103, which may not coat any portion of the sidewalls 103c of the first semiconductor die 103. The material of the underfill 105 may be any suitable type of underfill material known in the art, such as, but not limited to, a thermosetting epoxy resin (containing a silica filler).

The coating 107 is located on the second surface 103b of the first semiconductor die 103. The coating 107 has a top surface 107a, a bottom surface 107b opposite the top surface 107a, and a sidewall 107c connecting the first surface 107a and the second surface 107 b. The top surface 107a and the bottom surface 107b may be flat surfaces. The sidewalls 107c may be substantially perpendicular to the top surface 107a and the bottom surface 107 b. The coating 107 may have a width W2 in the X-direction and a thickness H2 in the Y-direction. The width W2 of the coating 107 is substantially the same as the width W2 of the second semiconductor die 203, so the sidewalls 107c of the coating 107 can be substantially aligned with, i.e., substantially coplanar with, the sidewalls 103c of the first semiconductor die 103. The thickness H2 of coating layer 107 can be equal to or less than about 10 μm, such as, but not limited to, about 10 μm, about 6 μm, about 5 μm, about 4 μm, about 3 μm, about 2 μm. The coating 107 may be configured to de-wet the underfill 105. By "de-wetting" is meant that the coating layer 107 has a material property that repels the underfill 105, such that during application of the underfill 105 between the carrier 101 and the first surface 103a of the first semiconductor die 103, the property of the coating layer 107 to repel the underfill 105 may cause the interface of the underfill 105 and the coating layer 107 to produce a contact angle of greater than 90 degrees such that the underfill 105 does not remain on the second surface 103b of the first semiconductor die 103, as the coating layer 107 is disposed on the second surface 103b of the first semiconductor die 103. This material property of the coating layer 107 that repels the underfill 105 is defined in this disclosure as the "dewet" property to the underfill 105. The material of the coating layer 107 may be selected from any material that is capable of dewetting the underfill 105. The material of coating 107 may include, for example, but is not limited to, silicon and urethane resins, silicone resins, urethane resins, combinations of silicone resins and urethane resins, acrylic urethane resins, or acrylic silicone resins.

The encapsulant 109 encapsulates the carrier 101, the first semiconductor die 103, the underfill 105, and the coating 107. The material of the encapsulant 109 may be an encapsulant material commonly used in the art.

The embodiment of the present application provides the coating layer 107 with the material property of repelling the underfill 105 on the second surface 103b of the first semiconductor die 103, so that the underfill 105 does not exist on the second surface 103b of the first semiconductor die 103, thereby ensuring a flat and clean surface topography of the second surface 103b of the first semiconductor die 103, and avoiding poor product and subsequent inconvenient stacking due to the creep of the underfill 105 to the second surface 103b of the first semiconductor die 103 during the disposing of the underfill 105 on the carrier 101. Therefore, the embodiment of the application can avoid the unevenness of the second surface 103b of the first semiconductor die 103 caused by the underfill 105, thereby providing the semiconductor package structure 100 with good quality.

Fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor package structure 200 according to another embodiment of the present application.

In contrast to the semiconductor package structure 100 shown in fig. 1, the semiconductor package structure 200 shown in fig. 2 includes, in addition to the carrier 101, the first semiconductor die 103, the underfill 105, the coating 107, and the encapsulant 109 shown in fig. 1, the semiconductor package structure 200 shown in fig. 2 further includes a second semiconductor die 203, a third semiconductor die 205, a fourth semiconductor die 207, an adhesive layer 211 between the first semiconductor die 103 and the second semiconductor die 203, an adhesive layer 211 between the second semiconductor die 203 and the third semiconductor die 205, and an adhesive layer 211 between the third semiconductor die 205 and the fourth semiconductor die 207. The semiconductor package 200 may be a Hybrid Dynamic Random Access Memory (Hybrid Dynamic Random Access Memory) type package.

The second semiconductor die 203 is located above the second surface 103b of the first semiconductor die 103. The second semiconductor die 203 has a first surface 203a, a second surface 203b opposite the first surface 203a, and a sidewall 203c connecting the first surface 203a and the second surface 203 b. The first surface 203a and the second surface 203b may be substantially flat surfaces. The sidewall 203c may be substantially perpendicular to the first surface 203a and the second surface 203 b. The second semiconductor die 203 may have a width W3 along the X-direction and a thickness along the Y-direction. The width W3 of the second semiconductor die 203 may be substantially the same as the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. The thickness of second semiconductor die 203 may be greater than thickness H1 of first semiconductor die 103. In certain embodiments, the thickness of the second semiconductor die 203 can be less than or substantially equal to the thickness H1 of the first semiconductor die 103. The second semiconductor die 203 can also include bond pads 203d disposed proximate the second surface 203 b. The material of the bonding pad 203d may be any suitable material having conductive ability in the art. The second semiconductor die 203 can be any type of chip that can be secured to the second surface 103b of the first semiconductor die 103 by an adhesive layer 211. The adhesive layer 211 can be previously disposed on the first surface 203a of the second semiconductor die 203 and then the second semiconductor die 203 disposed with the adhesive layer 211 can be secured to the coating 107 on the second surface 103b of the first semiconductor die 103. Alternatively, the adhesive layer 211 can be pre-coated with the coating layer 107 on the second surface 103b of the first semiconductor die 103, and then the second semiconductor die 203 can be secured to the adhesive layer 211. Second semiconductor die 203 may be electrically connected to bond pads 101d located on carrier 101 proximate top surface 101 through wire bonds 213 by a wire bonding process, thereby achieving an electrical connection configuration between second semiconductor die 203 and bond pads 101 d. The material of the bond wire 213 is a bond wire material common in the art, such as, but not limited to, gold wire. The material of the bonding pad 101d may be any suitable material having conductive ability in the art. The lateral distance D between the bond pad 101D and the sidewall 103c of the first semiconductor die 103 is less than about 500 μm.

The material of the adhesive layer 211 may be any suitable adhesive material in the art. The adhesive layer 211 may be a die attach film (die attach film). The adhesive layer 211 is laminated to the coating layer 107. The adhesive layer 211 may have a thickness of about 5 microns to about 30 microns, such as, but not limited to, about 5 microns, about 10 microns, about 20 microns, about 25 microns, about 30 microns. There is good adhesion between the adhesive layer 211 and the coating layer 107, and between the adhesive layer 211 and the second semiconductor die 203, so that the stacked second semiconductor die 203 and first semiconductor die 103 have good stability.

The third semiconductor die 205 is located above the second surface 203b of the second semiconductor die 203. The third semiconductor die 205 has a first surface 205a, a second surface 205b opposite the first surface 205a, and sidewalls 205c connecting the first surface 205a and the second surface 205 b. The first surface 205a and the second surface 205b may be substantially flat surfaces. The sidewall 205c may be substantially perpendicular to the first surface 205a and the second surface 205 b. The third semiconductor die 205 may have a width in the X-direction and a thickness in the Y-direction. The width of the third semiconductor die 205 can be substantially the same as the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. In certain embodiments of the present application, the width of the third semiconductor die 205 can be different from the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. The thickness of the third semiconductor die 205 can be greater than the thickness H1 of the first semiconductor die 103. In certain embodiments, the thickness of the third semiconductor die 205 can be less than or substantially equal to the thickness H1 of the first semiconductor die 103. The third semiconductor die 205 can also include bond pads 205d disposed proximate the second surface 205 b. The material of the bonding pad 205d may be any suitable material having conductive capabilities in the art. The third semiconductor die 205 can be any type of chip that can be secured to the second surface 203b of the second semiconductor die 203 by an adhesive layer 211. The adhesive layer 211 may be provided on the first surface 205a of the third semiconductor die 205 in advance and then the third semiconductor die 205 provided with the adhesive layer 211 is fixed to the second surface 203b of the second semiconductor die 203, or the adhesive layer 211 may be coated on the second surface 203b of the second semiconductor die 203 in advance and then the third semiconductor die 205 is fixed to the adhesive layer 211. The adhesive layer 211 has good adhesion to the third semiconductor die 205, and thus the stacked second and third semiconductor dies 203, 205 have good stability. The third semiconductor die 205 can be electrically connected to the bond pad 203d via a wire bond 213 by a wire bonding process, thereby achieving electrical connection between the third semiconductor die 205 and the bond pad 203d of the second semiconductor die 203.

The fourth semiconductor die 207 is located above the second surface 205b of the third semiconductor die 205. The fourth semiconductor die 207 has a first surface 207a, a second surface 207b opposite the first surface 207a, and sidewalls 207c connecting the first surface 207a and the second surface 207 b. The first surface 207a and the second surface 207b may be substantially flat surfaces. The sidewall 207c may be substantially perpendicular to the first surface 207a and the second surface 207 b. The fourth semiconductor die 207 may have a width in the X-direction and a thickness in the Y-direction. The width of the fourth semiconductor die 207 can be substantially the same as the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. In certain embodiments of the present application, the width of the fourth semiconductor die 207 can be different from the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. The thickness of the fourth semiconductor die 207 can be greater than the thickness H1 of the first semiconductor die 103. In certain embodiments, the thickness of the fourth semiconductor die 207 can be less than or substantially equal to the thickness H1 of the first semiconductor die 103. The fourth semiconductor die 207 can also include bond pads 207d disposed proximate the second surface 207 b. The material of the bonding pad 207d may be any suitable material having conductive capability in the art. The fourth semiconductor die 207 can be any type of chip that can be secured to the second surface 205b of the third semiconductor die 205 by an adhesive layer 211. The adhesive layer 211 can be previously disposed on the first surface 207a of the fourth semiconductor die 207 and then the fourth semiconductor die 207 with the adhesive layer 211 disposed thereon can be secured to the second surface 205b of the third semiconductor die 205. Alternatively, the adhesive layer 211 can be pre-coated on the second surface 205b of the third semiconductor die 205, and then the fourth semiconductor die 207 can be secured to the adhesive layer 211. The adhesive layer 211 has good adhesion to the fourth semiconductor die 207, and thus the stacked fourth and third semiconductor dies 207, 205 have good stability. The fourth semiconductor die 207 can be electrically connected to the bond pads 205d via bond wires 213 by a wire bonding process, thereby achieving electrical connection between the fourth semiconductor die 207 and the bond pads 205d of the third semiconductor die 205.

In addition to carrier 101, first semiconductor die 103, underfill 105, and coating 107, encapsulant 109 encapsulates second semiconductor die 203, third semiconductor die 205, fourth semiconductor die 207, and bonding wires 213.

By providing the coating layer 107 with the material property of repelling the underfill 105 on the second surface 103b of the first semiconductor die 103, the embodiment of the present application can prevent the underfill 105 from creeping to the second surface 103b of the first semiconductor die 103, so that the second surface 103b of the first semiconductor die 103 can be kept clean and flat, thereby providing great convenience for stacking other subsequent dies or chips, and avoiding stress concentration and even cracking which easily occur when the chips are stacked. Therefore, the semiconductor packaging structure with the multilayer stack provided by the embodiment of the application has good product quality.

Fig. 3 is a schematic longitudinal cross-sectional view of a semiconductor package structure 300 according to yet another embodiment of the present application.

The semiconductor package 300 shown in fig. 3 differs from the semiconductor package 200 shown in fig. 2 in that: the width W3 of the second semiconductor die 203 is greater than the width W1 of the first semiconductor die 103 and the width W2 of the coating 107, i.e., the width W2 of the coating 107 is narrower than the width W3 of the second semiconductor die 203. The second semiconductor die 203 may also be supported by spacers 301 located on the carrier 101. The spacers 301 may be a non-conductive material with suitable holding force. The spacers 301 support the second semiconductor die 203 from the edge of the second semiconductor die 203, i.e., the sidewalls 203c of the second semiconductor die 203. The top surface 301a of the spacer 301 is substantially coplanar with the top surface 107a of the coating 107. The semiconductor package structure 300 may be a NAND (Not AND) type flash memory package. Compared to the semiconductor package structure 200 of fig. 2, the semiconductor package structure 300 shown in fig. 3 requires a space for disposing the spacer 301, so that the distance between the sidewall of the first semiconductor die 103 and the bonding pad 101d is larger, which is beneficial for the process of applying the underfill 105, and the underfill 105 is less likely to contaminate the bonding pad 101d or the second surface 103b of the first semiconductor die 103.

Fig. 4A, 4B', 4C, 4D, 4E, and 4F are schematic flow diagrams of a process for fabricating a semiconductor package structure according to an embodiment of the present application, which can fabricate the semiconductor package structure 100 shown in fig. 1.

As shown in fig. 4A, a wafer prepared in advance may be cut into a plurality of first semiconductor dies 103. Each first semiconductor die 103 has a first surface 103a, a second surface 103b opposite the first surface 103a, and sidewalls 103c connecting the first surface 103a and the second surface 103 b. The first surface 103a and the second surface 103b may be substantially flat surfaces. The sidewall 103c may be substantially perpendicular to the first surface 103a and the second surface 103 b. The first semiconductor die 103 further includes a conductor bump 103d disposed on the first surface 103 a. The material of the conductor bump 103d may be any suitable material in the art with good support and electrical conductivity, such as, but not limited to, copper, lead-tin alloy, or a combination thereof. The first semiconductor die 103 may have a width W1 along the X-direction and a thickness H1 along the Y-direction. The thickness H1 may be equal to or less than about 100 μm, such as, but not limited to, about 95 μm, about 90 μm, about 80 μm, about 75 μm, about 50 μm. The first semiconductor die 103 may be a flip chip. In some embodiments of the present application, the first semiconductor die 103 may be any type of die or chip.

A carrier 101 is provided. The carrier 101 may be a substrate having a top surface 101a and a bottom surface 101b opposite the top surface 101 a. The top surface 101a and the bottom surface 101b may be substantially flat surfaces. In some embodiments, the top surface 101a and/or the bottom surface 101b may include recessed structures disposed as desired. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the top surface 101a for electrical connection with the first semiconductor die 103, and/or other electronic components carried by the carrier 101. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the bottom surface 101b for electrical connection with other electronic components located outside the semiconductor package structure 100. In some embodiments, the carrier 101 may comprise a plurality of layers, which may include dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. In certain embodiments, the carrier 101 may be composed of any suitable type of substrate material.

Next, the first semiconductor die 103 is connected to the top surface 101a of the carrier 101 via the conductor bumps 103d thereon by a flip chip bonding process.

As shown in fig. 4B, a rolling process can be performed to apply the coating layer 107 to the second surface 103B of the first semiconductor die 103.

Alternatively, as shown in fig. 4B', the coating 107 can be applied to the second surface 103B of the first semiconductor die 103 using a stamping process.

The coating 107 has a top surface 107a, a bottom surface 107b opposite the top surface 107a, and a sidewall 107c connecting the first surface 107a and the second surface 107 b. The top surface 107a and the bottom surface 107b may be substantially flat surfaces. The sidewalls 107c may be substantially perpendicular to the top surface 107a and the bottom surface 107 b. The coating 107 may have a width W2 in the X-direction and a thickness in the Y-direction. The width W2 of the coating 107 is substantially the same as the width W2 of the second semiconductor die 203, so the sidewalls 107a of the coating 107 can be substantially aligned with, i.e., substantially coplanar with, the sidewalls 103c of the first semiconductor die 103. The thickness of the coating 107 may be equal to or less than about 10 μm, such as, but not limited to, about 10 μm, about 6 μm, about 5 μm, about 4 μm, about 3 μm, about 2 μm. The coating 107 may be configured to de-wet the underfill 105, i.e., the coating 107 has material properties that repel the underfill 105. The material of the coating layer 107 may be selected from any material that is capable of dewetting the underfill 105. The material of coating 107 may include, for example, but is not limited to, silicon and urethane resins, silicone resins, urethane resins, combinations of silicone resins and urethane resins, acrylic urethane resins, or acrylic silicone resins.

As shown in fig. 4C, a baking (baking) process and a curing (curing) process are performed on the coating layer 107. The drying time, curing time, temperature, and other relevant parameters may be determined based on the material and thickness of the coating 107.

As shown in fig. 4D, the underfill 105 is applied between the top surface 101a of the carrier 101 and the first surface 103a of the first semiconductor die 103 to encapsulate each of the conductive bumps 103D, thereby providing sufficient support for the conductive bumps 103D to prevent the possibility of deformation of the conductive bumps 103D in the presence of a large pressure. For example, when the encapsulant is subsequently injected to form the encapsulation body, the flow of the encapsulant may impact the conductor bump 103d to some extent. As another example, if one or more semiconductor dies or other types of electronic elements need to be stacked on the first semiconductor die 103, the conductor bumps 103d need to withstand greater pressure. Therefore, disposing underfill 105 to cover each conductive bump 103d helps the conductive bump 103d bear a greater pressure and prevents deformation of the conductive bump 103 d. After applying the underfill 105, the step shown in fig. 4D further includes performing a curing process to cure the applied underfill 105. In some embodiments, the underfill 105 may also coat a portion of the sidewalls 103c of the first semiconductor die 103, but due to the "dewet" nature of the coating 107, the underfill 105 is not present on the second surface 103b of the first semiconductor die 103. The material of the underfill 105 may be any suitable type of underfill material commonly used in the art, such as, but not limited to, a thermosetting epoxy resin.

As shown in fig. 4E, an injection molding process is performed such that the encapsulant 109 encapsulates the carrier 101, the first semiconductor die 103, the underfill 105, and the coating 107. The material of the encapsulant 109 may be an encapsulant material commonly used in the art. The encapsulant 109 and carrier 101 may then be cut along the line a-a shown in fig. 4E, resulting in a plurality of semiconductor package structures 100 as shown in fig. 1.

As shown in fig. 4F, after the step of applying the underfill 105 shown in fig. 4D is completed and before the injection molding process shown in fig. 4E is performed, another semiconductor die 401 may be stacked on the second surface 103b of the first semiconductor die 103 to obtain a package with stacked semiconductor dies according to actual product requirements.

Specifically, another semiconductor die 401 may be disposed over the second surface 103b of the first semiconductor die 103. Another semiconductor die 401 has a first surface 401a, a second surface 401b opposite the first surface 401a, and sidewalls 401c connecting the first surface 401a and the second surface 401 b. The first surface 401a and the second surface 401b may be substantially flat surfaces. The sidewall 401c may be substantially perpendicular to the first surface 401a and the second surface 401 b. Another semiconductor die 401 may have a width in the X-direction and a thickness in the Y-direction. The width of the other semiconductor die 401 may be substantially the same as the width W1 of the first semiconductor die 103 and the width W2 of the coating 107. The thickness of the other semiconductor die 401 may be greater than the thickness H1 of the first semiconductor die 103. In certain embodiments, the thickness of the other semiconductor die 401 may be less than or substantially equal to the thickness H1 of the first semiconductor die 103. The other semiconductor die 401 may also include bond pads disposed proximate to the second surface of the other semiconductor die 401 b. The material of the bond pad can be any suitable material having conductive capabilities in the art. Another semiconductor die 401 may be any type of chip that may be secured to the second surface 103b of the first semiconductor die 103 by an adhesive layer 211. The adhesive layer 211 may be previously disposed on the first surface 401a of the other semiconductor die 401 and then the other semiconductor die 401 disposed with the adhesive layer 211 may be secured to the second surface 103b of the first semiconductor die 103. Alternatively, the adhesive layer 211 may be pre-coated on the second surface 103b of the first semiconductor die 103 and then the other semiconductor die 401 may be secured to the adhesive layer 211. Next, another semiconductor die 401 can be electrically connected to bonding pads disposed near the top surface 101 on the carrier 101 through a wire bonding process, so as to realize an electrical connection configuration between the another semiconductor die 401 and the carrier 101. The material of the bond wire is a bond wire material common in the art, such as, but not limited to, gold wire. The material of the bond pad can be any suitable material having conductive capabilities in the art.

In certain embodiments of the present application, additional one or more semiconductor dies can be sequentially stacked above the second surface 103b of the first semiconductor die 103 in the same manner as another semiconductor die 401. Then, the electrical connection between each die and the carrier 101 can be realized through a wire bonding process. Next, the injection molding process and the cutting process shown in fig. 4E are performed to obtain the semiconductor package structure 200 shown in fig. 2, for example.

In some embodiments of the present application, after the step shown in fig. 4D is completed, the spacer 301 shown in fig. 3 may be disposed on the surface of the carrier 101. Then, additional dies having a width in the X-direction greater than the width W1 of the first semiconductor die 103 can be stacked over the second surface 103b of the first semiconductor die 103 and the spacer 301 using the method as described in fig. 4F. Of course, other one or more semiconductor dies may be stacked sequentially over the additional dies in the same manner as the other semiconductor die 401, according to actual product needs. Then, the electrical connection between each die and the carrier 101 can be realized through a wire bonding process. Then, the injection molding process and the cutting process shown in fig. 4E are performed to obtain the semiconductor package 300 shown in fig. 3, for example.

By disposing the coating layer 107 having the material property of repelling the underfill 105 on the second surface 103b of the first semiconductor die 103, the embodiment of the present application can prevent the underfill 105 from creeping to the second surface 103b of the first semiconductor die 103, thereby ensuring the cleanness and flatness of the second surface 103b of the first semiconductor die 103, providing great convenience for subsequent stacking of other dies or chips, and avoiding stress concentration and even cracking which easily occur when chips are stacked. Therefore, the semiconductor packaging method provided by the embodiment of the application has the advantages of simple process, high production efficiency and the like.

Fig. 5A, 5B, 5C', 5D, 5E, 5F, 5G, and 5H are schematic flow diagrams of fabricating a semiconductor package structure according to an embodiment of the present application, which can fabricate the semiconductor package structure 100 shown in fig. 1. Fig. 5A, 5B, 5C', 5D, 5E, 5F, 5G, and 5H illustrate wafer-level processes.

As shown in fig. 5A, a wafer 501 having a first surface 501a and a second surface 105b opposite to the first surface 105A is provided. The first surface 501a and the second surface 105b may be substantially flat surfaces. The first surface 501a may be provided with a plurality of conductor bumps 103 d. The material of the conductor bump 103d may be any suitable material in the art with good support and electrical conductivity, such as, but not limited to, copper, lead-tin alloy, or a combination thereof.

The wafer 501 is disposed on a tape 503, wherein the conductive bump 103d is embedded in the tape 503. Adhesive film (tape)503 is any type of adhesive film commonly used in the art.

As shown in fig. 5B, a grinding process may be performed to grind the second surface 501B of the wafer 501 to reduce the thickness of the wafer 501.

As shown in fig. 5C, a spin coating (spin) process may be performed to apply the coating 107 to the second surface 501b of the wafer 501.

Alternatively, as shown in fig. 5C', the coating 107 may be applied to the second surface 501b of the wafer 501 using a spray (spray) process.

The coating 107 has a top surface 107a, a bottom surface 107b opposite the top surface 107a, and sidewalls 107c connecting the top surface 107a and the bottom surface 107 b. The top surface 107a and the bottom surface 107b may be substantially flat surfaces. The sidewalls 107c may be substantially perpendicular to the top surface 107a and the bottom surface 107 b. The coating 107 may have a thickness in the Y-direction. The thickness of the coating 107 may be equal to or less than about 10 μm, such as, but not limited to, about 10 μm, about 6 μm, about 5 μm, about 4 μm, about 3 μm, about 2 μm. The coating 107 has material properties that repel the underfill 105. The material of the coating layer 107 may be selected from any material that is capable of dewetting the underfill 105. The material of coating 107 may include, for example, but is not limited to, silicon and urethane resins, silicone resins, urethane resins, combinations of silicone resins and urethane resins, acrylic urethane resins, or acrylic silicone resins.

As shown in fig. 5D, a baking (baking) process and a curing (curing) process are performed on the coating layer 107. The drying time, curing time, temperature, and other relevant parameters may be determined based on the material and thickness of the coating 107.

As shown in fig. 5E, the wafer 501 is singulated to obtain a plurality of first semiconductor dies 103 having the coating 107.

As shown in fig. 5F, the first semiconductor die 103 with the coating 107 is connected to the top surface 101a of the carrier 101 by a flip chip bonding process via the conductor bumps 103d of the first semiconductor die 103. The carrier 101 may be a substrate having a top surface 101a and a bottom surface 101b opposite the top surface 101 a. The top surface 101a and the bottom surface 101b may be substantially flat surfaces. In some embodiments, the top surface 101a and/or the bottom surface 101b may include recessed structures disposed as desired. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the top surface 101a for electrical connection with the first semiconductor die 103, and/or other electronic components carried by the carrier 101. In some embodiments, the carrier 101 may include one or more bond pads disposed proximate the bottom surface 101b for electrical connection with other electronic components located outside the semiconductor package structure 100. In some embodiments, the carrier 101 may comprise a plurality of layers, which may include dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. In certain embodiments, the carrier 101 may be composed of any suitable type of substrate material.

As shown in fig. 5G, the underfill 105 is applied between the top surface 101a of the carrier 101 and the first surface 103a of the first semiconductor die 103 to encapsulate each of the conductive bumps 103d, thereby providing sufficient support for the conductive bumps 103d to prevent the possibility of deformation of the conductive bumps 103d in the presence of a large pressure. After applying the underfill 105, the step shown in fig. 5G further includes performing a curing process to cure the applied underfill 105. In some embodiments, the underfill 105 may also coat a portion of the sidewalls 103c of the first semiconductor die 103, but due to the "dewet" nature of the coating 107, the underfill 105 is not present on the second surface 103b of the first semiconductor die 103. The material of the underfill 105 may be any suitable type of underfill material commonly used in the art, such as, but not limited to, a thermosetting epoxy resin.

As shown in fig. 5H, an injection molding process is performed such that the encapsulant 109 encapsulates the carrier 101, the first semiconductor die 103, the underfill 105, and the coating 107. The material of the encapsulant 109 may be an encapsulant material commonly used in the art. The encapsulant 109 and carrier 101 may then be cut along the line B-B shown in fig. 5H, resulting in a plurality of semiconductor package structures 100 as shown in fig. 1.

After the step of applying the underfill 105 shown in fig. 5G is completed and before the injection molding process shown in fig. 5H is performed, one or more semiconductor dies may be stacked on the second surface 103b of the first semiconductor die 103 using the same method as described in fig. 4F to obtain a package with a plurality of stacked semiconductor dies according to actual product requirements.

Fig. 6 is a schematic top view of a plurality of semiconductor dies mounted on a carrier board according to an embodiment of the present application.

As shown in fig. 6, a carrier 101 has a plurality of semiconductor dies mounted thereon. The carrier 101 may be divided into an area a and an area B. A plurality of first semiconductor dies 103 provided according to embodiments of the present application are included in region a, and a second surface of each semiconductor die 103 has a coating 107. A plurality of second semiconductor dies 601 are included in region B, each second semiconductor die 601 having a surface 601a that is free of a coating. The thickness of second semiconductor die 601 is greater than the thickness of first semiconductor die 103, so underfill 105 does not easily creep to surface 601a of second semiconductor die 601 when underfill 105 is applied. Thus, the surface 601a of each semiconductor die 601 may be free of a coating. A rolling process or a stamping process as shown in fig. 4A, 4B', 4C, 4D, 4E and 4F may be selectively performed at region a of fig. 6 to apply the coating 107 to the second surface 103B or the back surface of the first semiconductor die 103. Alternatively, the semiconductor package structure 100 completed by the wafer-level process of fig. 5A, 5B, 5C', 5D, 5E, 5F, 5G and 5H and diced may be selectively disposed in the area a of fig. 6.

The embodiment that this application provided can prevent that the back of the chip of thickness is less contaminated in the in-process of applying the underfill to guaranteed the level and smooth and clean of the back of chip, therefore had better product quality. Meanwhile, the coating layer on the back surface of the chip and the bonding layer have good bonding force, so that the multi-layer stacked semiconductor structure provided by the application has stable product quality.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims (15)

1. A semiconductor package, comprising:

a carrier;

a first semiconductor die on the carrier, the first semiconductor die having a first surface facing the carrier and a second surface opposite the first surface;

an underfill between the carrier and the first surface; and

a coating on the second surface, the coating configured to de-wet the underfill.

2. The semiconductor package structure of claim 1, further comprising:

a second semiconductor die located over the second surface of the first semiconductor die; and

an adhesive layer between the first semiconductor die and the second semiconductor die.

3. The semiconductor package structure of claim 2, wherein the adhesive layer is laminated on the coating.

4. The semiconductor package structure of claim 1, wherein the first semiconductor die is flip chip bonded to the carrier.

5. The semiconductor package structure of claim 1, in which the underfill is absent from the second surface of the first semiconductor die.

6. The semiconductor package structure of claim 1, wherein the thickness of the first semiconductor die is equal to or less than 100 μ ι η.

7. The semiconductor package structure of claim 1, further comprising bond pads on the carrier, a lateral distance between the bond pads and sidewalls of the first semiconductor die being less than 500 μ ι η.

8. The semiconductor package structure of claim 7, further comprising bond wires connecting the bond pads to a second semiconductor die located over the second surface of the first semiconductor die.

9. The semiconductor package structure of claim 2, wherein a width of the coating is narrower than a width of the second semiconductor die.

10. The semiconductor package structure of claim 9, further comprising a spacer on the carrier, the spacer supporting the second semiconductor die from an edge of the second semiconductor die, a top surface of the spacer being coplanar with a top surface of the coating.

11. The semiconductor package structure of claim 2, wherein a width of the coating is the same as a width of the second semiconductor die.

12. The semiconductor package structure of claim 1, further comprising an encapsulant encapsulating the underfill, the first semiconductor die, and the coating.

13. The semiconductor package structure of claim 1, wherein sidewalls of the coating are aligned with sidewalls of the first semiconductor die.

14. The semiconductor package structure of claim 1, wherein the coating has a thickness of less than 5 μ ι η.

15. The semiconductor package structure of claim 1, wherein the coating is selected from one of a silicone, a polyurethane, an acrylic urethane, or an acrylic silicone.

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