CN213042232U - IO board based on MisTer FPGA technology - Google Patents

Abstract

The utility model provides a IO board based on MisTer FPGA technique, the bottom of IO board is provided with the mother board, and the mother board is DE10-Nano FPGA development board, and the integration has the USB HUB module on the IO board, and the USB HUB module includes a plurality of USB interfaces and a USB HUB chip, USB interface and USB HUB chip set up on the IO board. The utility model provides high external USB equipment stability and reliability of operation, the integration of several function module systems scattered originally is in the same place, has optimized the space of whole product portable more and has placed again, very big improvement user's simplicity in operation, reduced size and volume when having increased the function, reduced the complexity of production and processing manufacturing equipment, reduced holistic manufacturing material and cost.

Description

IO board based on MisTer FPGA technology

Technical Field

The utility model relates to an integrated circuit technical field specifically is an IO board based on MisTer FPGA technique.

Background

MisTer is an open source project based On FPGA technology, and aims to reproduce original hardware and circuit structures of various classical computer systems by using advanced circuit simulation technology in The world at present, such as PC486, Apple II, Altair, Super Nitndo Enterprise System, SEGA Mega Drive and The like, The project has certain value for experiencing and researching some classical software programs On The classical computer systems, dozens of computer systems can be perfectly reconstructed at present, Mister adopts a DE10-Nano FPGA development board produced by terasic company as a base, The development board carries a Cyclone V FPGA 5CSEBA6U23I7 chip and a Cortex-A9 processor, and The basic IO interface comprises 1 MicroSD card slot, 1 HDMI2.0 digital interface, 1 RJ45 thousand Ethernet interface, 1 USB Micro-2.0 OnARM-USB interface (USB) and The USB interface is called for short under The USB for USB (OTG), The USB-UART interface, the USB flush interface and the 2 GPIO interfaces can be used for expanding more IO interfaces, peripheral equipment such as a mouse, a keyboard, a joystick and other controllers can be connected through the IO interfaces, a software program can run on real hardware, and compared with the existing virtual machines and simulators, the USB-UART interface, the USB flush interface and the 2 GPIO interfaces have more accurate running results and more efficient computing efficiency. In order to restore the actual operation conditions of the classical computer systems more truly and the actual operation mode of the MisTer, a 128Mb SDRAM memory board is expanded through a GPIO1 interface on a DE10-Nano FPGA development board, a program can be allowed to run at the low-speed frequency of 140MHZ to realize more accurate operation, an additional IO board is expanded on a second GPIO interface, and the board has the functions of further expanding the input and output functions of the MisTer, increasing a 3.5mm stereo interface, an optical fiber audio output interface, a simulation comprehensive output interface, and increasing a cooling fan and three function keys.

The existing hardware circuit design of the MisTer has serious defects on an input part of a USB device, and the input part has the problems that a DE10-Nano FPGA development board adopted by the MisTer only has 1 USB Micro OTG interface, and when a user wants to simultaneously access a plurality of USB devices (such as a mouse, a keyboard, a mobile hard disk and the like), the user has to select an external USB HUB to expand the number of the USB interfaces, but because the accessed USB devices in a bus power supply mode in a USB2.0 protocol specification can only obtain 0.5A current at most, a plurality of problems often occur in practical use. For example, the equipment that the power supply was not enough when the USB equipment that inserts was too much caused works unusually, inserts high-power USB mobile hard drive etc. and establishes the unable start-up of not enough complete machine of power supply when other, and external USB HUB equipment connecting wire is not hard up easily, often pulls out and inserts external USB HUB and also damages the only USB Micro OTG interface on the development board, leads to the condemned hidden danger of expensive DE10-Nano FPGA development board, and complicated loaded down with trivial details wiring mode also occupies more extra space and influences pleasing to the eye scheduling problem. In addition, an additional IO board is expanded on the upper layer of the existing FPGA development board through a second GPIO interface, an additionally customized USBHUB module can be selected and matched on the bottom layer, the hidden danger problem that the USB 10-Nano FPGA development board USB Micro OTG interface is damaged due to the trouble of external USB HUB wiring is solved by the module, but the problem caused by insufficient power supply cannot be solved fundamentally by adopting 'bus type power supply', a three-layer structure is arranged totally, the whole size is large, the occupied space of the three-layer structure is large, the functional modules are scattered, the integration level and the stability are low, the complexity of production, processing and manufacturing assembly is increased, and further the whole production materials and the manufacturing cost are increased.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an IO board based on MisTer FPGA technique, can external a plurality of USB equipment and power supply stable, occupation space is less, has higher integrated level and stability.

To achieve the above objective, the present invention provides the following technical solutions: the utility model provides a IO board based on MisTer FPGA technique, the bottom of IO board is provided with the mother board, and the mother board is DE10-Nano FPGA development board, and the integration has the USB HUB module on the IO board, and the USB HUB module includes a plurality of USB interfaces and a USB HUB chip, USB interface and USB HUB chip set up on the IO board, the last power stitch in the GPIO mouth of FPGA development board supplies power to the USB HUB module.

Further, in the utility model discloses in, the power stitch provides +5V power supply stitch for the second GPIO interface.

Further, the utility model discloses in, the IO board is provided with Video signal decoding chip, and Video signal decoding chip is used for the RGBS Video signal, colour difference yprpB Video signal, compound Video signal and the S-Video signal of NTSC/PAL trial system for the standard with the synthetic output of original RGBHV signal, and this signal will be can the general display device of safe and stable access.

Further, the utility model discloses in, the IO board includes the integrated circuit board base, the integrated circuit board base is printed circuit board, the integrated circuit board base is provided with the function button, the mid-mounting of integrated circuit board base has radiator fan, radiator fan's both sides are provided with fan interface and fan speed governing switch, fan interface is used for connecting the fan, fan speed governing switch controls the fan gear, the right-hand member of integrated circuit board base still is provided with Serial interface, analog audio interface and synthesizes the output interface, still be provided with video output change over switch on the integrated circuit board base for video output's conversion control.

Further, the utility model discloses in, the USB interface is four, and four USB interfaces are first USB interface, second USB interface, third USB interface and fourth USB interface respectively, second USB interface and third USB interface are located the left end at integrated circuit board base top, first USB interface and fourth USB interface are located the both sides of integrated circuit board base top left end.

Further, the utility model discloses in, be provided with USB Micro OTG interface an on the IO board, be provided with USB Micro OTG interface b on the mother board, USB Micro OTG interface a passes through USB bridge connection USB Micro OTG interface b, still is provided with main FPGA chip, power source, memory board, USB-UART interface, RJ45 ethernet interface, HDMI interface, USB blaster interface, first GPIO interface, second GPIO interface and MicroSD slot on the mother board.

The beneficial effects are that the technical scheme of this application possesses following technological effect:

1. the utility model discloses in integrating the IO board with USB HUB function, unified IO board and the partial power supply line of USB HUB, thorough solution USB equipment insert because of the unstable various problems that produce of power supply, improved the stability and the reliability of external USB equipment operation, the user mode after the integration is more simple and convenient can accomplish plug-and-play, and need not to do extra explanation to the user.

2. The utility model discloses RGBS Video Signal, colour difference YprPb Video Signal, compound Video Signal (Composite Video Signal) and S-Video (isolate Video) Video Signal output function have been increased, great expansion the occasion that the product used.

3. The utility model discloses have high integrated level and stability for current product, be in the same place the integration of several function module systems scattered originally, optimized the space of whole product portable more and placed again, very big improvement user's simplicity in operation, reduced size and volume when having increased the function, reduced the complexity of production and processing manufacturing equipment, reduced holistic manufacturing material and cost.

It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below can be considered as part of the inventive subject matter of the present disclosure unless such concepts are mutually inconsistent.

The foregoing and other aspects, embodiments and features of the present teachings can be more fully understood from the following description taken in conjunction with the accompanying drawings. Additional aspects of the present invention, such as features and/or advantages of exemplary embodiments, will be apparent from the description which follows, or may be learned by practice of the specific embodiments in accordance with the teachings of the present invention.

Drawings

The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Embodiments of various aspects of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

fig. 1 is a schematic view of the three-dimensional structure of the mother board and the IO board of the present invention after connection.

Fig. 2 is the perspective structure schematic diagram of the mother board and the IO board of the present invention after being connected.

Fig. 3 is the structural schematic diagram of the IO plate of the present invention.

Fig. 4 is the structural schematic diagram of the IO plate of the present invention.

Fig. 5 is a schematic diagram of the motherboard structure of the present invention.

Fig. 6 is a schematic diagram of a part of the circuit of the present invention.

Fig. 6A is a schematic diagram of a portion of the circuit of fig. 6 according to the present invention.

Fig. 6B is a schematic diagram of a portion of the circuit of fig. 6 according to the present invention.

Fig. 6C is a schematic diagram of a portion of the circuit of fig. 6 according to the present invention.

Fig. 6D is a schematic diagram of a portion of the circuit of fig. 6 according to the present invention.

Fig. 7 is a schematic diagram of a part of the circuit of the present invention.

Fig. 8 is a schematic diagram of a part of the circuit of the present invention.

Fig. 9 is a schematic diagram of a part of the circuit of the present invention.

In the figures, the meaning of the reference numerals is as follows: 1. a board card base; 2. a heat radiation fan; 3. a fan speed regulation switch; 4. a fan interface; 5. a serial interface; 6. an audio interface; 7. a comprehensive output interface; 8. a video output changeover switch; 9. a video signal decoding chip; 10. function keys; 11. USB Micro OTG interface a; 12. a first USB interface; 13. a second USB interface; 14. a USB HUB chip; 15. a third USB interface; 16. a fourth USB interface; 17. a motherboard; 18. a power interface; 19. an HDMI interface; 20. a USB flush; 21. a second GPIO interface; 22. an RJ45 ethernet interface; 23. a USB-UART interface; 24. USB Micro OTG interface b; 25. a memory board; 26. a first GPIO interface; 27. a main FPGA chip; 28. a USB bridge; 29. and a MicroSD slot.

Detailed Description

For a better understanding of the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. In this disclosure, aspects of the present invention are described with reference to the accompanying drawings, in which a number of illustrative embodiments are shown. Embodiments of the present disclosure are not necessarily intended to include all aspects of the invention. It should be appreciated that the various concepts and embodiments described above, as well as those described in greater detail below, may be implemented in any of numerous ways, as the disclosed concepts and embodiments are not limited to any implementation. Additionally, some aspects of the present disclosure may be used alone or in any suitable combination with other aspects of the present disclosure.

The IO board based on the MisTer FPGA technology as shown in fig. 1 to 5 includes a board base 1, the board base 1 is a printed circuit board, when the IO board is used, the IO board is connected to a motherboard 17, and the motherboard 17 of this embodiment is a DE10-Nano FPGA development board.

As shown in fig. 1-3, a USB HUB module is integrated in the left area of the IO board and powered by a +5V power pin in a GPIO port on the DE10-Nano FPGA development board, and the USB HUB module includes a first USB interface 12, a second USB interface 13, a third USB interface 15, a fourth USB interface 16 and a USB HUB chip 14, where the first USB interface 12, the second USB interface 13, the third USB interface 15, the fourth USB interface 16 and the USB HUB chip 14 are all disposed on the board base 1, and the first USB interface 12, the second USB interface 13, the third USB interface 15 and the fourth USB interface 16 are preferably disposed on the top of the board base 1, the second USB interface 13 and the third USB interface 15 are disposed on the left end of the top of the board base 1, the first USB interface 12 and the fourth USB interface 16 are disposed on two sides of the left end of the top of the board base 1, so that the connection is convenient and the connection does not occupy the lower space, more reasonable utilization the space at 17 tops of motherboard, this improvement can keep stable operation when external high-power USB equipment (like USB machinery mobile hard disk) in the actual test, and this improvement also does not need external USB HUB alone to use in integrated the IO board to MisTer for the first time with the USB HUB function simultaneously, great improvement holistic functional integrity, stability, use convenience and whole pleasing to the eye degree. It can be known that, with the USB HUB function integration to the IO board, unified IO board and the partial power supply line of USB HUB, the thorough various problems of having solved USB equipment and inserting have improved the stability and the reliability of external USB equipment operation, and plug-and-play can be accomplished to the user mode of use after the integration more portably, and need not to do extra explanation to the user.

The right side area of IO board has carried out following layout design, the mid-mounting of integrated circuit board base 1 has radiator fan 2, radiator fan 2 'S both sides are provided with fan interface 4 and fan speed governing switch 3, fan interface 4 is used for connecting fan 2, fan speed governing switch 3 controls fan 2 gear, in addition, integrated circuit board base 1' S right-hand member still is provided with serial interface 5, audio interface 6 and comprehensive output interface 7, wherein comprehensive output interface 7 type can be the S-Video interface, and then can connect some old-fashioned TV sets or display device. The system comprises a board card base 1, a heat radiation fan 2 arranged on an IO board and a serial interface 5, wherein the heat radiation fan is responsible for radiating heat for an FPGA chip and a whole machine; the audio interface 6 provides 3.5cm \ optical fiber audio output; the integrated output interface 7 outputs various analog video signals and analog audio signals; the board card base 1 is further provided with a video output selector switch 8 for switching 4 types of analog video signals in the integrated output interface 7.

In the using process, the existing Video output part of the device is not perfect enough, and the existing MisTer Video output part only provides HDMI digital Signal output and RGBHV analog Signal output, but for many computer systems, the original Video output also includes Composite Video Signal output and S-Video (separate Video) Signal output, which is a functional defect for many users who want to completely experience the original effect of the operation of these classical computer systems, and at present, the users who need these Signal outputs can only additionally select the Video converter with poor effect on the market for transcoding, which brings many image quality losses. Therefore, a Video Signal decoding chip 9 is further disposed on the board base 1, and the Video Signal decoding chip 9 is configured to synthesize and output the original RGBHV Signal as a standard NTSC/PAL trial RGBS Video Signal, a color difference YprPb Video Signal, a Composite Video Signal (Composite Video Signal), and an S-Video (separate Video) Video Signal, which can be safely and stably connected to a common display device. The RGBS Signal, the color difference YprPb Signal, the Composite Video Signal and the S-Video (separate Video) Signal output function are added, and the use occasions of the product are greatly expanded.

The video signal decoding chip 9n can decode the original analog video signal in the low edition and output a plurality of analog video signals, the board card base 1 is also provided with three function keys 10, and the three function keys 10 complete some basic operations: such as cold restart, system core reset, menus, bluetooth connections, controller key function mapping, etc.; the IO board is provided with a USB Micro OTG interface a 11, the motherboard 17 is provided with a USB Micro OTG interface b 24, and the USB Micro OTG interface a 11 is connected with the USB Micro OTG b 24 through a USB bridge 28.

The motherboard 17 is further provided with a main FPGA chip 27, a power interface 18, an additionally accessed memory board 25, a USB-UART interface 23, an RJ45 ethernet interface 22, an HDMI interface 19, a USB blast interface 20, a first GPIO interface 26, a second GPIO interface 21, and a MicroSD slot 29.

The main FPGA chip 27 is responsible for hardware circuit simulation operation, the power interface 18 is used for accessing a main power supply +5v power supply, the internal memory board 25 is matched with the main FPGA chip 27 to enable the device to work at the highest 140MHz frequency, the USB-UART interface 23 can enable the device to be connected with a computer USB for data transmission, the RJ45 Ethernet interface 22 can provide network functions such as networking connection, FTP, SMB, NAS and the like, the HDMI interface 19 can output digital video and audio signals, the USB flush 20 is used for program burning, debugging, DBUG and the like, the first GPIO interface 26 is used for connecting an expanded SDRAM internal memory board, the second GPIO interface 21 is used for connecting an IO board, and the MicroSD slot 29 is used for installing a MicroSD card storage system and program data.

Fig. 6-9 show circuit diagrams in this embodiment, fig. 6 is divided into fig. 6A, 6B, 6C and 6D for clearer representation, and fig. 6 shows a circuit diagram of a portion where the IO board is connected to the DE10-Nano FPGA development board through the second GPIO interface 21, that is, a circuit diagram of processing and separating signals in the second GPIO interface 21 into an original analog video (RGBHV) signal, an analog audio signal, an operation status indication signal, a serial port data transmission signal, and +5v power supply. The circuit of fig. 7 shows a circuit structure of a USB HUB part integrated in an IO board, and a +5V power supply part of the circuit is provided in a second GPIO interface 21 on a DE10-Nano FPGA development board, so as to provide 4 USB interfaces. Fig. 8 shows a Video decoding portion in the IO board, which modulates and synthesizes the original analog Video Signal (RGBHV) separated from the second GPIO interface 21 by using an AD724 decoding chip, outputs an RGBS Video Signal, a color difference YprPb Video Signal, a Composite Video Signal, and an S-Video (separate Video) Video Signal that conform to the NTSC \ PAL trial specification, and switches the types of the output signals by using a 4-way switch. The circuit of fig. 9 shows an interface for analog Video and analog audio output on the IO board, which adopts an S-Video (Mini DIN 10P) type mother socket to simultaneously transmit 10 signals, and is responsible for outputting RGBS Video signals, color difference yprppb Video signals, Composite Video signals, and S-Video (separate Video) Video signals and analog audio signals generated in the IO board.

Working principle (actual use process): after obtaining the DE10-Nano FPGA development board, the memory board, and the IO board in this embodiment, a user may start to construct a complete set of MisTer FPGA system, insert the memory board 25 and the IO board into the GPIO1 interface and the second GPIO interface 21 on the DE10-Nano FPGA development board, connect the USB Micro OTG interface a 11 on the IO board and the USB Micro OTG interface b 24 on the DE10-Nano FPGA development board with the USB bridge 28, then connect the HDMI digital signal line to the HDMI interface 19 for connecting to the display devices such as the liquid crystal display or the liquid crystal television, and at the same time, the user may select an analog video/audio signal line to connect to the integrated output interface 7 on the IO board to connect to the display devices such as the CRT color monitor or the CRT television according to the use situation, insert a Micro sd card (exfat format) containing the system, the core program, and the user data into the Micro sd slot 29, inserting a mobile hard disk or a U disk with a kernel program and user data into 4 USB interfaces (exfat format, only used as a data storage expansion device, and unnecessary components) in an IO board, accessing a keyboard, a mouse, a controller, a Bluetooth adapter, a wifi adapter and other devices onto the 4 USB interfaces (selecting and accessing the required devices according to the specific use condition of a user), finally accessing a +5V (rated current 2A or higher) power supply into a power input interface 18 on a DE10-Nano FPGA development board, displaying a MisTer startup picture on display equipment at the moment, pairing the Bluetooth devices and mapping the key functions of the controller by using three functional keys on the IO board, then operating and selecting a specific kernel program to load and operate through the mouse keyboard or the controller, and in use, enabling a user to connect a router through an RJ45 Ethernet interface or a wifi wireless network card and adopting FTP or SMB or other modes through a computer And reading and writing operations are carried out on the MicroSD card and the mobile storage equipment which enter the MisTer, and the +5V power supply is disconnected after the use is finished.

And although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the invention. The present invention is intended to cover by those skilled in the art various modifications and adaptations of the invention without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims (6)

1. The utility model provides a IO board based on MisTer FPGA technique, the bottom of IO board is provided with the mother board, and the mother board is DE10-Nano FPGA development board, its characterized in that: the integrated USB HUB module that has on the IO board, the USB HUB module includes a plurality of USB interfaces and a USB HUB chip, USB interface and USB HUB chip set up on the IO board, the power stitch in the second GPIO interface supplies power to the USB HUB module on the FPGA development board.

2. The IO board based on MisTer FPGA technology of claim 1, wherein: the power supply pin is a +5V power supply pin.

3. The IO board based on MisTer FPGA technology of claim 1, wherein: the IO board is provided with a Video signal decoding chip, the Video signal decoding chip is used for synthesizing and outputting the original RGBHV signal into a standard NTSC/PAL trial-produced RGBS signal, a color difference YprPb signal, a composite Video signal and an S-Video signal, and the signal can be safely and stably connected into common display equipment.

4. The IO board based on MisTer FPGA technology of claim 1, wherein: the IO board includes the integrated circuit board base, the integrated circuit board base is printed circuit board, the integrated circuit board base is provided with the function button, the mid-mounting of integrated circuit board base has radiator fan, radiator fan's both sides are provided with fan interface and fan speed governing switch, fan interface is used for connecting the fan, fan speed governing switch controls the fan gear, the right-hand member of integrated circuit board base still is provided with serial interface of serial, audio interface and synthesizes the output interface, still be provided with video output change over switch on the integrated circuit board base for video output's conversion control.

5. The IO board based on MisTer FPGA technology of claim 1, wherein: the USB interface is four, and four USB interfaces are first USB interface, second USB interface, third USB interface and fourth USB interface respectively, second USB interface and third USB interface are located the left end at integrated circuit board base top, first USB interface and fourth USB interface are located the both sides of integrated circuit board base top left end.

6. The IO board based on MisTer FPGA technology of any one of claims 1-5, wherein: the USB flash drive is characterized in that a USB Micro OTG interface a is arranged on the IO board, a USB Micro OTG interface b is arranged on the mother board, the USB Micro OTG interface a is connected with the USB Micro OTG interface b through a USB bridge, and a main FPGA chip, a power interface, a memory board, a USB-UART interface, an RJ45 Ethernet interface, an HDMI interface, a USB flush, a first GPIO interface, a second GPIO interface and a MicroSD slot are further arranged on the mother board.

Images