CN213027444U - Data line plug circuit - Google Patents
Data line plug circuit Download PDFInfo
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- CN213027444U CN213027444U CN202020808531.4U CN202020808531U CN213027444U CN 213027444 U CN213027444 U CN 213027444U CN 202020808531 U CN202020808531 U CN 202020808531U CN 213027444 U CN213027444 U CN 213027444U
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Abstract
The utility model discloses a data line plug circuit, including first joint J1, second joint J2, switch circuit and chip U1, first joint J1's positive negative pole and second joint J2's positive negative pole correspond to be connected, switch circuit includes MOS pipe Q9, resistance R1 and resistance R2, MOS pipe Q9 source is connected with first joint J1's VCC end, MOS pipe Q9 drain electrode is connected with second joint J2's OUT end, resistance R1 one end and MOS pipe Q9 gate are connected, the resistance R1 other end is connected with chip U1's door control pin, MOS pipe Q9's source electrode and drain electrode are connected respectively to resistance R2 both ends, chip U1's USB pin and OUT pin connect first joint J1's VCC end and second joint J2's OUT end respectively, second joint J2's ID end and chip U1's communication connection pin. The utility model provides a simple structure, anti surge, electrostatic interference's data line plug circuit.
Description
Technical Field
The utility model relates to a plug circuit technical field especially relates to a data line plug circuit.
Background
The mobile phone is an essential article in life, the capacity of the mobile phone battery is limited, and the power consumption is fast under the condition of high use frequency. When the electricity of the mobile phone is used up, the mobile phone must be charged, and the existing mobile phone products are generally designed schemes of non-detachable batteries, so that a charging data line must be connected during charging.
The charging data line is widely applied to daily life of people, but the interference problems such as surge and static electricity generally occur in the charging process. The existing charging data line has a complex anti-surge structure and high production cost; and its antistatic grade is also relatively lower, can't effectual prevention high strength static to the destruction of charging data line, and the security is relatively poor.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a simple structure, anti surge, electrostatic interference's data line plug circuit.
The utility model discloses a technical scheme that data line plug circuit adopted is:
a data line plug circuit comprises a first joint J1, a second joint J2, a switch circuit and a chip U1, wherein the positive pole and the negative pole of the first joint J1 are correspondingly connected with the positive pole and the negative pole of the second joint J2, the switch circuit comprises a MOS tube Q9, a resistor R1 and a resistor R2, the source of the MOS tube Q9 is connected with the VCC end of the first joint J1, the drain of the MOS tube Q9 is connected with the OUT end of the second joint J2, one end of the resistor R1 is connected with the gate of the MOS tube Q9, the other end of the resistor R1 is connected with the gate control pin of the chip U1, the two ends of the resistor R2 are respectively connected with the source and the drain of the MOS tube Q9, the USB pin and the OUT pin of the chip U1 are respectively connected with the VCC end of the first joint J1 and the OUT end of the second joint J2, and the ID end of the second joint J2 is connected with the communication pin of the chip U1.
Preferably, a ground transient suppression diode TVS1 is additionally arranged between the source of the MOS transistor Q9 and the VCC terminal of the first junction J1, the communication pin of the chip U1 is further connected to the ground transient suppression diode TVS2, and the transient suppression diode TVS1 and the transient suppression diode TVS2 are both bidirectional.
Preferably, a protection resistor R3 is disposed between the USB pin of the chip U1 and the VCC terminal of the first connector J1.
Preferably, the VDD pin of the chip U1 is connected to a ground capacitor C1.
Preferably, the resistance value of the resistor R1 is in a range of 50 Ω to 1k Ω.
Preferably, the model of the chip U1 is MC 9047.
The utility model discloses a data line plug circuit's beneficial effect is: the positive and negative poles of the first joint J1 and the positive and negative poles of the second joint J2 are correspondingly connected, the switch circuit comprises an MOS tube Q9, a resistor R1 and a resistor R2, the source of the MOS tube Q9 is connected with the VCC end of the first joint J1, the drain of the MOS tube Q9 is connected with the OUT end of the second joint J2, one end of the resistor R1 is connected with the gate of the MOS tube Q9, the other end of the resistor R1 is connected with the gate control pin of the chip U1, the two ends of the resistor R2 are respectively connected with the source and the drain of the MOS tube Q9, the USB pin and the OUT pin of the chip U1 are respectively connected with the VCC end of the first joint J1 and the VCC OUT end of the second joint J2, and the ID end of the second joint J2 is connected with the communication pin. The gate control pin of the chip U1 controls the MOS transistor Q9 to form a gate resistor structure, namely, the gate resistor structure has the functions of voltage division and current limitation, effectively inhibits surge voltage and can discharge static electricity. The resistor R2 is used for protecting the MOS transistor Q9. Simple structure, can reduce manufacturing cost to a great extent.
Drawings
Fig. 1 is a schematic structural diagram of a data line plug circuit of the present invention.
Detailed Description
The invention will be further elucidated and described with reference to the following embodiments and drawings in which:
referring to fig. 1, a data line plug circuit includes a first connector J1, a second connector J2, a switch circuit 10, and a chip U1.
The positive and negative poles of the first joint J1 and the positive and negative poles of the second joint J2 are correspondingly connected.
The switch circuit 10 comprises a MOS transistor Q9, a resistor R1 and a resistor R2, a source of the MOS transistor Q9 is connected to a VCC terminal of a first connector J1, a drain of the MOS transistor Q9 is connected to an OUT terminal of a second connector J2, one end of the resistor R1 is connected to a GATE of the MOS transistor Q9, the other end of the resistor R1 is connected to a GATE control pin (corresponding to a GATE pin of a chip U1 in the figure) of a chip U1, two ends of the resistor R2 are respectively connected to a source and a drain of the MOS transistor Q9, a USB pin and an OUT pin of the chip U1 are respectively connected to a VCC terminal of the first connector J1 and a VCC OUT terminal of the second connector J2, and an ID terminal of the second connector J2 is connected to a communication pin of the chip U1.
The gate control pin of the chip U1 controls the MOS transistor Q9 to form a gate resistance structure. The voltage division and current limiting functions are realized, and the overvoltage phenomenon caused by surge is effectively inhibited; static electricity can be discharged, and the chip U1 can be effectively prevented from being burnt out. The resistor R2 is used for protecting the MOS transistor Q9. The whole circuit structure is relatively simple, and the production cost can be greatly reduced.
Preferably, the resistance of the resistor R1 in this example is in the range of 50 Ω to 1k Ω. R1 in this case is preferably 1 k.OMEGA.. So as to improve the pressure resistance.
A ground transient suppression diode TVS1 is additionally disposed between the source of the MOS transistor Q9 and the VCC terminal of the first junction J1, so as to prevent the chip U1 from malfunction due to transient pulse, such as electrostatic discharge effect and power surge. By using the transient suppression diode TVS1, the pulse which can cause the damage of the chip U1 can be effectively absorbed, and the electrostatic interference can be eliminated.
The communication pin of the chip U1 is also connected to the ground transient suppression diode TVS2, which can change the high impedance between the two poles into low impedance at the speed of 10 minus 12 times of a second when the two poles of the transient suppression diode TVS2 are impacted by high energy of reverse transient, so as to absorb high surge power, clamp the voltage between the two poles at a predetermined value, and effectively protect the chip U1 from the damage of surge pulse.
In this example, the transient suppression diode TVS1 and the transient suppression diode TVS2 are both bidirectional.
Preferably, a protection resistor R3 is disposed between the USB pin of the chip U1 and the VCC terminal of the first connector J1. For protecting chip U1.
The VDD pin of the chip U1 is connected with a grounding capacitor C1 for noise reduction.
In this example, the chip U1 is an IC chip of type MC 9047.
The utility model provides a data line plug circuit, the positive negative pole that first joint J1 connects J2 with the positive negative pole corresponds to be connected, switch circuit includes MOS pipe Q9, resistance R1 and resistance R2, MOS pipe Q9 source electrode is connected with the VCC end that first joint J1, MOS pipe Q9 drain electrode is connected with the OUT end that the second connects J2, resistance R1 one end is connected with MOS pipe Q9 grid, the resistance R1 other end is connected with chip U1's door control pin, MOS pipe Q9's source electrode and drain are connected respectively at resistance R2 both ends, chip U1's USB pin and OUT pin connect first joint J1's VCC end and second joint J2's VCC OUT end respectively, the ID end that the second connects J2 is connected with chip U1's communication pin. The gate control pin of the chip U1 controls the MOS transistor Q9 to form a gate resistance structure, so that surge voltage is effectively inhibited, and static electricity can be discharged. The resistor R2 is used for protecting the MOS transistor Q9. Simple structure, can reduce manufacturing cost to a great extent.
It should be finally noted that the above embodiments are only intended to illustrate the technical solutions of the present invention, and not to limit the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention can be modified or replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention.
Claims (6)
1. A data line plug circuit is characterized by comprising a first joint J1, a second joint J2, a switch circuit and a chip U1, wherein the positive pole and the negative pole of the first joint J1 are correspondingly connected with the positive pole and the negative pole of the second joint J2, the switch circuit comprises a MOS tube Q9, a resistor R1 and a resistor R2, the source of the MOS tube Q9 is connected with the VCC end of the first joint J1, the drain of the MOS tube Q9 is connected with the OUT end of the second joint J2, one end of the resistor R1 is connected with the gate of the MOS tube Q9, the other end of the resistor R1 is connected with the gate control pin of the chip U1, two ends of the resistor R2 are respectively connected with the source and the drain of the MOS tube Q9, the USB pin and the OUT pin of the chip U1 are respectively connected with the VCC end of the first joint J1 and the VCC OUT end of the second joint J2, and the ID end of the second joint J2 is connected with the communication pin of the chip U1.
2. The data line plug circuit of claim 1, wherein a ground transient suppression diode TVS1 is additionally disposed between the source of the MOS transistor Q9 and the VCC terminal of the first junction J1, the communication pin of the chip U1 is further connected to a ground transient suppression diode TVS2, and the transient suppression diode TVS1 and the transient suppression diode TVS2 are both bidirectional.
3. The data line plug circuit according to claim 1, wherein a protection resistor R3 is disposed between the USB pin of the chip U1 and the VCC terminal of the first connector J1.
4. The data line plug circuit of claim 1, wherein a VDD pin of the chip U1 is connected to a ground capacitor C1.
5. A data line plug circuit according to any one of claims 1 to 4, wherein the resistance R1 has a value in the range of 50 Ω to 1kΩ.
6. The data line plug circuit of any one of claims 1-4, wherein the type of the chip U1 is MC 9047.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020808531.4U CN213027444U (en) | 2020-05-15 | 2020-05-15 | Data line plug circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020808531.4U CN213027444U (en) | 2020-05-15 | 2020-05-15 | Data line plug circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213027444U true CN213027444U (en) | 2021-04-20 |
Family
ID=75484361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020808531.4U Active CN213027444U (en) | 2020-05-15 | 2020-05-15 | Data line plug circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213027444U (en) |
-
2020
- 2020-05-15 CN CN202020808531.4U patent/CN213027444U/en active Active
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