CN213024806U - Image recognition device - Google Patents

Abstract

The utility model discloses an image recognition device relates to image recognition technical field, and it is current license plate image recognition system with high costs, bulky technical problem that mainly solves, the device includes microprocessor, power management chip, DDR3 memory, SD card, LCD display screen, audio interface module, USB interface module, the general CMOS camera of UVC form, and microprocessor connects power management chip, DDR3 memory, SD card, LCD display screen, general CMOS camera, audio interface module, USB interface module respectively. The utility model discloses a general CMOS camera gathers license plate image and sends microprocessor discernment to, then through LCD display screen output, whole integrated level is high, and is with low costs, small.

Description

Image recognition device

Technical Field

The utility model relates to an image recognition technical field, more specifically say, it relates to an image recognition device.

Background

Most of the traditional license plate image recognition systems in China adopt solutions based on platforms such as a DSP (digital signal processor), an FPGA (field programmable gate array), a PC (personal computer) and the like, and particularly, the solutions of the PC platform are the most common, and the solutions have the defects of high cost, high technical threshold, large size and the like, so that certain difficulty is caused in the practical application and popularization process.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is not enough to the above-mentioned of prior art, the utility model aims at providing an image recognition device with low costs, small.

The technical scheme of the utility model is that: an image recognition device comprises a microprocessor, a power management chip, a DDR3 internal memory, an SD card, an LCD display screen, an audio interface module, a USB interface module and a universal CMOS camera in UVC format, wherein the microprocessor is respectively connected with the power management chip, the DDR3 internal memory, the SD card, the LCD display screen, the universal CMOS camera, the audio interface module and the USB interface module.

As a further improvement, the microprocessor is of the type Allwinner-A13.

Further, the model of the power management chip is AXP 209.

Further, the model of the universal CMOS camera is OV 7670.

Further, the audio interface module is a headphone jack.

Further, the USB interface module comprises a USB-HOST interface used as HOST equipment and a USB-OTG interface used as HOST equipment and a debugging interface, the USB-HOST interface is connected with the microprocessor, and the USB-OTG interface is connected with the power management chip through an overcurrent protection chip.

Further, the model of the overcurrent protection chip is SY 6280.

Further, the USB-HOST interface is connected with a WiFi & BT module.

Further, the model number of the WiFi & BT module is RTL8723 BU.

Further, the human body input device is connected with the microprocessor.

Advantageous effects

Compared with the prior art, the utility model, the advantage that has does:

the utility model discloses a general CMOS camera gathers license plate image and sends microprocessor discernment to, then through LCD display screen output, whole integrated level is high, and is with low costs, small.

Drawings

Fig. 1 is a schematic diagram of a square frame structure of the present invention;

FIG. 2 is a wiring diagram of the microprocessor of the present invention;

FIG. 3 is a wiring diagram of the power management chip of the present invention;

FIG. 4 is a wiring diagram of the external current-to-voltage conversion according to the present invention;

fig. 5 is a wiring diagram of the DDR3 memory of the present invention;

FIG. 6 is a diagram of the SD card of the present invention;

FIG. 7 is a wiring diagram of the LCD display panel of the present invention;

FIG. 8 is a wiring diagram of the LCD backlight boosting of the present invention;

fig. 9 is a wiring diagram of a general CMOS camera of the present invention;

fig. 10 is a wiring diagram of the middle audio interface module according to the present invention;

FIG. 11 is a wiring diagram of the USB-OTG interface of the present invention;

FIG. 12 is a wiring diagram of the USB-HOST interface connection WiFi & BT module of the present invention;

FIG. 13 is a wiring diagram of the USB-HOST interface of the present invention connecting to the USB socket;

fig. 14 is a GPIO circuit diagram led out through the pin header in the present invention.

Detailed Description

The invention will be further described with reference to specific embodiments shown in the drawings.

Referring to fig. 1 to 14, an image recognition apparatus includes a microprocessor, a power management chip, a DDR3 memory, an SD card, an LCD display, an audio interface module, a USB interface module, a human body input device, and a universal CMOS camera in UVC format, where the microprocessor is connected to the power management chip, the DDR3 memory, the SD card, the LCD display, the universal CMOS camera, the audio interface module, the USB interface module, and the human body input device, respectively.

The microprocessor is of the type Allwinner-a13 (hereinafter referred to as a 13) and, as shown in fig. 2, a decoupling capacitor is placed near each power pin of the microprocessor in order to improve the stability of the microprocessor power supply and reduce the noise coupling of components to the power supply terminals. The clock source outside the microprocessor uses a 24M passive crystal oscillator, the frequency of the 24MHz external clock is multiplied to 1GHz through an internal CPU phase-locked loop (PLL), and the working main clock frequency of the CPU is 1GHz (fixed frequency).

The model of the power management chip is AXP209 (hereinafter referred to as AXP 209), and as shown in fig. 3, the power management chip AXP209 outputs 6 different types of voltages: the voltage of the CPU core is 1.2V, the voltage of the CPU interrupt is 1.2V, the voltage of the camera is 1.8V and 2.8V, the voltage of the on-chip analog peripheral is 3V, and the voltage of the RTC peripheral is 3.3V. A13 controls AXP209 through a two wire serial interface (TWI), and a13 controls the output voltage of the LDOx pin by setting the registers of AXP 209.

The non-maskable interrupt pin (pin 158) of a13 is connected to the interrupt pin (pin 48) of AXP209, and the reset pin (pin 159) of a13 is connected to the power-up preparation complete flag pin (pin 25) of AXP 209. This allows AXP209 to output a low on the interrupt pin and the power-on ready flag pin before AXP209 completes initialization of the power system, leaving a13 in a reset-to-stop state. When the AXP209 completes the initialization of the power system, the AXP209 outputs a high level at the interrupt pin and the power-on ready flag pin, and releases a13 to allow it to start operating.

The AXP209 manages the enabling of the external dc boost, buck chip via the EXTEN pin (pin 20). The CHSENCE pin (43 th pin) of the AXP209 is connected with the BAT1 and BAT2 pins by connecting a sampling resistor of 0.03 omega in parallel, and when the lithium battery is used for supplying power, the A13 can know the current electric quantity of the battery by reading an internal register of the AXP 209.

The utility model discloses a hardware system has 2 kinds of power supply modes, outside 5V power supply and lithium cell power supply. When the lithium battery is used for supplying power, the voltage of the common lithium battery is only 3.7V-4.2V, and the voltage for supplying power to external equipment when the system is used as a USB host cannot be met, so that the SY7208 BOOST converter chip is used for designing a BOOST circuit to generate 5V voltage. The SY8008 synchronous BUCK regulator chip is used for designing a BUCK BUCK circuit to generate 3.3V voltage (IO port power supply voltage for CPU) and 1.5V voltage (power supply voltage for DDR 3), namely a SY7208 boost converter chip and a SY8008 synchronous BUCK regulator chip are connected to a power management chip respectively. A schematic diagram of an external dc voltage conversion circuit is shown in fig. 4.

The utility model discloses the DDR3 memory working clock frequency who chooses for use is 533MHz, and DDR3 read-write operation speed is high, and DDR3 circuit part belongs to high-speed circuit, so need consider the signal delay between the different length signal lines when the wiring, and DDR 3's signal line must make isometric processing. The signal wires with the longest length are used as the standard for equal length, and the error between the lengths of the signal wires is controlled within +/-100 mils. The DDR3 differential signal lines are strictly equal in length, and the length error is controlled within +/-10 mils.

In a high-speed PCB, relatively serious crosstalk occurs between signal lines due to a high signal frequency. When the center distance between the wires is not less than 3 times of the line width, 70% of the electric fields are not influenced by each other. In order to reduce crosstalk between signal lines, the center distance between signal lines is not less than 3 times of the line width during wiring. Utility model's DDR3 signal line length control is within 820mil because it is shorter to walk the line distance, can ignore the problem of impedance match.

As shown in fig. 5, in order to improve the stability of the DDR3 power supply, a decoupling capacitor needs to be provided: a100 nF capacitor is placed on each power pin, and at least a 10uF capacitor is placed on the power line beside the DDR 3.

The utility model discloses a circuit schematic diagram of SD card is shown in FIG. 6, in the design of Micro SD card circuit, signal line except the clock line all will add the stability of drawing resistance in order to ensure data signal, chooses the great resistance of resistance for use as pull-up resistance can reduce hardware system's consumption, but considers the purchase convenience of different resistance, and this design chooses the resistance of common 47K resistance for use.

The clock frequency of the Micro SD card during working can reach 208MHz at most, so the signal lines of the Micro SD card need to be subjected to equal length processing, the equal length is carried out by taking the signal line with the longest length as a reference, the length error of each signal line is controlled within +/-300 mils, and the distance between the signal lines conforms to the line width of which the center distance between the leads is not less than 3 times.

The general purpose LCD controller of a13 supports serial, parallel RGB565, RGB666 format video signal interface outputs. In order to obtain the best image display effect, an RGB666 format video signal output mode is selected, a hardware interface is designed to be a 40-pin LCD-RGB interface, a 40-pin FPC packaged connector (a down-connection mode) is used, and R0, R1, G0, G1, B0 and B1 data lines are not used for direct grounding processing of the interfaces. The interface schematic of the LCD display is shown in fig. 7.

In order to facilitate the direct use of the LCD screen, a backlight booster circuit is designed on the panel for driving the LCD screen, and the CPU can control the brightness of the LCD screen through PWM. The schematic diagram of the LCD backlight booster circuit is shown in FIG. 8.

The model of the universal CMOS camera is OV7670, A13 universal CMOS camera interface (CSI), which is suitable for controlling the CMOS camera, and the interface supports at most 8-bit parallel input data. The OV7670 camera module is common, is easy to purchase in the market and has low price. The pin definition of the OV7670 module is used as the pin definition of the interface, and the interface uses a 24-pin FPC package connector (a down connection mode). The 1.8V voltage, 2.8V voltage for the OV7670 set of modules is provided by the CPU configuration AXP209 output. A schematic diagram of a general CMOS camera interface circuit is shown in fig. 9.

The audio interface module is an earphone socket. A13 built-in audio codec, with 24 bit A/D converter, available recording and audio decoding output; support 44.1K, 48K, 96K, 192K audio sample rates; digital and analog volume output control is supported. Fig. 10 is a schematic diagram of an audio interface circuit. The A13 audio interface is led out by using a headset socket, and a headset can be directly used. The audio (microphone) input is filtered by using an RC passive low-pass filter circuit, and is used for filtering the interference of high-frequency noise.

The USB interface module comprises a USB-HOST interface used as HOST equipment and a USB-OTG interface used as HOST equipment and a debugging interface, the USB-HOST interface is connected with the microprocessor, and the USB-OTG interface is connected with the power management chip through the overcurrent protection chip.

The USB-OTG interface can be connected to a computer to serve as a debugging interface of an Android application program, and can also be connected with external equipment (a U disk, a keyboard, a USB camera and the like) to expand functions of the hardware system. It should be noted here that when the USB-OTG interface is used as a host, if the external device is short-circuited, the current output by the USB-OTG interface is too large, which may cause damage to the power system on the board. Therefore, an overcurrent protection chip SY6280 is added between the VCC power end of the USB-OTG interface and the 5V power supply to perform current-limiting protection on the power supply system. The schematic diagram of the USB-OTG interface circuit is shown in FIG. 11.

The USB-HOST interface can only be used as a HOST device, and can be used to connect to the WiFi & BT module to implement wireless network communication, and fig. 12 is a schematic circuit diagram of the interface circuit of the WiFi & BT module. Preferably, the model of the WiFi & BT module is RTL8723 BU.

When the WiFi & BT module is not used, the USB female socket may be welded, and at this time, the USB female socket may also be used to connect external devices such as a USB disk, a keyboard, and a USB camera, and fig. 13 is a schematic circuit diagram of the USB-HOST interface connected to the USB female socket.

A13 has more idle GPIO ports after connecting the peripheral, which can be classified and led out by pin header for convenient use. Fig. 14 is a schematic diagram of a GPIO port leading out.

The utility model discloses a general CMOS camera gathers license plate image and sends microprocessor discernment to, then through LCD display screen output, whole integrated level is high, and is with low costs, small.

The above is only a preferred embodiment of the present invention, and it should be noted that for those skilled in the art, without departing from the structure of the present invention, several modifications and improvements can be made, which will not affect the utility of the invention and the utility of the patent.

Claims (10)

1. An image recognition device is characterized by comprising a microprocessor, a power management chip, a DDR3 internal memory, an SD card, an LCD display screen, an audio interface module, a USB interface module and a universal CMOS camera in UVC format, wherein the microprocessor is respectively connected with the power management chip, the DDR3 internal memory, the SD card, the LCD display screen, the universal CMOS camera, the audio interface module and the USB interface module.

2. An image recognition apparatus according to claim 1, wherein the microprocessor is of the type Allwinner-a 13.

3. The image recognition device of claim 1, wherein the power management chip has a model number AXP 209.

4. The image recognition device according to claim 1, wherein the model of the universal CMOS camera is OV 7670.

5. The image recognition device of claim 1, wherein the audio interface module is a headphone jack.

6. The image recognition device of claim 1, wherein the USB interface module comprises a USB-HOST interface for use as a HOST device, and a USB-OTG interface for use as a HOST device and a debugging interface, the USB-HOST interface is connected to the microprocessor, and the USB-OTG interface is connected to the power management chip through an over-current protection chip.

7. The image recognition device of claim 6, wherein the over-current protection chip has a model number of SY 6280.

8. An image recognition apparatus according to claim 6, wherein a WiFi & BT module is connected to the USB-HOST interface.

9. An image recognition apparatus according to claim 8, wherein the WiFi & BT module is model number RTL8723 BU.

10. An image recognition apparatus according to claim 1, further comprising a human input device connected to said microprocessor.

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