CN213023465U - High-speed switch circuit and test equipment for switch transient interruption - Google Patents

High-speed switch circuit and test equipment for switch transient interruption Download PDF

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CN213023465U
CN213023465U CN202021627319.4U CN202021627319U CN213023465U CN 213023465 U CN213023465 U CN 213023465U CN 202021627319 U CN202021627319 U CN 202021627319U CN 213023465 U CN213023465 U CN 213023465U
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capacitor
resistor
circuit
terminal
speed switch
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欧冉冉
王绎维
李斌
轩庆红
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Vkan Certification And Testing Co ltd
Guangjiayuan Weikai Shanghai Testing Technology Co ltd
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Vkan Certification And Testing Co ltd
Guangjiayuan Weikai Shanghai Testing Technology Co ltd
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Abstract

The utility model discloses a high-speed switch circuit and test equipment for switch transient interruption, wherein the circuit comprises a drive circuit, a level conversion circuit, a voltage input end filter circuit and a triode end filter circuit, and the level conversion circuit is connected with the input end of an external drive signal of the drive circuit; the voltage input end filter circuit is connected with the voltage input end of the drive circuit; the triode end filter circuit is connected with the collector of an NPN type triode Q2 of the drive circuit. The utility model discloses increased parallelly connected filter circuit in drive circuit's input and triode's position respectively, can effectively restrain the waveform of overshooting, improve output waveform speed, make output waveform reach basically and do not have the overshoot.

Description

High-speed switch circuit and test equipment for switch transient interruption
Technical Field
The utility model belongs to the test technology of switch transient state interrupt, concretely relates to high-speed switch circuit and test equipment of switch transient state interrupt.
Background
The switch is divided into disconnection and connection in general meaning, and the switch is difficult to avoid the bounce in the closed moment, and the switch bounce can cause short-time power supply interruption in the circuit, can cause certain influence to equipment. To detect possible failure due to switch bounce, a set of devices is required that can achieve switching speeds of less than 200 nanoseconds.
The price of the test equipment which can reach the switching speed in the market is generally expensive, and the equipment is generally integrated in larger equipment due to the requirement of higher integration level, for example, some large-scale electrical property equipment can be tested only by adding a corresponding test module, so the equipment is generally large in size and inconvenient to move.
How to provide a test device with high switching speed, high integration level and miniaturization is a problem which needs to be solved urgently.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at provides a high-speed switch circuit, is reaching switching speed and is being less than the reduce cost under the condition of 200 nanoseconds to overcome prior art's not enough.
For realizing the purpose of the utility model, the utility model discloses a technical scheme include: a high-speed switch circuit comprises a drive circuit, a level conversion circuit, a voltage input end filter circuit and a triode end filter circuit,
the driving circuit comprises an NPN type triode Q2, an NMOS tube Q3, a voltage stabilizing diode D2, a capacitor C4, a resistor R6, a resistor R1, a resistor R5 and a resistor R3, wherein the grid electrode of the NMOS tube Q3 is connected with one end of a resistor R5, the other end of the resistor R5 is an input end of an external driving signal, the source electrode of the NMOS tube Q3 is grounded, and the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R1; a base electrode of the NPN type triode Q2 is connected with a drain electrode of the NMOS transistor Q3 through a capacitor C4, a collector electrode of the NPN type triode Q2 is connected with a voltage input end of an external power supply and a source electrode of the PMOS transistor Q1 to be driven, an emitter electrode of the NPN type triode Q2 is connected with the other end of the resistor R1 and a gate electrode of the PMOS transistor Q1 to be driven, and a drain electrode of the PMOS transistor Q1 to be driven is a voltage output end; the resistor R6 is connected in parallel between the collector and the emitter of the NPN type triode Q2, and the resistor R3 is connected in parallel between the gate and the source of the NMOS transistor Q3; the anode of the voltage-stabilizing diode D2 is connected with the emitter of the NPN type triode Q2, and the cathode of the voltage-stabilizing diode D2 is connected with the base of the NPN type triode Q2;
the level conversion circuit is connected with the input end of the external driving signal;
the voltage input end filter circuit is connected with the voltage input end;
the triode end filter circuit is connected with the collector of the NPN type triode Q2.
In a preferred embodiment, the level shift circuit includes an isolated gate driver U1, an IDC connector CN1, a barrier terminal U2, a capacitor C3, a capacitor C7, a capacitor C9 and a capacitor C12, the IDC connector CN1 is connected to an input terminal of the isolated gate driver U1, one end of the capacitor C12 is connected to the input terminal of the isolated gate driver U1, the other end of the capacitor C12 is connected to ground, an output terminal of the isolated gate driver U1 is connected to the input terminal of the external driving signal, one end of the capacitor C3 is connected to the output terminal of the isolated gate driver U1, the other end of the capacitor C9 is connected to ground, the capacitor C7 is connected in parallel, and one end of the capacitor C9 and the capacitor C7 is connected to the input voltage terminal of the isolated gate driver U1 and one port 1 of the barrier terminal U2, and the other end of the barrier terminal U2 is connected.
In a preferred embodiment, the voltage input end filter circuit includes a fence type connection terminal U3, a polarity capacitor C11, a polarity capacitor C6 and a capacitor C5, a port 2 of the fence type connection terminal U3 is grounded, the polarity capacitor C11, the polarity capacitor C6 and the capacitor C5 are connected in parallel, the anodes of the three are all connected to a port 1 of the fence type connection terminal U3 and the voltage input end, and the cathodes of the three are all grounded.
In a preferred embodiment, the triode end filter circuit comprises a polar capacitor C10 and a capacitor C1, wherein the anode of the polar capacitor C10 is connected with the collector of the NPN type triode Q2, the cathode is grounded, one end of the capacitor C1 is connected with the anode of the polar capacitor C10, and the other end is connected with the cathode of the polar capacitor C10.
In a preferred embodiment, the driving circuit further includes a zener diode D3, an anode of the zener diode D3 is connected to the drain of the NMOS transistor Q3, and a cathode of the zener diode D3 is connected to the emitter of the NPN transistor Q2.
In a preferred embodiment, the circuit further includes a barrier terminal U4 and a resistor R2, a port 1 of the barrier terminal U4 is connected to the voltage output terminal, one end of the resistor R2 is connected to the voltage output terminal, and the other end of the resistor R2 and a port 2 of the barrier terminal U4 are both grounded.
Another object of the utility model is to provide a test equipment of switch transient state interrupt also realizes the volume miniaturization when realizing that the integrated level is high.
For realizing the purpose of the utility model, the utility model discloses a technical scheme include: the utility model provides a test equipment of switch transient state interrupt, includes host computer PC, the FPGA system board that links to each other with host computer PC and with the high-speed switchboard that FPGA system board links to each other, the high-speed switchboard with voltage input end and voltage output end link to each other, the high-speed switchboard includes above-mentioned high-speed switch circuit.
In a preferred embodiment, the PC of the upper computer, the FPGA system board and the high-speed switch board are all modularized and are all detachable.
In a preferred embodiment, the rising edge and the falling edge of the high-speed switch plate are switched on and off at a high speed within 200 nanoseconds.
In a preferred embodiment, the PC of the upper computer, the FPGA system board and the high-speed switch board are arranged in a metal box.
Compared with the prior art, the beneficial effects of the utility model reside in at least:
1. the utility model discloses increased parallelly connected filter circuit in drive circuit's input and triode's position respectively, can effectively restrain the waveform of overshooting, improve output waveform speed, make output waveform reach basically and do not have the overshoot. Just the utility model discloses also can reach the high-speed break-make switching speed within 200 nanoseconds of rising edge and falling edge, satisfy the test requirement, reduce cost.
2. By using the modular design, all modules are installed in a small metal box, so that the integrated level is high, the volume is small, the weight is light, the carrying is convenient, and the test is convenient.
3. Because this test equipment is small, light in weight, so can be very lightly with this equipment remove to the incubator by, realize respectively the test under low temperature, normal atmospheric temperature, high temperature environment, improve efficiency of software testing.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a high speed switching circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of a testing device for switching transient interrupts according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a waveform output by the testing apparatus of the present invention.
Detailed Description
The present invention will be more fully understood from the following detailed description, which should be read in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed embodiment.
The utility model discloses a high speed switch circuit and test equipment of switch transient state interrupt, high speed switch circuit can realize 100kHz, and the high-speed break-make within 200 nanoseconds of rising edge and falling edge, test equipment pass through the modularized design, have equipment cost low, and is small, light in weight, advantages such as convenient to use.
As shown in fig. 1, the embodiment of the present invention discloses a high-speed switching circuit, which includes a driving circuit, a level converting circuit, a voltage input end filter circuit and a triode end filter circuit, wherein the level converting circuit is connected to an input end of an external driving signal of the driving circuit, and is used for providing 0-5V high-low level conversion; and the voltage input end filter circuit is connected with the voltage input end of an external power supply of the driving circuit.
The driving circuit specifically comprises an NPN type triode Q2, an NMOS tube Q3, a voltage stabilizing diode D2, a capacitor C4, a resistor R6, a resistor R1, a resistor R5 and a resistor R3, wherein the grid electrode of the NMOS tube Q3 is connected with one end of a resistor R5, the other end of the resistor R5 is an input end of an external driving signal, the source electrode of the NMOS tube Q3 is grounded, and the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R1; a base electrode of the NPN type triode Q2 is connected with a drain electrode of the NMOS transistor Q3 through a capacitor C4, a collector electrode of the NPN type triode Q2 is connected with a voltage input end of an external power supply and a source electrode of the PMOS transistor Q1 to be driven, an emitter electrode of the NPN type triode Q2 is connected with the other end of the resistor R1 and a gate electrode of the PMOS transistor Q1 to be driven, and a drain electrode of the PMOS transistor Q1 to be driven is a voltage output end; the resistor R6 is connected in parallel between the collector and the emitter of the NPN type triode Q2, and the resistor R3 is connected in parallel between the gate and the source of the NMOS transistor Q3; the anode of the zener diode D2 is connected to the emitter of the NPN transistor Q2, and the cathode of the zener diode D2 is connected to the base of the NPN transistor Q2.
Preferably, the driving circuit further includes a zener diode D3, an anode of the zener diode D3 is connected to the drain of the NMOS transistor Q3, and a cathode of the zener diode D3 is connected to the emitter of the NPN transistor Q2.
The level conversion circuit specifically comprises an isolated gate driver U1, an IDC connector CN1, a fence type wiring terminal U2, a capacitor C3, a capacitor C7, a capacitor C9 and a capacitor C12, wherein the IDC connector CN1 is connected with an input end of the isolated gate driver U1, one end of the capacitor C12 is connected with an input end of the isolated gate driver U1, the other end of the capacitor C12 is grounded, an output end of the isolated gate driver U1 is connected with an input end of an external driving signal, one end of the capacitor C3 is connected with an output end of the isolated gate driver U1, the other end of the capacitor C9 is grounded, the capacitor C9 is connected with the capacitor C7 in parallel, and one end of the capacitor C is connected with an input voltage end of the isolated gate driver U1 and one port 1 of the fence type wiring terminal U2, and the other end of the other port 2 of the fence. In this embodiment, the isolated gate driver U1 is model IR4427SPBF, the IDC connector CN1 is model 300S-40P, and the fence terminal U2 is model DBT 30C-9.5-2P. The isolated gate driver U1, model IR4427SPBF, is a MOS transistor or IGBT high speed driver chip that is capable of boosting the voltage at the input terminal (e.g., here the INB terminal) to the voltage at the input voltage terminal (i.e., here the Vs terminal). When the FPGA system board outputs a high level of 3.3V, the output end (namely OUTB pin) of the IR4427 chip supplies voltage to the VS end, and when the output of the FPGA system board is 0V low, the OUTB end outputs 0V, namely, the function of converting the high and low levels into analog quantity for output is achieved.
The voltage input end filter circuit specifically comprises a fence type wiring terminal U3, a polar capacitor C11, a polar capacitor C6 and a capacitor C5, wherein a port 2 of the fence type wiring terminal U3 is grounded, the polar capacitor C11, the polar capacitor C6 and the capacitor C5 are connected in parallel, the anodes of the three are connected with a port 1 of the fence type wiring terminal U3 and the voltage input end, and the cathodes of the three are grounded. In the embodiment, the type of the fence type wiring terminal U3 is DBT 30C-9.5-2P.
The triode end filter circuit is connected with a collector of an NPN type triode Q2 of the driving circuit and specifically comprises a polar capacitor C10 and a capacitor C1, wherein the positive electrode of the polar capacitor C10 is connected with the collector of the NPN type triode Q2, the negative electrode of the polar capacitor C10 is grounded, one end of the capacitor C1 is connected with the positive electrode of the polar capacitor C10, and the other end of the capacitor C1 is connected with the negative electrode of the polar capacitor C10.
The voltage input end filter circuit and the pole tube end filter circuit can filter out alternating current components mixed in direct current by utilizing the working characteristics of the capacitor, namely filtering, the alternating current components return to a power supply through the capacitor after filtering, and pure direct current without fluctuation is left on two sides of the capacitor.
Further, the high-speed switch circuit further comprises a fence type wiring terminal U4 and a resistor R2, a port 1 of the fence type wiring terminal U4 is connected with the voltage output end, one end of the resistor R2 is connected with the voltage output end, and the other end of the resistor R2 and a port 2 of the fence type wiring terminal U4 are both grounded. In the embodiment, the type of the fence type wiring terminal U4 is DBT 30C-9.5-2P.
The utility model discloses a theory of operation specifically does: when the level switching circuit outputs a high level, the NMOS transistor Q3 is in saturation conduction, and after the input voltage is filtered by the voltage input end filter circuit, the input voltage not only charges the parasitic capacitor of the PMOS transistor Q1 to be driven through the resistor R1 and the NMOS transistor Q3 branch, but also quickly charges the parasitic capacitor through the zener diode D2, the capacitor C4 and the NMOS transistor Q3 branch. Therefore, the voltage across the parasitic capacitor rises rapidly, and the PMOS transistor Q1 is turned on; when the level conversion circuit outputs a low level, the NMOS transistor Q3 is turned off, and the shunt capacitor C4 discharges to provide a base driving current for the NPN transistor Q2, so that the NPN transistor Q2 is saturated and turned on, and at the same time, the resistor R6 is short-circuited, and the parasitic capacitor discharges rapidly, so that the PMOS transistor Q1 is turned off rapidly.
As shown in fig. 2, the testing apparatus for switching transient interruption disclosed in the embodiment of the present invention includes an upper computer PC, an FPGA system board and a high-speed switch board, wherein the FPGA system board is connected to the upper computer PC for generating a driving waveform under the control of the upper computer PC; and the high-speed switch board is connected with the FPGA system board and is used for realizing high-speed on-off within 200 nanoseconds of rising edge and falling edge. The high-speed switch board comprises the high-speed switch circuit, and the high-speed switch board is connected with a voltage input end and a voltage output end in the high-speed switch circuit.
Preferably, the upper computer PC, the FPGA system board and the high-speed switch board are all in detachable modular design, and all modules are installed in a small metal box (not shown), so that the device is small in size, light in weight, convenient to carry, and convenient to test, produce and maintain.
And, the utility model discloses a test equipment's break-make speed is very fast, utilizes the characteristic of electric capacity charge-discharge to improve rising edge and falling edge, consequently can bring great overshoot, so the position of input and triode has increased parallelly connected filter capacitor respectively again, and the effect is showing, can effectively restrain the waveform of overshooting, improves output waveform speed. As shown in FIG. 3, the square wave frequency is 100kHz, and the output waveform speed is high after the filter circuit is added, so that the overshoot is basically avoided.
Because this test equipment is small, light in weight, so can be very lightly with this equipment remove to the incubator by, be convenient for realize respectively in low temperature, normal atmospheric temperature, test under the high temperature environment, improve efficiency of software testing.
The embodiment of the utility model provides a disclosed test equipment of switch transient state interrupt is equivalent to a high-speed switch, can play on-off control to automobile storage battery's positive pole, is 100kHz at development frequency, and when using 13.5V's voltage break-make, the rising edge and the falling edge of break-make are less than 200 nanoseconds.
The aspects, embodiments, features and examples of the present invention should be considered illustrative in all respects and not intended to be limiting, the scope of the invention being defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.
The use of titles and chapters in the utility model is not meant to limit the utility model; each section may apply to any aspect, embodiment, or feature of the present invention.
Unless specifically stated otherwise, use of the terms "comprising", "including", "having" or "having" is generally to be understood as open-ended and not limiting.
While the invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions and/or additions may be made and substantial equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims (10)

1. A high-speed switch circuit is characterized in that the circuit comprises a driving circuit, a level conversion circuit, a voltage input end filter circuit and a triode end filter circuit,
the driving circuit comprises an NPN type triode Q2, an NMOS tube Q3, a voltage stabilizing diode D2, a capacitor C4, a resistor R6, a resistor R1, a resistor R5 and a resistor R3, wherein the grid electrode of the NMOS tube Q3 is connected with one end of a resistor R5, the other end of the resistor R5 is an input end of an external driving signal, the source electrode of the NMOS tube Q3 is grounded, and the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R1; a base electrode of the NPN type triode Q2 is connected with a drain electrode of the NMOS transistor Q3 through a capacitor C4, a collector electrode of the NPN type triode Q2 is connected with a voltage input end of an external power supply and a source electrode of the PMOS transistor Q1 to be driven, an emitter electrode of the NPN type triode Q2 is connected with the other end of the resistor R1 and a gate electrode of the PMOS transistor Q1 to be driven, and a drain electrode of the PMOS transistor Q1 to be driven is a voltage output end; the resistor R6 is connected in parallel between the collector and the emitter of the NPN type triode Q2, and the resistor R3 is connected in parallel between the gate and the source of the NMOS transistor Q3; the anode of the voltage-stabilizing diode D2 is connected with the emitter of the NPN type triode Q2, and the cathode of the voltage-stabilizing diode D2 is connected with the base of the NPN type triode Q2;
the level conversion circuit is connected with the input end of the external driving signal;
the voltage input end filter circuit is connected with the voltage input end;
the triode end filter circuit is connected with the collector of the NPN type triode Q2.
2. The high speed switching circuit of claim 1, wherein the level shifting circuit comprises an isolated gate driver U1, an IDC connector CN1, a fence wire terminal U2, a capacitor C3, a capacitor C7, a capacitor C9, and a capacitor C12, the IDC connector CN1 is connected to the input terminal of the isolated gate driver U1, one end of the capacitor C12 is connected to the input terminal of the isolated gate driver U1, the other end is grounded, the output terminal of the isolated gate driver U1 is connected to the input terminal of the external driving signal, one end of the capacitor C3 is connected with the output end of the isolated gate driver U1, the other end is grounded, the capacitor C9 is connected with the capacitor C7 in parallel, one end of the isolation gate driver U1 and the other end of the isolation gate driver U1 are connected to one port 1 of the barrier terminal U2, and the other end of the isolation gate driver U1 and the other port 2 of the barrier terminal U2 are connected to ground.
3. The high-speed switch circuit according to claim 1, wherein the voltage input end filter circuit comprises a fence terminal U3, a polarity capacitor C11, a polarity capacitor C6 and a capacitor C5, a port 2 of the fence terminal U3 is grounded, the polarity capacitor C11, the polarity capacitor C6 and the capacitor C5 are connected in parallel, the anodes of the three are connected with a port 1 of the fence terminal U3 and the voltage input end, and the cathodes of the three are grounded.
4. The high-speed switch circuit according to claim 1, wherein the triode end filter circuit comprises a polar capacitor C10 and a capacitor C1, the anode of the polar capacitor C10 is connected to the collector of an NPN type triode Q2, the cathode is grounded, one end of the capacitor C1 is connected to the anode of a polar capacitor C10, and the other end is connected to the cathode of a polar capacitor C10.
5. The high-speed switch circuit according to claim 1, wherein the driving circuit further comprises a zener diode D3, an anode of the zener diode D3 is connected to the drain of the NMOS transistor Q3, and a cathode of the zener diode D3 is connected to the emitter of the NPN transistor Q2.
6. The high-speed switch circuit according to claim 1, further comprising a barrier terminal U4 and a resistor R2, wherein the port 1 of the barrier terminal U4 is connected to the voltage output terminal, one end of the resistor R2 is connected to the voltage output terminal, and the other end of the resistor R2 and the port 2 of the barrier terminal U4 are both grounded.
7. A test device for switch transient interruption, which is characterized by comprising an upper computer PC, an FPGA system board connected with the upper computer PC and a high-speed switch board connected with the FPGA system board, wherein the high-speed switch board is connected with a voltage input end and a voltage output end and comprises the high-speed switch circuit as claimed in any one of claims 1 to 6.
8. The apparatus of claim 7, wherein the PC, the FPGA system board and the high-speed switch board are all modular and are all detachable.
9. The apparatus for testing for switching transient interruption of claim 7, wherein said high speed switch plate is turned on and off at a high speed within 200 nanoseconds of its rising and falling edges.
10. The apparatus of claim 7, wherein the host PC, FPGA system board and high speed switch board are mounted in a metal box.
CN202021627319.4U 2020-08-07 2020-08-07 High-speed switch circuit and test equipment for switch transient interruption Active CN213023465U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202021627319.4U CN213023465U (en) 2020-08-07 2020-08-07 High-speed switch circuit and test equipment for switch transient interruption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202021627319.4U CN213023465U (en) 2020-08-07 2020-08-07 High-speed switch circuit and test equipment for switch transient interruption

Publications (1)

Publication Number Publication Date
CN213023465U true CN213023465U (en) 2021-04-20

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CN202021627319.4U Active CN213023465U (en) 2020-08-07 2020-08-07 High-speed switch circuit and test equipment for switch transient interruption

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