CN212967754U

CN212967754U - Display device and display panel

Info

Publication number: CN212967754U
Application number: CN202022098481.8U
Authority: CN
Inventors: 张子予; 孙韬; 王涛
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-09-22
Filing date: 2020-09-22
Publication date: 2021-04-13
Anticipated expiration: 2030-09-22

Abstract

The disclosure relates to a display device and a display panel, and relates to the technical field of display. The display panel comprises a substrate, a driving layer, a light-emitting device layer, a first blocking dam, a plurality of drainage strips and a packaging layer, wherein the driving layer is arranged on one side of the substrate and is provided with a pixel circuit area, a peripheral circuit area and a marginal area; the light-emitting device layer is arranged on one side of the pixel circuit region, which is far away from the substrate; the first blocking dam is arranged at the edge region and surrounds the peripheral circuit region; the drainage strips are arranged on one side of the edge region, which is far away from the substrate, and are positioned in the first blocking dam, and each drainage strip extends to the peripheral circuit region from the edge region; the packaging layer comprises a first inorganic layer, an organic layer and a second inorganic layer, the first inorganic layer covers the light-emitting device layer, the first blocking dam and the drainage strip, and the first inorganic layer protrudes in the area corresponding to the first blocking dam and the drainage strip; the organic layer is arranged on the surface of the first inorganic layer, which is far away from the substrate, and is limited in the range surrounded by the first barrier dam; the second inorganic layer covers the organic layer and the first inorganic layer.

Description

Display device and display panel

Technical Field

The disclosure relates to the technical field of display, in particular to a display device and a display panel.

Background

In an OLED (Organic Light-Emitting Diode) display panel, a Thin-Film Encapsulation (TFE) process is generally used for Encapsulation. However, the optical uniformity of the packaging layer of the conventional display panel is low, and the water and oxygen blocking effect still needs to be improved.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a display device and a display panel, which can improve optical uniformity and reduce the risk of package failure.

According to an aspect of the present disclosure, there is provided a display panel including:

a substrate;

the driving layer is arranged on one side of the substrate and is provided with a pixel circuit area, a peripheral circuit area surrounding the pixel circuit area and an edge area surrounding the peripheral circuit area;

the light-emitting device layer is arranged on one side of the pixel circuit region, which is far away from the substrate;

the first blocking dam is arranged on one side, away from the substrate, of the edge region, and the first blocking dam is of a ring-shaped structure surrounding the peripheral circuit region;

the plurality of drainage strips are arranged on one side of the edge region, which is far away from the substrate, and are positioned in the range surrounded by the first blocking dam; the drainage strips are distributed at intervals, and each drainage strip extends from the edge area to the peripheral circuit area;

an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer, the first inorganic layer covering the light emitting device layer, the first blocking dam, and the drainage strip, and protruding in a region corresponding to the first blocking dam and the drainage strip; the organic layer is arranged on the surface of the first inorganic layer, which faces away from the substrate, and is limited within the range surrounded by the first barrier dam; the second inorganic layer covers the organic layer and the first inorganic layer.

In an exemplary embodiment of the present disclosure, the drainage strip is connected with an inner sidewall of the first blocking dam; in a direction perpendicular to the substrate, a thickness of the flow guide strips is smaller than a thickness of the first dam.

In an exemplary embodiment of the present disclosure, the first barrier dam includes a first layer and a second layer stacked in this order in a direction away from the substrate, an inner sidewall of the second layer surrounding outside an inner sidewall of the first layer; the drainage strip is connected with the first layer and is made of the same material.

In an exemplary embodiment of the present disclosure, a gap is provided between an inner sidewall of the first blocking dam and the drainage strip.

In an exemplary embodiment of the present disclosure, an orthographic projection of the edge region on the substrate is a polygon, and the edge region includes a plurality of side regions and arc regions, and two adjacent side regions are transitionally connected by one of the arc regions;

the width of the drainage strip positioned in the arc-shaped area is increased towards the direction far away from the pixel circuit area.

In an exemplary embodiment of the present disclosure, the driving layer includes:

the active layer is arranged on one side of the substrate and is positioned in the pixel circuit area and the peripheral circuit area;

the first grid insulating layer covers the active layer and is positioned in the pixel circuit area, the peripheral circuit area and the edge area;

the grid layer is arranged on the surface, away from the substrate, of the first grid insulating layer and is positioned in the pixel circuit area and the peripheral circuit area;

a second gate insulating layer covering the gate layer and the first gate insulating layer and located in the pixel circuit region, the peripheral circuit region and the edge region;

a dielectric layer covering the second gate insulating layer and located in the pixel circuit region, the peripheral circuit region and the edge region;

the source drain layer is arranged on the surface, deviating from the substrate, of the dielectric layer and is positioned in the pixel circuit area and the peripheral circuit area;

the flat layer covers the source drain layer and the dielectric layer and is positioned in the pixel circuit area and the peripheral circuit area;

the power line is arranged on the surface, deviating from the substrate, of the dielectric layer and is positioned in the edge area, and the material and the thickness of the power line and the thickness of the source drain layer are the same;

the first blocking dam and the drainage strip cover at least a partial region of the power supply line.

In one exemplary embodiment of the present disclosure, the light emitting device layer includes:

the first electrode layer is arranged on the surface, away from the substrate, of the flat layer and is positioned in the pixel circuit area, and the first electrode layer comprises a plurality of first electrodes distributed in an array manner;

a pixel defining layer covering the first electrode layer and the planarization layer and exposing each of the first electrodes;

a light-emitting functional layer at least covering the surface of the first electrode facing away from the substrate;

a second electrode layer covering the light emitting function layer;

the display panel further includes:

the lapping layer is arranged on the surface, away from the substrate, of the flat layer and extends to the surface, away from the substrate, of the power line, and a plurality of exhaust holes distributed in an array are formed in the area, corresponding to the flat layer, of the lapping layer; the materials and the thicknesses of the lapping layer and the first electrode layer are the same;

the protective layer is arranged on the surface of the lapping layer, which is far away from the substrate, covers the exhaust hole and exposes a partial area of the lapping layer; the protective layer and the drainage strip are made of the same material and have the same thickness;

the drainage strip is positioned on one side of the protective layer, which is far away from the pixel circuit area, and covers a partial area of the lap joint layer, which corresponds to the power line;

the second electrode layer extends to the edge region to the surface of the protective layer, which is far away from the substrate, and is connected with the lap joint layer.

In an exemplary embodiment of the present disclosure, the protective layer includes a plurality of protective strips, and the vent holes are distributed in an area of the overlapping layer covered by the protective strips; and the protection strips are butted with the drainage strips in a one-to-one correspondence manner.

In an exemplary embodiment of the present disclosure, the display panel further includes:

the supporting column is arranged on the surface, away from the substrate, of the pixel defining layer;

one of the support posts and the pixel defining layer is the same material as the drainage strips.

the second blocks the dam, locates the marginal zone deviates from one side of substrate, and set up around first blocking the dam, first inorganic layer covers the second blocks the dam.

In an exemplary embodiment of the present disclosure, a distance between the inner sidewall of the second layer and the inner sidewall of the first layer is not less than 3 μm.

In an exemplary embodiment of the present disclosure, a width of a gap between the drainage strip and the inner sidewall of the first blocking dam is 3 μm to 30 μm.

In an exemplary embodiment of the present disclosure, the length of the drainage strip is 50 μm to 500 μm, and the width of the drainage strip is 5 μm to 50 μm; the distance between two adjacent drainage strips is 5-100 mu m.

In an exemplary embodiment of the present disclosure, each of the drainage strips is spaced along a circular trajectory.

According to an aspect of the present disclosure, there is provided a display device including the display panel of any one of the above.

According to the display device and the display panel, the drainage strip extending from the edge region to the peripheral circuit region is arranged on the inner side of the first barrier layer, and the first inorganic layer protrudes in the region corresponding to the first barrier dam and the drainage strip; when the organic layer is formed, the protrusions corresponding to the drainage strips break the equilibrium state of the surface tension of the liquid organic material, and under the action of the capillary effect, the organic material diffuses toward the first blocking dam along the protrusions corresponding to the drainage strips until being blocked by the protrusions corresponding to the first blocking dam. The problem of insufficient coverage or overflow (crossing the first blocking dam) of the organic material caused by the fact that the flow leveling boundary of the organic material cannot be accurately controlled can be prevented; insufficient coverage of the organic material in the edge region easily causes accumulation of the organic material in a peripheral circuit region or a pixel circuit region, increases the risk of subsequent processes, and causes insufficient light-emitting uniformity; overflow of the organic material can expose the organic material to external water oxygen, resulting in package failure. In conclusion, the display panel can improve the uniformity of light emission, reduce the process risk and prevent the package from losing efficacy.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a package of a display panel in the related art.

Fig. 2 is a partial cross-sectional view of an organic material distribution of an encapsulation layer of a display panel in the related art.

Fig. 3 is a partial top view of organic material distribution of an encapsulation layer of a display panel according to the related art.

Fig. 4 is a top view of a display panel of the present disclosure.

Fig. 5 is a cross-sectional view a-a of the display panel of fig. 4.

FIG. 6 is a cross-sectional view taken along line B-B of the display panel shown in FIG. 4.

Fig. 7 is a distribution diagram of a drainage bar corresponding to the embodiment of the display panel in fig. 6.

Fig. 8 is a B-B sectional view of another embodiment of the display panel of fig. 4.

Fig. 9 is a schematic distribution diagram of a drainage bar corresponding to the embodiment of the display panel in fig. 8.

FIG. 10 is a cross-sectional view taken along line B-B of the display panel shown in FIG. 4.

Fig. 11 is a distribution diagram of a drainage bar corresponding to the embodiment of the display panel in fig. 10.

Fig. 12 is a schematic distribution diagram of the drainage strips in the side area and the arc area of the display panel of the present disclosure.

FIG. 13 is a flow chart of one embodiment of a method of manufacturing the present disclosure.

Description of reference numerals:

in fig. 1-3: 001. driving the back plate; 002. a light emitting device layer; 003. a packaging layer; 0031. a first inorganic layer; 0032. an organic layer; 0033. a second inorganic layer; 004. blocking the dam.

In fig. 4-12: 1. a substrate; 2. a drive layer; 201. a pixel circuit region; 202. a peripheral circuit region; 203. an edge region; 2031. a side area; 2032. an arc-shaped area; 21. an active layer; 211. an active portion; 22. a first gate insulating layer; 23. a gate layer; 231. a gate electrode; 24. a second gate insulating layer; 25. a dielectric layer; 26. a source drain layer; 261. a source electrode; 262. a drain electrode; 27. a planarization layer; 28. a power line; 291. a first electrode plate; 292. a second polar plate; 293. a third polar plate; 294. a fourth pole plate; 3. a light emitting device layer; 31. a first electrode layer; 311. a first electrode; 32. a pixel defining layer; 33. a light-emitting functional layer; 331. an organic common layer; 332. a light emitting material layer; 34. a second electrode layer; 4. a first dam; 41. a first layer of a first barrier dam; 42. a second layer of the first barrier dam; 5. a drainage strip; 6. a packaging layer; 61. a first inorganic layer; 62. an organic layer; 63. a second inorganic layer; 7. a lap joint layer; 71. an exhaust hole; 8. a protective layer; 81. a protective strip; 9. a support pillar; 10. a second dam; 101. a first layer of a second barrier dam; 102. a second layer of second barrier dams; 103. a third layer of the second dam; 11. a buffer layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

In the related art, as shown in fig. 1, the OLED display panel may include a driving backplane 001, a photo device layer 002, and an encapsulation layer 003, wherein one side of the driving backplane 001 is provided with a plurality of annular blocking dams 004 arranged concentrically; the light emitting device layer 002 is arranged on the driving back plate 001 and located in the range surrounded by the blocking dam 004, and the light emitting devices in the light emitting device layer 002 can be driven to emit light through a circuit in the driving back plate 001, so that an image is displayed.

The encapsulation layer 003 may include a first inorganic layer 0031, an organic layer 0032, and a second inorganic layer 0033, in which the first inorganic layer 0031 covers the barrier dam 004 and the light-emitting device layer 002, and the organic layer 0032 is provided on a surface of the first inorganic layer 0031 facing away from the driving back plate 001 and is confined within a range surrounded by the barrier dams 004 (the closest one of the barrier dams 004 to the light-emitting device layer 002); the second inorganic layer 0033 covers the organic layer 0032 and the first inorganic layer 0031, so that the organic layer 0032 is wrapped between the first inorganic layer 0031 and the second inorganic layer 0033. The first inorganic layer 0031 and the second inorganic layer 0033 are inorganic materials and can be used for blocking water; and the material of the organic layer 0032 is an organic material, which can play a role in flattening an interface, coating defects and releasing stress.

At the time of encapsulation, an organic material may be formed on the first inorganic layer 0031 through an Ink Jet Printing (IJP) process, and the barrier dam 004 blocks the overflow of the organic material toward the barrier dam 004 to prevent the organic material from contacting with external water and oxygen. In the process, the liquid organic material is free to flow on the first inorganic layer 0031 and affected by local wettability and liquid surface tension fluctuation, the difference of the actual stopping positions of the organic materials in different areas is large, namely the edge linearity is poor; that is, the boundary of the organic layer 0032 of different regions is difficult to match the range defined by the barrier dam 004.

As shown in fig. 2 and 3, the edge of the organic layer 0032 is desirably the region ii, i.e., the inside of the barrier dam 004 is filled with the organic material without overflowing. However, since the actual stopping position of the organic material is difficult to control, problems of insufficient coverage or overflow are likely to occur. Specifically, in fig. 2 and 3, the area with insufficient leveling distance in the area i, that is, the boundary of the organic material does not reach the blocking dam 004, so that a partial area inside the blocking dam 004 is not covered by the organic layer 0032, and the area i is prone to have a large slope, which causes a risk in a subsequent process, and presses the organic material inside to form a protrusion on the light emitting device layer 002, which affects optical uniformity. And the III area is formed by overflowing the organic material out of the blocking dam 004, so that the organic layer 0032 is exposed and easily contacted with water and oxygen, and the packaging is failed.

The present disclosure provides a display panel, which may be an OLED display panel, as shown in fig. 4 to 7, and which may include a substrate 1, a driving layer 2, a light emitting device layer 3, a first blocking dam 4, a drainage bar 5, and an encapsulation layer 6, wherein:

the driving layer 2 is disposed on one side of the substrate 1, and has a pixel circuit region 201, a peripheral circuit region 202 surrounding the pixel circuit region 201, and a peripheral region 203 surrounding the peripheral circuit region 202.

The light emitting device layer 3 is disposed on a side of the pixel circuit region 201 facing away from the substrate 1.

The first blocking dam 4 is disposed on a side of the edge region 203 away from the substrate 1, and the first blocking dam 4 is a ring-shaped structure surrounding the pixel circuit region 201.

A plurality of drainage strips 5 are arranged on one side of the edge region 203, which is far away from the substrate 1, and are positioned in the range surrounded by the first blocking dam 4; the drainage strips 5 are distributed at intervals, and each drainage strip 5 extends from the edge region 203 to the peripheral circuit region 202.

For example, the strips 5 are spaced along a circular path.

The encapsulation layer 6 includes a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63, the first inorganic layer 61 covers the light emitting device layer 3, the first barrier dam 4, and the flow guide strip 5, and is protruded at a region corresponding to the first barrier dam 4 and the flow guide strip 5; the organic layer 62 is provided on the surface of the first inorganic layer 61 facing away from the substrate 1 and is confined within a range surrounded by the first barrier dam 4; the second inorganic layer 63 covers the organic layer 62 and the first inorganic layer 61.

In the display panel according to the embodiment of the present disclosure, when the organic layer 62 is formed, the protrusions corresponding to the drainage bars 5 break the equilibrium state of the surface tension of the liquid organic material, and the organic material is diffused toward the first blocking dam 4 along the protrusions corresponding to the drainage bars 5 until being blocked by the protrusions corresponding to the first blocking dam 4 by the capillary effect, so that the boundary of the organic layer 62 is matched with the range defined by the first blocking dam 4, and the problems of insufficient coverage and overflow (crossing over the first blocking dam 4) of the organic material do not occur. Insufficient coverage of the organic material in the edge region 203 easily causes accumulation of the organic material in the peripheral circuit region 202 or the pixel circuit region 201, increases the risk of subsequent processes, and makes the uniformity of light emission insufficient; overflow of the organic material can expose the organic material to external water oxygen, resulting in package failure. In conclusion, the display panel can improve the uniformity of light emission, reduce the process risk and prevent the package from losing efficacy.

The following describes each part of the display panel according to the embodiment of the present disclosure in detail:

the substrate 1 may be a transparent plate-shaped structure, and the material thereof may be a flexible material such as PI (polyimide), and correspondingly, the display panel is a flexible display panel, and of course, the material of the substrate 1 may also be a hard material such as glass.

The driving layer 2 is disposed on one side of the substrate 1, and in order to prevent impurities in the substrate 1 from affecting the driving layer 2, a buffer layer 11 may be disposed on the substrate 1, and the driving layer 2 is disposed on a surface of the buffer layer 11 away from the substrate 1.

The driving layer 2 has a pixel circuit region 201, a peripheral circuit region 202 surrounding the pixel circuit region 201, and a peripheral region 203 surrounding the peripheral circuit region 202. The pixel circuit is disposed in the pixel circuit area 201, and the specific structure of the pixel circuit is not particularly limited herein as long as the pixel circuit can be used for driving the light emitting device of the light emitting device layer 3 to emit light. A peripheral circuit is provided in the peripheral circuit region 202, and a driving signal can be input to the pixel circuit via the peripheral circuit, so that the light emitting device in the light emitting device layer 3 emits light. The peripheral circuit may include an emission control circuit (EM-GOA), a Gate drive circuit (Gate-GOA), and the like, and the specific configuration of the peripheral circuit is not particularly limited herein.

In some embodiments of the present disclosure, the pixel circuit and the peripheral circuit of the driving layer 2 each include a plurality of thin film transistors, as shown in fig. 5, 6, 8 and 10, only the driving transistor of the pixel circuit is shown in fig. 5, and only one thin film transistor of the light emission control circuit of the peripheral circuit is also shown in fig. 6, 8 and 10. Taking all the tfts as top gate type structures as an example, as shown in fig. 5, the driving layer 2 may include an active layer 21, a first gate insulating layer 22, a gate layer 23, a second gate insulating layer 24, a dielectric layer 25, a source/drain layer 26 and a planarization layer 27 in a direction perpendicular to the driving layer 2, wherein:

the active layer 21 is provided on the substrate 1 side, for example, the active layer 21 is provided on the surface of the buffer layer 11 facing away from the substrate 1. The active layer 21 is made of a semiconductor material such as amorphous silicon, polycrystalline silicon, or metal oxide. The active layer 21 may include a plurality of independent active portions 211, and the active portions 211 are formed in the pixel circuit region 201 and the peripheral circuit region 202 in regions corresponding to the respective thin film transistors.

The first gate insulating layer 22 covers the active layer 21, for example, the active layer 21 and the buffer layer 11 not covered by the active layer 21. Meanwhile, the first gate insulating layer 22 extends to the pixel circuit region 201, the peripheral circuit region 202, and the edge region 203, i.e., an orthographic projection of the first gate insulating layer 22 on the substrate 1 may coincide with a boundary of the substrate 1.

The gate layer 23 may be disposed on a surface of the first gate insulating layer 22 facing away from the substrate 1, and located in the pixel circuit region 201 and the peripheral circuit region 202. The gate layer 23 may include a plurality of independent gate electrodes 231, and the gate electrodes 231 are formed in the pixel circuit region 201 and the peripheral circuit region 202 in regions corresponding to the respective thin film transistors, and the gate electrodes 231 and the active portions 211 of the same thin film transistor are disposed to face each other in a direction perpendicular to the substrate 1.

The second gate insulating layer 24 covers the gate layer 23 and a region of the first gate insulating layer 22 not covered by the gate layer 23. The pixel circuit region 201, the peripheral circuit region 202, and the edge region 203 each have the second gate insulating layer 24, i.e., an orthographic projection of the second gate insulating layer 24 on the substrate 1 may coincide with a boundary of the substrate 1.

The dielectric layer 25 covers the second gate insulating layer 24, and the pixel circuit region 201, the peripheral circuit region 202, and the edge region 203 all have the dielectric layer 25, that is, an orthographic projection of the dielectric layer 25 on the substrate 1 may coincide with a boundary of the substrate 1.

The source and drain layers 26 are disposed on the surface of the dielectric layer 25 away from the substrate 1, the source and drain layers 26 include a plurality of independent sets of source electrodes 261 and drain electrodes 262, a set of source electrodes 261 and drain electrodes 262 are formed in the pixel circuit region 201 and the peripheral circuit region 202 corresponding to the respective thin film transistors, and each set of source electrodes 261 and drain electrodes 262 includes a source electrode 261 and a drain electrode 262. The same thin film transistor includes a set of source electrodes 261 and drain electrodes 262, and the source electrodes 261 and the drain electrodes 262 are connected to both ends of the corresponding active portions 211.

The material of the planarization layer 27 may be an organic insulating material, which may cover the source/drain layer 26 and the area of the dielectric layer 25 not covered by the source/drain layer 26, and the planarization layer 27 is continuously located in the pixel circuit area 201 and the peripheral circuit area 202, and the edge area 203 has at most a portion of the planarization layer 27, that is, the boundary of the planarization layer 27 coincides with the boundary of the peripheral circuit area 202; alternatively, the flat layer 27 boundary may be located within the edge region 203.

Furthermore, as shown in fig. 5 and 6, the driving layer 2 may further include a power line 28, and the power line 28 may be disposed on a surface of the dielectric layer 25 facing away from the substrate 1 and located in the edge region 203, that is, the power line 28 is disposed on a surface of the dielectric layer 25 not covered by the planarization layer 27. The power line 28 and the source and drain layers 26 are made of the same material and have the same thickness, and thus may be formed simultaneously using the same patterning process, which may be a photolithography process. Meanwhile, the power supply line 28 is separated from the peripheral circuits of the peripheral circuit region 202 by a partial region of the planarization layer 27, so that the power supply line 28 is not directly connected to the peripheral circuits.

The planarization layer 27 may also extend into the edge region 203 and cover a partial region of the power supply line 28. The power line 28 may be connected to a driving circuit board bound to the binding region of the edge region 203, and receive a driving signal from the driving circuit board so as to drive the light emitting devices of the light emitting device layer 3 to emit light.

As shown in fig. 5, the pixel circuit of the pixel circuit region 201 may further include a first capacitor including a first electrode plate 291 and a second electrode plate 292, wherein the first electrode plate 291 may be disposed on a surface of the first gate insulating layer 22 facing away from the substrate 1, covered by the second gate insulating layer 24, and has the same material and thickness as the gate layer 21, so that the gate layer 21 and the first electrode plate 291 may be formed simultaneously by a single patterning process. The second plate 292 may be disposed on a surface of the second gate insulating layer 25 facing away from the substrate 1 and covered by the dielectric layer 25.

As shown in fig. 6, 8 and 10, the peripheral circuit of the peripheral circuit region 202 includes a second capacitor, and the second capacitor may include a third plate 293 and a fourth plate 294, wherein the third plate 293 may be disposed on a surface of the first gate insulating layer 22 facing away from the substrate 1, covered by the second gate insulating layer 24, and has the same material and thickness as the gate layer 21, so that the gate layer 21 and the third plate 293 may be formed simultaneously by a single patterning process. The fourth electrode plate 294 may be disposed on a surface of the second gate insulating layer 25 facing away from the substrate 1 and covered by the dielectric layer 25. The fourth electrode plate 294 and the second electrode plate 292 are the same in material and the same in thickness so as to be formed through a single patterning process.

It should be noted that the first capacitor shown in fig. 5 is only a structure illustrating the first capacitor, and does not refer to a specific capacitor in the pixel circuit. The second capacitor in fig. 6, 8 and 10 is merely for illustrating the structure of the second capacitor, and does not refer to a specific capacitor in the peripheral circuit.

As shown in fig. 5, the light emitting device layer 3 may include a plurality of light emitting devices, taking the light emitting devices as OLED light emitting devices as an example, as shown in fig. 5, in some embodiments of the present disclosure, the light emitting device layer 3 may include a first electrode layer 31, a pixel defining layer 32, a light emitting function layer 33, and a second electrode layer 34, wherein:

the first electrode layer 31 is disposed on a surface of the planarization layer 27 away from the substrate 1 and located in the pixel circuit region 201, the first electrode layer 31 includes a plurality of first electrodes 311 distributed in an array, each first electrode 311 can serve as an anode of an OLED light emitting device and can be connected to a pixel circuit in the pixel circuit region 201 so as to receive a signal for driving the light emitting device to emit light. For example, the pixel circuit may include pixel circuit units corresponding to the respective light emitting devices one by one, each pixel circuit unit including a driving transistor having a source electrode 261 or a drain electrode 262 connected to the first electrode 311 of the corresponding light emitting device through a via hole passing through the planarization layer 27.

The pixel defining layer 32 covers the first electrode layer 31 and the planarization layer 27, and the pixel defining layer 32 is provided with a plurality of openings, each of which exposes each of the first electrodes 311 in a one-to-one correspondence, so that the range of each light emitting device can be defined by the pixel defining layer 32.

The light-emitting functional layer 33 covers at least the surface of the first electrode 311 facing away from the substrate 1. For example, it may include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, and an electron injection layer, which are sequentially stacked in a direction away from the substrate 1, wherein the OLED light emitting devices of different colors may share at least the same electron transport layer and the same hole transport layer, while the light emitting material layers of the OLED light emitting devices of different colors are different. Thus, for all OLED light emitting devices, the light emitting functional layer 33 may comprise at least an organic common layer 331 and a light emitting material layer 332, wherein: the organic common layer 331 is used to represent a film layer shared by the OLED light emitting devices, the number of the light emitting material layers 332 is multiple and distributed in an array, and the light emitting material layers 332 are disposed in one-to-one correspondence with the first electrodes 311 to limit the light emitting colors of the OLED light emitting devices.

It should be noted that although the organic common layer 331 in fig. 5 is depicted as a film layer between the first electrode layer 31 and the light emitting material layer 332, it is not intended to indicate a certain film layer actually existing in the light emitting function layer 33, but is intended to indicate all common film layers. If the organic common layer 331 is depicted as a plurality of layers that it actually comprises, for example, the organic common layer 331 includes an electron transport layer and a hole transport layer; the light emitting material layer 332 may be positioned between the electron transport layer and the hole transport layer. That is, the organic common layer 331 and the light emitting material layer 332 in fig. 5 do not constitute a limitation on the lamination relationship of the respective film layers actually existing in the OLED light emitting device.

The second electrode layer 34 covers the light emitting function layer 33, which may serve as a cathode of each light emitting device, i.e., each light emitting device may share the second electrode layer 34. Each of the first electrodes 311 and the corresponding light emitting function layer 33 and the second electrode layer 34 may constitute an OLED light emitting device, and the light emitting function layer 33 may emit light by applying a driving signal to the first electrode layer 31 and the second electrode layer 34.

Further, the light-emitting functional layer 33 may further include an optical adjustment layer (not shown in the figure), which may be disposed on a surface of the second electrode layer 34 away from the substrate 1, and by reasonably setting a refractive index of the optical adjustment layer, a reflection effect of the second electrode layer 34 on light emitted by the light-emitting material layer 332 may be reduced, so as to improve light extraction efficiency.

Further, as shown in fig. 6, 8 and 10, in order to facilitate connection of the second electrode layer 34 with the power line 28 so as to input a signal to the second electrode layer 34, the display panel may further include a bonding layer 7 and a protective layer 8, wherein:

the lap joint layer 7 is made of a conductive material, is arranged on the surface of the flat layer 27, which is away from the substrate 1, and extends to the surface of the power line 28, which is away from the substrate 1, but the lap joint layer 7 does not need to completely cover the power line 28, as long as the lap joint layer 7 can be connected with the power line 28, and the lap joint layer 7 and the first electrode layer 31 are made of the same material and have the same thickness, so that the lap joint layer 7 and the first electrode layer 31 can be formed simultaneously through the same patterning process, but are not directly connected. The peripheral circuit of the peripheral circuit region 202 may be opposed to the landing layer 7 in a direction perpendicular to the substrate 1, for example, the landing layer 7 may be opposed to the light emission control circuit, and only one thin film transistor of the light emission control circuit of the peripheral circuit is shown in fig. 6, 8, and 10, which is opposed to the landing layer 7.

The flat layer 27 is made of an organic material and is easy to absorb water, the light-emitting function layer 33 of the light-emitting device layer 3 can be formed by an evaporation process, and in order to discharge water vapor, the light-emitting function layer can be baked before the light-emitting device layer 3 is formed and after the lap layer 7 and the first electrode layer 31 are formed, and a plurality of exhaust holes 71 distributed in an array are formed in the lap layer 7 corresponding to the area of the flat layer 27, so that the lap layer 7 is prevented from blocking water vapor release.

In order to avoid the damage of the upper layer film layer caused by the burrs at the edge of the vent hole 71, the vent hole 71 can be covered by the protective layer 8, so that the edge of the vent hole 71 is positioned in the range covered by the protective layer 8, and the damage of the burrs to the upper layer film layer is prevented. Specifically, the protective layer 8 is disposed on a surface of the landing layer 7 away from the substrate 1, covers each of the vent holes 71, and exposes a partial region of the landing layer 7, and the second electrode layer 34 may extend to the edge region 203 to a surface of the protective layer 8 away from the substrate 1 and be connected to the landing layer 7 that is not covered by the protective layer 8, so that the second electrode layer 33 is connected to the power line 28 through the landing layer 7, so as to input a signal to the second electrode layer 34.

For example, the protection layer 8 may include a plurality of protection units distributed in an array, each protection unit covers each exhaust hole 71 in a one-to-one correspondence manner, an edge of each exhaust hole 71 is located within an orthographic projection range of the corresponding protection unit on the bonding layer 7, and the protection unit fills the corresponding exhaust hole 71.

As shown in fig. 6 to 11, the first blocking dam 4 is provided on the side of the edge region 203 of the driving layer 2 facing away from the substrate 1. For example, the first blocking dam 4 may be disposed on the surface of the dielectric layer 25 facing away from the substrate 1 and located at the edge region 203, and the first blocking dam 4 may cover the region of the power line 28 not covered by the landing layer 7 and a partial region of the landing layer 7. The first blocking dam 4 is a ring-shaped structure surrounding the peripheral circuit region 202 for confining the organic layer 62 of the encapsulation layer 6.

The first barrier dam 4 is a single-layer or multi-layer structure, and in some embodiments of the present disclosure, the first barrier dam 4 may include a first layer 41 and a second layer 42, wherein:

the first layer 41 of the first blocking dam 4 may be provided on the surface of the dielectric layer 25 facing away from the substrate 1 and located in the edge region 203, and the first layer 41 may cover the region of the power line 28 not covered by the landing layer 7 and a partial region of the landing layer 7. Further, the first layer 41 may be the same material as the pixel defining layer 32 so as to be simultaneously formed through the same patterning process.

The second layer 42 is disposed on a surface of the first layer 41 facing away from the substrate 1, for example, the display panel of the present disclosure may further include a supporting pillar 9, and the supporting pillar 9 may be disposed on a surface of the pixel defining layer 32 facing away from the substrate 1 and does not block the opening of the pixel defining layer 32. The second layer 42 may be the same material as the support posts 9 and thus may be formed through a one-time patterning process in order to simplify the process. Of course, if the supporting pillars 9 and the pixel defining layer 32 are made of the same material, the supporting pillars 9, the pixel defining layer 32, the first layer 41, and the second layer 42 may be formed simultaneously by a single gray-scale mask process.

As shown in fig. 6-11, the drainage strips 5 may be disposed on a side of the edge region 203 of the driving layer 2 facing away from the substrate 1 and extend from the edge region 203 to the peripheral circuit region 202. For example: the current bar 5 can be arranged on the surface of the dielectric layer 25 facing away from the substrate 1 and can cover at least a partial region of the power supply line 28 and extend from the edge region 203 to the surface of the bonding layer 7 facing away from the substrate 1. Meanwhile, the drainage strips 5 are positioned in the range surrounded by the first blocking dam 4, and the drainage strips 5 are distributed at intervals along the annular track and can guide the organic materials to flow to the first blocking dam 4 under the action of capillary effect.

The same material may be used for the drainage bars 5 and the protective layer 8, so that the drainage bars 5 may be formed simultaneously by the same patterning process to simplify the process. Furthermore, the drainage bars 5 may also be the same material as the support posts 9 or the pixel defining layer 32, and thus may be formed simultaneously with the support posts 9 or the pixel defining layer 32. Of course, if the material of the protective layer 8 is the same as the pixel defining layer 32, the flow guide stripes 5 may be formed simultaneously with the protective layer 8 and the pixel defining layer 32. Further, the drainage strips 5 may be formed of the same material as the first layer 41 of the first barrier dam 4 at the same time.

In some embodiments of the present disclosure, as shown in fig. 6 and 7, the drainage bar 5 is connected to the inner sidewall of the first blocking dam 4, and may be of an integrated structure, that is, one end of the drainage bar 5 is connected to the inner sidewall of the first blocking dam 4, and the other end extends toward the pixel driving region 201. Meanwhile, the thickness of the flow guide strips 5 is smaller than that of the first blocking dam 4 in the direction perpendicular to the substrate 1.

Further, the inner side wall of the second layer 42 of the first blocking dam 4 surrounds the outer side wall of the first layer 41, that is, the inner side wall of the second layer 42 of the first blocking dam 4 is located on one side of the inner side wall of the first layer 41, which is far away from the pixel circuit area 201, so that the second layer 42 exposes a partial area of the first layer 41 to form a step, and the drainage strip 5 is connected with the first layer 41, which is beneficial to enabling the organic material of the packaging layer 6 to be stopped at the inner side of the first blocking dam 4. At the same time, the strips 5 are of the same material as the first layer 41 and can thus be formed simultaneously with the first layer 41.

Further, the distance K between the inner side wall of the second layer 42 and the inner side wall of the first layer 41 is not less than 3 μm, so that the organic material is less likely to overflow the first blocking dam 4. In addition, the drainage strips 5 may extend in a straight line toward the pixel driving region 201, and the length L of the drainage strips 5 is 50 μm to 500 μm, and the width D of the drainage strips 5 is 5 μm to 50 μm; the spacing W2 between two adjacent drainage strips 5 can be 5 μm to 100 μm. The width of the drainage strip 5 is the distance between two side walls of the drainage strip 5; the distance between two adjacent drainage strips 5 is the width of the gap between two adjacent drainage strips 5.

In other embodiments of the present disclosure, as shown in fig. 8 and 9, a gap is formed between the inner sidewall of the first blocking dam 4 and the drainage bar 5 to prevent the organic material of the encapsulation layer 6 from overflowing the first blocking dam 4. The gap between the inner side wall of the first blocking dam 4 and the drainage strip 5 is as follows: the first layer 41 is spaced from the orthographic projection of the first barrier dam 4 on the substrate 1 at an end of the orthographic projection of the substrate 1 near the first barrier dam 4. Further, the width W1 of the gap between the drainage strip 5 and the inner side wall of the first blocking dam 4 may be 3 μm to 30 μm.

In still other embodiments of the present disclosure, as shown in fig. 10 and 11, the protective layer 8 includes a plurality of protective stripes 81, and the vent holes 71 are distributed in the area of the overlapping layer 7 covered by the protective stripes 81. For example, the vent holes 71 may be arranged in an array, and each protective strip 81 may cover one row of vent holes 71. The protective bars 81 are butted against the respective flow guide bars 5 in a one-to-one correspondence, so that a path for guiding the organic material to flow toward the first blocking dam 4 can be extended. The protection strips 81 and the drainage strips 5 may be of an integral structure and have the same width, and the two can be formed simultaneously by the same patterning process, that is, the protection strips 81 may be regarded as a strip structure formed by extending at least part of the drainage strips 5 to the pixel circuit region 201, as long as the strip structure can cover each of the exhaust holes 71.

In the embodiment shown in fig. 9 and 10, the drainage strip 5 has a gap with the inner side wall of the first blocking dam 4. Of course, the drainage strip 5 may also be connected to the inner side wall of the first blocking dam 4.

In some embodiments of the present disclosure, as shown in fig. 4 and 12, the orthographic projection of the edge region 203 on the substrate 1 is a polygon, and the edge region 203 may include a plurality of side regions 2301 and an arc region 2032, and two adjacent side regions 2031 are transitionally connected by an arc region 2032. Accordingly, the display panel has a rectangular shape with four curved corners. The first blocking dam 4 is connected in series with each side area 2031 and the arc area 2032, and each side area 2031 and the arc area 2032 are distributed with a flow guide strip 5.

In the arc region 2032, during the process of flowing the organic material used for forming the organic layer 62 of the encapsulation layer 6 outward, the organic material needs to diffuse to both sides, so that the area to be filled gradually increases outward, but the organic material is not increased compared with the side region 2031, thereby causing the problem of insufficient flowing distance of the organic material in the arc region 2032. Therefore, the width of the drainage strip 5 located in the arc area 2032 can be increased towards the direction far away from the pixel circuit area 201, so that the drainage strip 5 of the arc area 2032 is a fan-shaped structure expanded towards the direction far away from the pixel circuit area 201, thereby reducing the area of the area needing to be filled, the organic material of the arc area 2032 can flow to contact with the first blocking dam 4, the condition of insufficient coverage is avoided, the uniformity of light emission at the corner of the display panel is improved, and the process risk is reduced.

Further, the side walls of the draining bars 5 at two sides of the gap between two adjacent draining bars 5 of the arc region 2032 are parallel, so that the orthographic projection of the gap between two adjacent draining bars 5 of the arc region 2032 on the substrate 1 is rectangular. The distance W3 between two adjacent drainage strips 5 in the arc region 2032 is not greater than the distance W2 between two adjacent drainage strips 5 in the side region 2031, so that the area to be filled between two adjacent drainage strips 5 in the arc region 2032 is not greater than the area to be filled between two adjacent drainage strips 5 in the side region 2031.

In the embodiment shown in fig. 12, the drainage strip 5 has a gap with the inner side wall of the first blocking dam 4. Of course, the drainage strip 5 may also be connected to the inner side wall of the first blocking dam 4.

As shown in fig. 6 to 12, the encapsulation layer 6 includes a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63, in which:

the first inorganic layer 61 covers the light emitting device layer 3, the first blocking dam 4 and the drainage strip 5, the thickness of the first inorganic layer 61 is smaller than that of the drainage strip 5, and the first inorganic layer is attached to the first blocking dam 4 and the drainage strip 5 along with the shape, namely, the first inorganic layer protrudes from the area corresponding to the first blocking dam 4 and the drainage strip 5.

The organic layer 62 is provided on the surface of the first inorganic layer 61 facing away from the substrate 1, and is confined within a range surrounded by the first blocking dam 4. The organic material may be printed by means of ink-jet printing on the surface of the first inorganic layer 61 facing away from the substrate 1, resulting in an organic layer 62. In this process, the projections of the first inorganic layer 61 corresponding to the drainage strips 5 may generate a capillary effect to guide the organic material toward the first blocking dam 4, thereby preventing the occurrence of insufficient coverage and overflow of the organic layer 62.

The second inorganic layer 63 may cover the organic layer 62 and the first inorganic layer 61, thereby wrapping the organic layer 62 between the first inorganic layer 61 and the second inorganic layer 63. The boundary of the orthographic projection of the first inorganic layer 61 and the second inorganic layer 63 on the substrate 1 coincides with the boundary of the substrate 1 and can be used for water blocking, and the organic layer 62 is used for flattening the interface, covering defects and releasing stress.

As shown in fig. 6 to 12, the display panel further includes a second blocking dam 10, and the second blocking dam 10 is disposed on a side of the edge region 203 facing away from the substrate 1, for example, on a surface of the dielectric layer 25 facing away from the substrate 1. Meanwhile, the second blocking dam 10 is disposed around the first blocking dam 4, and the first inorganic layer 61 covers the second blocking dam 10.

In some embodiments of the present disclosure, as shown in fig. 6, 8, and 10, the second blocking dam 10 may cover a partial area of the power supply line 28, for example, the second blocking dam 10 covers an edge of a side of the power supply line 28 facing away from the pixel circuit area 201, may cover a burr of the edge of the power supply line 28, and prevent the power supply line 28 from warping.

The second blocking dam 10 may be a single layer or a multi-layer structure, and in some embodiments of the present disclosure, the second blocking dam 10 may have a height greater than that of the first blocking dam 4, which may include a first layer 101, a second layer 102, and a third layer 103, wherein the first layer 101 may be the same material as the planarization layer 27 and may be formed through the same patterning process. The second layer 102 may be the same material as the pixel defining layer 32 and may be formed simultaneously by the same patterning process. The third layer 103 may be the same material as the support posts 9 and may be formed simultaneously by the same patterning process. In addition, the edge of the lap joint layer 7 away from the pixel circuit area 201 can extend into the space between the first layer 101 and the second layer 102, so that the lap joint layer 7 is prevented from warping, the first layer 101 can be protected by the lap joint layer 7, and the first layer 101 is prevented from being peeled off from the dielectric layer 25 in other processes after the first layer 101 is formed.

The embodiments of the present disclosure also provide a method for manufacturing a display panel, where the display panel may be the display panel of any of the above embodiments, and the specific structure of the display panel may refer to the above embodiments of the display panel, and will not be described in detail herein. As shown in fig. 13, the manufacturing method may include steps S110 to S160, in which:

step S110, forming a driving layer on one side of a substrate, the driving layer having a pixel circuit region, a peripheral circuit region surrounding the pixel circuit region, and a margin region surrounding the peripheral circuit region;

step S120, forming a light-emitting device layer on one side of the pixel circuit region layer, which is far away from the substrate;

step S130, forming a first blocking dam and a plurality of drainage strips on one side of the edge region, which is far away from the substrate, wherein the first blocking dam is of an annular structure surrounding the peripheral circuit region; the drainage strip is positioned in a range surrounded by the first blocking dam; the drainage strips are distributed at intervals, and each drainage strip extends from the edge area to the peripheral circuit area;

step S140 of forming a first inorganic layer covering the light emitting device layer, the first blocking dam, and the current guide strip, and the first inorganic layer being protruded in a region corresponding to the first blocking dam and the current guide strip;

step S150, forming an organic layer on the surface of the first inorganic layer, which is far away from the substrate, wherein the organic layer is limited within the range surrounded by the first barrier dam;

step S160 of forming a second inorganic layer covering the organic layer and the first inorganic layer.

Details of the corresponding structures of the steps of the manufacturing method according to the embodiment of the present disclosure have been described in the above embodiment of the display panel, and are not described herein again.

The embodiment of the present disclosure further provides a display device, which may include the display panel of any of the above embodiments, and the structure of the display panel may refer to the above embodiments of the display panel, and specific structures and beneficial effects thereof are not described herein again. The display device disclosed by the present disclosure may be an electronic device with a display function, such as a mobile phone, a tablet computer, a television, etc., which are not listed here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising:

a substrate;

2. The display panel according to claim 1, wherein the drainage bar is connected to an inner sidewall of the first blocking dam; in a direction perpendicular to the substrate, a thickness of the flow guide strips is smaller than a thickness of the first dam.

3. The display panel according to claim 2, wherein the first barrier dam includes a first layer and a second layer stacked in this order in a direction away from the substrate, an inner sidewall of the second layer surrounding outside an inner sidewall of the first layer; the drainage strip is connected with the first layer and is made of the same material.

4. The display panel according to claim 1, wherein a gap is provided between an inner sidewall of the first blocking dam and the drainage bar.

5. The display panel according to claim 1, wherein the orthographic projection of the edge region on the substrate is polygonal and comprises a plurality of side regions and arc regions, and two adjacent side regions are transitionally connected by one arc region;

6. The display panel according to claim 1, wherein the driving layer comprises:

7. The display panel according to claim 6, wherein the light-emitting device layer comprises:

a second electrode layer covering the light emitting function layer;

the display panel further includes:

8. The display panel according to claim 7, wherein the protective layer comprises a plurality of protective strips, and the vent holes are distributed in the area of the overlapping layer covered by the protective strips; and the protection strips are butted with the drainage strips in a one-to-one correspondence manner.

9. The display panel according to claim 7, characterized by further comprising:

10. The display panel according to claim 1, characterized in that the display panel further comprises:

11. The display panel according to claim 3, wherein a distance between an inner sidewall of the second layer and an inner sidewall of the first layer is not less than 3 μm.

12. The display panel according to claim 4, wherein a width of a gap between the drainage bar and the inner sidewall of the first barrier dam is 3 μm to 30 μm.

13. The display panel according to claim 1, wherein the length of the drainage bars is 50 μm to 500 μm, and the width of the drainage bars is 5 μm to 50 μm; the distance between two adjacent drainage strips is 5-100 mu m.

14. The display panel of claim 1, wherein each of the plurality of drainage bars is spaced along a circular track.

15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.