CN212967039U - OPS host computer regulating circuit that is shaded - Google Patents
OPS host computer regulating circuit that is shaded Download PDFInfo
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- CN212967039U CN212967039U CN202021543142.XU CN202021543142U CN212967039U CN 212967039 U CN212967039 U CN 212967039U CN 202021543142 U CN202021543142 U CN 202021543142U CN 212967039 U CN212967039 U CN 212967039U
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- 230000009286 beneficial effect Effects 0.000 description 2
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Abstract
The utility model discloses a OPS host computer regulating circuit that is shaded, OPS host computer are equipped with first chip and signal input module, and first chip includes first control module and second control module, signal input module with first control module connects. And after the first control module receives a low level signal of the signal input module and the counting analysis of the first control module, the second control module adjusts the Pulse Width Modulation (PWM) duty ratio to adjust the backlight brightness. The backlight brightness can be simply and conveniently adjusted along with the change of the input signal of the signal input module.
Description
Technical Field
The utility model relates to an adjusting circuit, in particular to OPS host computer adjusting circuit in a poor light.
Background
Currently, the backlight control is generally operated by a soft control, i.e. a soft keyboard, such as clicking an on-screen icon, or directly clicking an on-screen icon, such as an OSD, i.e. an on-screen menu type adjustment control.
The conventional OPS host cannot directly adjust the backlight brightness and can only adjust the backlight brightness in a system soft control mode. In the using process, the soft control mode for adjusting the backlight brightness needs to be displayed on a screen, and can occupy a display screen picture and interrupt an ongoing task, and the soft control mode generally needs to be set to enter the adjustment picture, so that the adjustment of the backlight brightness is complex.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides an OPS host computer is shaded and is adjusted circuit, regulation luminance in a poor light that can be simple and convenient.
According to the utility model discloses OPS host computer regulating circuit in a poor light, include: the chip comprises a signal input module and a first chip, wherein the first chip comprises a first control module and a second control module, and the first control module is connected with the signal input module.
According to the utility model discloses OPS host computer regulating circuit in a poor light has following beneficial effect at least: the OPS host is provided with a first chip and a signal input module, the first chip comprises a first control module and a second control module, and the signal input module is connected with the first control module. And after the first control module receives a low level signal of the signal input module and the counting analysis of the first control module, the second control module adjusts the Pulse Width Modulation (PWM) duty ratio to adjust the backlight brightness. The backlight brightness can be simply and conveniently adjusted along with the change of the input signal of the signal input module.
According to the utility model discloses a some embodiments, signal input module includes button module and adjusting module, button module one end ground connection, the other end with adjusting module's input is connected, adjusting module's output with first control module connects.
According to some embodiments of the present invention, the adjusting module comprises a Brightness raising module, the key module comprises a UP pin, the Brightness raising module is connected to the UP pin of the key module, and the output end of the Brightness raising module is connected to the GPIO port bright _ UP pin of the first control module.
According to some embodiments of the present invention, the Brightness raising module includes a first NMOS transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3, the first resistor R1 is connected to a power source VCC at an upper end thereof, and is connected to the second resistor R2 at another end thereof, the output end of the signal input module is connected to a connection line between the first resistor R1 and the second resistor R2, the second resistor R2 is connected to a gate of the first NMOS transistor Q1 at another end thereof, the source of the first NMOS transistor Q1 is grounded, the upper drain of the first NMOS transistor Q1 is connected to the third resistor R3 at an upper end thereof, the other end of the third resistor R3 is connected to the power source VCC, and the GPIO bright _ UP pin of the first control module is connected to a drain of the first NMOS transistor Q1 and the third resistor R3 at another end thereof.
According to some embodiments of the present invention, the luminance raising module includes a first NMOS transistor Q1, a second NMOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, the first resistor R1 is connected to a power source VCC at an upper end and to the second resistor R2 at another end, the output terminal of the signal input module is connected to a connection line between the first resistor R1 and the second resistor R2, the second resistor R2 is connected to the gate of the first NMOS transistor Q1 at another end, the source of the first NMOS transistor Q1 is grounded, the drain of the first NMOS transistor Q1 is terminated with the third resistor R3, the third resistor R3 is connected to the power source VCC at another end, the gate of the second NMOS transistor Q2 is connected to a drain of the first NMOS transistor Q1 and to the third resistor R3, the source of the second NMOS transistor Q5 is grounded, and the drain of the second NMOS transistor Q2 is connected to the fourth resistor R57323, the other end of the fourth resistor R4 is connected to a power supply VSS, and a GPIO port bright _ UP pin corresponding to the first control module is connected between the drain of the second NMOS transistor Q2 and a connection line of the fourth resistor R4.
According to the utility model discloses a some embodiments, the adjusting module includes the luminance reduction module, and the button module still includes the DOWN foot, the luminance reduction module with the DOWN foot of button module is connected, the output of luminance reduction module with GPIO mouth Brightness _ Down foot of first control module is connected.
According to some embodiments of the present invention, the Brightness reduction module includes a third NMOS transistor Q3, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the upper end of the fifth resistor R5 is connected to a power source VCC, the other end of the fifth resistor R5 is connected to the sixth resistor R6, the output end of the signal input module is connected to the space between the connection lines of the fifth resistor R5 and the sixth resistor R6, the other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3, the source of the third NMOS transistor Q3 is grounded, the drain of the third NMOS transistor Q3 is terminated with the seventh resistor R7 GPIO, the other end of the seventh resistor R7 is connected to the power source VCC, and the bright _ Down pin of the first control module is connected to the drain of the third NMOS transistor Q3 and the drain of the seventh resistor R7.
According to some embodiments of the present invention, the luminance reducing module includes a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, the upper end of the fifth resistor R5 is connected to a power source VCC, the other end of the fifth resistor R5 is connected to the sixth resistor R6, the output end of the signal input module is connected between the connection line of the fifth resistor R5 and the sixth resistor R6, the other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3, the source of the third NMOS transistor Q3 is grounded, the drain of the third NMOS transistor Q3 is terminated to the seventh resistor R7, the other end of the seventh resistor R7 is connected to the power source VCC, the gate of the fourth NMOS transistor Q4 is connected to the drain of the seventh resistor Q45 and the third NMOS transistor Q3, the source of the fourth NMOS transistor Q5 is grounded, the source of the fourth NMOS transistor Q4 is connected to the eighth NMOS transistor Q57323, the other end of the eighth resistor R8 is connected to a power supply VSS, and a GPIO port bright _ Down pin corresponding to the first control module is connected between the drain of the fourth NMOS transistor Q4 and the connection line of the eighth resistor R8.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram of an OPS host backlight adjusting circuit according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of an OPS host backlight adjusting circuit according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of an OPS host backlight adjusting circuit according to a third embodiment of the present invention;
fig. 4 is a schematic diagram of a brightness increasing module of an OPS host backlight adjusting circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a brightness increasing module of an OPS host backlight adjusting circuit according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a brightness reduction module of an OPS host backlight adjusting circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a brightness reduction module of an OPS host backlight adjusting circuit according to another embodiment of the present invention;
fig. 8 is a schematic diagram of a key module of an OPS host backlight adjusting circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a first chip of an OPS host backlight adjusting circuit according to an embodiment of the present invention.
Reference numerals:
the display device comprises a signal input module 100, a key module 110, an adjusting module 120, a brightness increasing module 121, a brightness decreasing module 122, a first chip 200, a first control module 210 and a second control module 220.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.
Referring to fig. 1, an embodiment of the present invention provides an OPS host backlight adjusting circuit, including a signal input module 100 and a first chip 200, where the first chip 200 includes a first control module 210 and a second control module 220, and the first control module 210 is connected with the signal input module 100.
According to the utility model discloses OPS host computer regulating circuit in a poor light has following beneficial effect at least: the OPS host is provided with a first chip 200 and a signal input module 100, the first chip 200 includes a first control module 210 and a second control module 220, and the signal input module 100 is connected to the first control module 210. After the first control module 210 receives a low level signal from the signal input module 100, the second control module 220 adjusts the PWM duty ratio to adjust the backlight brightness through the counting analysis of the first control module 210. The backlight brightness can be easily adjusted according to the variation of the input signal of the signal input module 100.
Referring to fig. 2 and 6, in some embodiments of the present invention, the signal input module 100 includes a key module 110 and an adjusting module 120, one end of the key module 110 is grounded, the other end is connected to an input end of the adjusting module 120, and the adjusting module 120 is connected to the first control module 210. When the key is pressed down, the key is contacted with the ground wire, a low level signal is input, the key is released and disconnected with the ground wire, and the low level signal is converted into a high level signal. Thus, a signal input of a low level is completed. When the signal completes one time of the change from the high level to the low level and then to the high level, the first control module 210 of the OPS host receives the signal and counts, specifically, records the number of rising edges. After the first control module 210 of the OPS host receives the signal, it interrupts the ongoing task and jumps to the second control module 220, and the second control module 220 adjusts the backlight brightness by adjusting the PWM duty.
Referring to fig. 3, 4, 6 and 7, in some embodiments of the present invention, the adjusting module 120 includes a Brightness increasing module 121, the key module includes a UP pin, the Brightness increasing module 121 is connected to the UP pin of the key module 110, and an output end of the Brightness increasing module 121 is connected to a GPIO port bright _ UP pin of the first control module 210. The first control module 210 of the OPS host is divided into a GPIO interface to connect with the brightness increasing module 121, and can count the signals with increased brightness and jump to the second control module 220, and the corresponding increasing response is made by adjusting the duty ratio of the pulse width modulation PWM.
Referring to fig. 4, in some embodiments of the present invention, the Brightness raising module 121 includes a first NMOS transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3, an upper end of the first resistor R1 is connected to the power source VCC, the other end of the first resistor R1 is connected to the second resistor R2, an output end of the signal input module 100 is connected to a connection line between the first resistor R1 and the second resistor R2, the other end of the second resistor R2 is connected to a gate of the first NMOS transistor Q1, a source of the first NMOS transistor Q1 is grounded, an upper end of a drain of the first NMOS transistor Q1 is connected to the third resistor R3, the other end of the third resistor R3 is connected to the power source VCC, and a GPIO port bright _ UP pin of the first control module 210 is connected between a drain of the first NMOS transistor Q1 and the third resistor R3.
In the initial state, VCC supplies power, the gate of Q1 is in a high level state, at this time, Q1 is turned on, the drain voltage of Q1 is low level, and the input voltage of the first control module 210 of the OPS host is Q1; when the UP key is pressed, the key is in contact with the ground to obtain a low-level signal, at this time, Q1 is turned off, the drain voltage of Q1 is high level, and the drain voltage of the GPIO port of the first control module 210 of the OPS host is high level, namely the drain voltage of Q1; when the key is released, the initial state is restored, and the input voltage of the GPIO port is low level. The first control module 210 jumps to the second control module 220 to adjust the Pulse Width Modulation (PWM) duty ratio to increase the corresponding gear by recording the number of the rising edges of the input signal.
Referring to fig. 5, in some embodiments of the present invention, the luminance raising module 121 includes a first NMOS transistor Q1, a second NMOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, an upper end of the first resistor R1 is connected to a power source VCC, and the other end is connected to a second resistor R2, an output end of the signal input module 100 is connected to a connection line between the first resistor R1 and the second resistor R2, the other end of the second resistor R2 is connected to a gate of the first NMOS transistor Q1, a source of the first NMOS transistor Q1 is grounded, a drain of the first NMOS transistor Q1 is connected to the third resistor R3, the other end of the third resistor R3 is connected to the power source VCC, a gate of the second NMOS transistor Q2 is connected to a drain of the first NMOS transistor Q1 and a drain of the third resistor R3, a source of the second NMOS transistor Q2 is grounded, a drain of the second NMOS transistor Q2 is connected to a VSS resistor R68628, and a fourth resistor R599, the GPIO port Brightness _ UP pin of the first control block 210 is connected between the drain of the second NMOS transistor Q2 and the fourth resistor R4.
In the initial state, VCC supplies power, the gate of Q1 is in the high level state, at this time, Q1 is turned on, the drain voltage of Q1 and the gate voltage of Q2 are both at the low level, so Q2 is turned off, and the output voltage, that is, the input voltage of the first control module 210 of the OPS host is VSS high level; when the UP key is pressed, the key is in contact with the ground to obtain a low-level signal, at this time, Q1 is turned off, Q2 is turned on, and the output voltage of Q2, i.e., the input voltage of the GPIO port of the first control module 210 of the OPS host computer, is low level; when the key is released, the initial state is restored, and the input voltage of the GPIO port is high level. The first control module 210 jumps to the second control module 220 to adjust the Pulse Width Modulation (PWM) duty ratio to increase the corresponding gear by recording the number of the rising edges of the input signal.
Referring to fig. 3, 5, 6 and 7, in some embodiments of the present invention, the adjusting module 120 includes a Brightness reducing module 122, the key module includes a DOWN pin, an output terminal of the Brightness reducing module 122 is connected to the GPIO port Brightness _ DOWN pin of the first control module 210, and the Brightness reducing module 122 is connected to the DOWN pin of the key module 110. The first control module 210 of the OPS host is divided into a GPIO port to connect to the brightness reduction module 122, and can count the brightness reduction signal and jump to the second control module 220, and the corresponding reduction response is made by adjusting the PWM duty ratio.
Referring to fig. 6, in some embodiments of the present invention, the luminance reducing module 122 includes a third NMOS transistor Q3, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, an upper end of the fifth resistor R5 is connected to the power source VCC, another end of the fifth resistor R5 is connected to the sixth resistor R6, an output end of the signal input module 100 is connected between connection lines of the fifth resistor R5 and the sixth resistor R6, another end of the sixth resistor R6 is connected to a gate of the third NMOS transistor Q3, a source of the third NMOS transistor Q3 is grounded, an upper end of a drain of the third NMOS transistor Q3 is connected to the seventh resistor R7, another end of the seventh resistor R7 is connected to the power source VCC, and a GPIO port bright _ Down pin of the first control module 210 is connected between a drain of the third NMOS transistor Q3 and the seventh resistor R7.
In the initial state, VCC supplies power, the gate of Q3 is in a high level state, at this time, Q3 is turned on, the drain voltage of Q3 is low level, and the input voltage of the first control module 210 of the OPS host is Q3; when a DOWN key is pressed, the key is contacted with the ground to obtain a low-level signal, at the moment, the Q3 is cut off, the drain voltage of the Q3 is high level, and the drain voltage of the GPIO port of the first control module 210 of the OPS host is high level, namely the drain voltage of the Q3; when the key is released, the initial state is restored, and the input voltage of the GPIO port is low level. The first control module 210 jumps to the second control module 220 to adjust the Pulse Width Modulation (PWM) duty ratio to increase the corresponding gear by recording the number of the rising edges of the input signal.
Referring to fig. 7, in some embodiments of the present invention, the luminance reducing module 122 includes a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, an upper end of the fifth resistor R5 is connected to the power source VCC, and the other end is connected to the sixth resistor R6, an output end of the signal input module 100 is connected between a connection line of the fifth resistor R5 and the sixth resistor R6, the other end of the sixth resistor R6 is connected to a gate of the third NMOS transistor Q3, a source of the third NMOS transistor Q3 is grounded, an upper end of a drain of the third NMOS transistor Q3 is connected to the seventh resistor R7, the other end of the seventh resistor R7 is connected to the power source VCC, a gate of the fourth NMOS transistor Q4 is connected between a drain of the third NMOS transistor Q3 and the seventh resistor R7, a source of the fourth NMOS transistor Q4 is grounded, a drain of the fourth NMOS transistor Q4 is connected to the VSS, and the other end of the eighth resistor R599, the GPIO port bright _ Down pin of the first control block 210 is connected between the drain of the fourth NMOS transistor Q4 and the eighth resistor R8.
In the initial state, VCC supplies power, the gate of Q3 is in the high level state, at this time, Q3 is turned on, the drain voltage of Q3 and the gate voltage of Q4 are both at the low level, so Q4 is turned off, and the output voltage, that is, the input voltage of the first control module 210 of the OPS host is VSS high level; when a DOWN key is pressed, the key is contacted with the ground to obtain a low level signal, at the moment, Q3 is cut off, Q4 is conducted, and the output voltage of Q4, namely the input voltage of the GPIO port of the first control module 210 of the OPS host computer, is low level; when the key is released, the initial state is restored, and the input voltage of the GPIO port is high level. The first control module 210 jumps to the second control module 220 to adjust the Pulse Width Modulation (PWM) duty ratio to lower the corresponding gear by recording the number of the rising edges of the input signal.
Further, the second control module 220 sets the pulse width modulation PWM duty ratio to 10 levels, the default level is at the fifth level, the default duty ratio is 50%, a low level signal is input at the GPIO port to trigger the system terminal, and the pulse width modulation PWM duty ratio is increased/decreased by one level on the original basis until the pulse width modulation PWM duty ratio is adjusted to 100/5 or 0.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (8)
1. An OPS host backlight adjusting circuit, comprising: the chip comprises a signal input module and a first chip, wherein the first chip comprises a first control module and a second control module, and the first control module is connected with the signal input module.
2. The OPS host backlight adjusting circuit of claim 1, wherein the signal input module comprises a key module and an adjusting module, one end of the key module is grounded, the other end of the key module is connected with the input end of the adjusting module, and the output end of the adjusting module is connected with the first control module.
3. The OPS host backlight adjustment circuit of claim 2, wherein the adjustment module comprises a Brightness boost module, the key module comprises a UP pin, the Brightness boost module is connected to the UP pin of the key module, and the output terminal of the Brightness boost module is connected to the GPIO port Brightness _ UP pin of the first control module.
4. The OPS host backlight adjusting circuit of claim 3, wherein the Brightness increasing module comprises a first NMOS transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3, the first resistor R1 is connected to a power source VCC at an upper end thereof and to the second resistor R2 at another end thereof, the output terminal of the signal input module is connected to a connection line between the first resistor R1 and the second resistor R2, the second resistor R2 is connected to a gate of the first NMOS transistor Q1 at another end thereof, the source of the first NMOS transistor Q1 is grounded, the drain of the first NMOS transistor Q1 is terminated with the third resistor R3 at a drain end thereof, the third resistor R3 is connected to the power source VCC at another end thereof, and the GPIO port bright _ pin of the first control module is connected to the drain of the first NMOS transistor Q1 and the third resistor R3.
5. The OPS host backlight adjusting circuit of claim 3, wherein the brightness raising module comprises a first NMOS transistor Q1, a second NMOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, the first resistor R1 is connected to a power source VCC at its upper end and to the second resistor R2 at its other end, the output terminal of the signal input module is connected to a connection line between the first resistor R1 and the second resistor R2, the second resistor R2 is connected to the gate of the first NMOS transistor Q1 at its other end, the source of the first NMOS transistor Q1 is grounded, the drain of the first NMOS transistor Q1 is connected to the third resistor R3 at its upper end, the third resistor R3 is connected to the power source VCC at its other end, the gate of the second NMOS transistor Q2 is connected to the drain of the first NMOS transistor Q1 and the source of the third resistor R3, and the source of the second NMOS transistor Q2 is grounded, the drain of the second NMOS transistor Q2 is connected to a fourth resistor R4, the other end of the fourth resistor R4 is connected to a power supply VSS, and a GPIO port bright _ UP pin corresponding to the first control module is connected between the drain of the second NMOS transistor Q2 and a connection line of the fourth resistor R4.
6. The OPS host backlight adjustment circuit of claim 2, wherein the adjustment module comprises a Brightness reduction module, the key module further comprises a DOWN pin, the Brightness reduction module is connected to the DOWN pin of the key module, and an output terminal of the Brightness reduction module is connected to a GPIO port Brightness _ DOWN pin of the first control module.
7. The OPS host backlight adjusting circuit of claim 6, wherein the Brightness reduction module comprises a third NMOS transistor Q3, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the fifth resistor R5 is connected to a power source VCC at an upper end and is connected to the sixth resistor R6 at another end, the output terminal of the signal input module is connected between the connection lines of the fifth resistor R5 and the sixth resistor R6, the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3 at another end, the source of the third NMOS transistor Q3 is grounded, the drain of the third NMOS transistor Q3 is terminated with the seventh resistor R7 at another end, the seventh resistor R7 is connected to the power source VCC at another end, and the GPIO port bright _ n pin of the first control module is connected between the drain of the third NMOS transistor Q3 and the seventh resistor R7.
8. The OPS host backlight adjusting circuit of claim 6, wherein the brightness reduction module comprises a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, the upper end of the fifth resistor R5 is connected to a power source VCC, the other end of the fifth resistor R6 is connected to the sixth resistor R6, the output end of the signal input module is connected between the connection line of the fifth resistor R5 and the sixth resistor R6, the other end of the sixth resistor R6 is connected to the gate of the third NMOS transistor Q3, the source of the third NMOS transistor Q3 is grounded, the drain of the third NMOS transistor Q3 is connected to the seventh resistor R7, the other end of the seventh resistor R7 is connected to the power source VCC, the gate of the fourth NMOS transistor Q4 is connected to the source of the seventh resistor R7 and the drain of the third NMOS transistor Q3, and the source of the fourth NMOS transistor Q4, the drain of the fourth NMOS transistor Q4 is connected to an eighth resistor R8, the other end of the eighth resistor R8 is connected to the power supply VSS, and the GPIO port bright _ Down pin corresponding to the first control module is connected between the drain of the fourth NMOS transistor Q4 and the connection line of the eighth resistor R8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021543142.XU CN212967039U (en) | 2020-07-28 | 2020-07-28 | OPS host computer regulating circuit that is shaded |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021543142.XU CN212967039U (en) | 2020-07-28 | 2020-07-28 | OPS host computer regulating circuit that is shaded |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212967039U true CN212967039U (en) | 2021-04-13 |
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|---|---|---|---|
| CN202021543142.XU Expired - Fee Related CN212967039U (en) | 2020-07-28 | 2020-07-28 | OPS host computer regulating circuit that is shaded |
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| Country | Link |
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| CN (1) | CN212967039U (en) |
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2020
- 2020-07-28 CN CN202021543142.XU patent/CN212967039U/en not_active Expired - Fee Related
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