CN212909338U - Power supply redundancy circuit - Google Patents
Power supply redundancy circuit Download PDFInfo
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- CN212909338U CN212909338U CN202021611017.8U CN202021611017U CN212909338U CN 212909338 U CN212909338 U CN 212909338U CN 202021611017 U CN202021611017 U CN 202021611017U CN 212909338 U CN212909338 U CN 212909338U
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Abstract
The utility model relates to a power supply redundancy circuit, including two at least way input power, each way input power exports to same load, every input power all is connected with MOS pipe protection circuit all the way, MOS pipe protection circuit includes the NMOS pipe, and the input power is connected to the source electrode of NMOS pipe, and the load is connected to the drain electrode, and a the control unit is connected to the grid for the break-make of control NMOS pipe. The utility model discloses replace the diode with the MOS pipe, because MOS pipe conduction pressure drop is little, power loss is little, and the heat conductivity is better, and is safer, has also saved the demand to diode radiator or similar heat management technique in the high power is used, the cost is reduced.
Description
Technical Field
The utility model belongs to the technical field of the technique of power protection and specifically relates to a redundant circuit of power is related to.
Background
In the context of modern industrial automation, in particular in the application of control systems, more and more devices are connected to the control system, which greatly increases the power supply of the power supply, so that a reliable and powerful power supply is required in the control system.
In order to improve safety and reliability, the power supplies of the control system are often in a redundant mode, that is, at least one additional power supply is added in the system, and when one power supply fails, the other power supplies can provide power for the system. The redundancy mode is a fault tolerance technology, and under the normal operation condition, the probability of the simultaneous fault of a plurality of power supplies is quite low, so that the system fault can be effectively avoided, and the cost performance of a system with a larger scale is higher.
The conventional power supply redundancy is realized by means of diodes, as shown in fig. 1, two power supplies are output to a common point connected to a load through diodes D1 and D2, and are used for preventing faults such as short circuit of an input power supply and the like of a system. Because the diode only allows current to flow in a single direction, the diode can realize fault isolation of the redundant bus, thereby enabling the system to keep running by using the residual power supply.
However, there are also disadvantages to using conventional diodes. When the method works, the diode is always in a forward conduction state, and the inherent conduction voltage drop of the diode causes the problems of serious heating and serious power loss in a high-power application occasion, so that the potential safety hazard and the resource waste are caused.
In the prior art, a diode radiator or similar thermal management technology is often needed to solve the problems, but the problems are only relieved, the cost is too high, and the problem of resource waste is not solved.
With the increase of high-power application occasions, the problems of serious heat generation and high power loss of the power supply redundancy design of the diode are more and more serious.
SUMMERY OF THE UTILITY MODEL
Not enough to prior art exists, the utility model aims at providing a power supply redundancy circuit improves the problem that the generating heat that the redundant power supply circuit of diode brought is high, power loss is high, the security performance is low.
The above utility model discloses an above-mentioned utility model purpose can realize through following technical scheme: a power supply redundancy circuit comprises at least two paths of input power supplies, wherein each path of input power supply is output to the same load, each path of input power supply is connected with an MOS (metal oxide semiconductor) tube protection circuit, each MOS tube protection circuit comprises an NMOS tube, the source electrode of the NMOS tube is connected with the input power supply, the drain electrode of the NMOS tube is connected with the load, and the grid electrode of the NMOS tube is connected with a control unit for controlling the on-off of the NMOS tube.
Through adopting above-mentioned technical scheme, replace the diode with the MOS pipe, because MOS pipe conduction pressure drop is little, power loss is little, and the heat conductivity is better, and is safer, has also saved the demand to diode radiator or similar thermal management technique in the high power is used, the cost is reduced.
The voltage between the source electrode and the drain electrode of the MOS tube is monitored by the control unit, and the control unit controls the voltage output to the grid electrode of the MOS tube through the monitored source electrode-drain electrode voltage of the MOS tube, so that the control of the working state of the MOS tube is realized. When two paths of redundant power supplies are input, the output is the power supply with higher power supply voltage, and the other path is in a standby state; when the output power supply fails, the other power supply in the standby state works immediately.
Preferably, the control unit adopts an LM5050MK-1 control chip, a pin 4 of the control chip is connected with a source electrode of the NMOS tube, a pin 5 is connected with a grid electrode of the NMOS tube, a pin 6 is connected with a drain electrode of the NMOS tube, and a pin 3 is grounded after being connected with a pin 2 in parallel.
By adopting the technical scheme, the voltage of the 5 th pin is changed by detecting the voltage between the 4 th pin and the 6 th pin of the control chip, so that the control on the working state of the NMOS tube is realized.
Preferably, the 3 rd pin and the 2 nd pin of the control chip are connected in parallel and then connected with a first protection circuit, one end of the first protection circuit is connected with a connection point of the 3 rd pin and the 2 nd pin, and the other end of the first protection circuit is grounded. The first protection circuit can adopt a diode, so that the circuit has the function of preventing reverse connection, and the problem of wrong connection of a power line is avoided.
Preferably, the pin 3 and the pin 2 of the control chip are connected in parallel and then connected to an input power supply through a voltage regulator diode, the anode of the voltage regulator diode is connected to the connection point of the pin 3 and the pin 2, and the cathode of the voltage regulator diode is connected to the input power supply. The voltage stabilizing diode can keep the voltage at two ends unchanged, so that the power supply voltage is kept stable.
Preferably, the 1 st pin of the control chip is connected with the input power supply through a current-limiting resistor, so that the current can be prevented from being overlarge.
Preferably, the input end of the input power supply is connected in parallel with a first filter circuit, and the first filter circuit may be a bypass capacitor for filtering out voltage ripples.
Preferably, the input end of the input power supply is connected in parallel with a second protection circuit, one end of the second protection circuit is connected with the input power supply, and the other end of the second protection circuit is grounded. The second protection circuit is generally a resistor, when only one path of power supply is input, the added resistor can pull down the voltage drop generated at the input side of the other path of power supply, so as to ensure that the voltage of the path of power supply without input is 0, and improve the safety.
Preferably, the drain stage of the NMOS transistor is connected in parallel with a second filter circuit, and the second filter circuit may be one or more bypass capacitors for filtering out voltage ripples at the output terminal.
Preferably, the drain of the NMOS transistor is connected in parallel with a third protection circuit for protecting a load. The third protection circuit can be a transient suppression diode for overcurrent protection.
To sum up, the utility model discloses following beneficial technological effect has: the MOS tube is used for replacing a diode, so that the thermal conductivity is better, the safety is higher, the defects of high heating and large power loss of the traditional redundant circuit are overcome in a high-power environment, and the low-loss and high-efficiency safe application can be realized under the high power; and has the safety measures of preventing reverse connection of the power supply, power supply redundancy and the like.
Drawings
FIG. 1 is a schematic diagram of a prior art power supply redundancy circuit;
fig. 2 is a circuit diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 2, for the utility model discloses a power supply redundancy circuit, including two at least way input power, this embodiment is two way (V1, V2), two way input power exports to same load Vout, every input power all is connected with MOS pipe protection circuit all the way, MOS pipe protection circuit includes the NMOS pipe, and input power is connected to the source electrode of NMOS pipe, and the load is connected to the drain electrode, and a control unit is connected to the grid for the break-make of control NMOS pipe.
The MOS tube replaces a diode, and the MOS tube is small in conduction voltage drop, small in power loss, good in heat conductivity and safe, so that the requirement for a diode radiator or a similar heat management technology in high-power application is eliminated, and the cost is reduced.
The voltage between the source electrode and the drain electrode of the MOS tube is monitored by the control unit, and the control unit controls the voltage output to the grid electrode of the MOS tube through the monitored source electrode-drain electrode voltage of the MOS tube, so that the control of the working state of the MOS tube is realized. When two paths of redundant power supplies are input, the output is the power supply with higher power supply voltage, and the other path is in a standby state; when the output power supply fails, the other power supply in the standby state works immediately.
Taking one of the MOS transistor protection circuits as an example, as shown in fig. 2, the control unit adopts a first control chip U1 with a model number LM5050MK-1, a 4 th pin of the first control chip U1 is connected to a source of a first NMOS transistor Q1, a 5 th pin is connected to a gate of the first NMOS transistor Q1, and a 6 th pin is connected to a drain of the first NMOS transistor Q1. In this way, the voltage of the 5 th pin can be changed by detecting the voltage between the 4 th pin and the 6 th pin of the first control chip U1, thereby realizing the control of the operating state of the first NMOS transistor Q1.
The No. 3 pin and the No. 2 pin of the first control chip U1 are connected in parallel and then are connected with a first protection circuit, one end of the first protection circuit is connected with the connection point of the No. 3 pin and the No. 2 pin, and the other end of the first protection circuit is grounded. In this embodiment, the first protection circuit adopts the first diode D1, the anode of the first diode D1 is connected to the connection point of the 3 rd pin and the 2 nd pin, and the cathode is grounded, so that the circuit has the function of preventing reverse connection, and the problem of wrong connection of a power line is avoided.
Meanwhile, the 3 rd pin and the 2 nd pin of the first control chip U1 are connected in parallel and then connected to an input power supply through a second diode D2, the anode of the second diode D2 is connected to the connection point of the 3 rd pin and the 2 nd pin, and the cathode is connected to the first input power supply V1. The second diode D2 can keep the voltage across the terminals constant, keeping the supply voltage stable.
The 1 st pin of the first control chip U1 is connected to the first input power V1 through a first resistor R1, and the first resistor R1 is used for limiting current, so as to prevent excessive current.
In this embodiment, the input terminal of the first input power V1 is connected in parallel with a first filter circuit, the first filter circuit is a first capacitor E1, one end of the first capacitor E1 is connected to the first input power V1, the other end is grounded, and the first capacitor E1 is used for filtering out voltage ripples.
In this embodiment, the input end of the first input power source V1 is connected in parallel with a second protection circuit, the second protection circuit is a third resistor R3 and a fourth resistor R4, one end of the third resistor R3 is connected with the first input power source V1, and the other end is grounded; one end of the fourth resistor R4 is connected to the first input power source V1, and the other end is grounded.
In the present embodiment, the first input power V1 and the second input power V2 both have inputs, and one input is on and the other input is on standby. However, in actual use, only one power supply is turned on, and the other power supply is turned off. In the process of verifying the circuit, it is found that when only one path of power supply is input, because the MOS transistor has reverse current, and there is reverse voltage in the other path of MOS transistor protection circuit, in order to eliminate the reverse voltage, the input end of the input power supply is connected in parallel with the second protection circuit, and the reverse voltage can be pulled down to 0V through the third resistor R3 and the fourth resistor R4, so that the potential safety hazard is solved.
Normally, when the input power is 24V, the reverse voltage is about 18V, and even if the power collection point of the control chip is changed from the drain electrode of the NMOS tube to the source electrode, the voltage of about 3V still exists. Therefore, the resistance value of the resistor connected in parallel with the input end of the input power supply is generally selected to be 20K ohms, and the voltage can be pulled down to be 0V.
In this embodiment, the connection method of the other MOS transistor protection circuit is the same, and as shown in fig. 2, the seventh resistor R7, the eighth resistor R8, and the sixth capacitor E6 are all connected in parallel to the input end of the second input power source V2; the second input power supply V2 is connected with the source electrode of the second NMOS tube Q2 and simultaneously connected with the 4 th pin of the second control chip U2, the grid electrode of the second NMOS tube Q2 is connected with the 5 th pin of the second control chip U2, and the drain electrode (D) of the second NMOS tube Q2 is connected with the 6 th pin of the second control chip U2; the 3 rd pin and the 2 nd pin of the second control chip U2 are connected in parallel and then the anode of the third diode D3 is connected to the ground, and the anode of the fourth diode D4 is connected to the input end of the second input power supply V2; the 1 st pin of the second control chip U2 is connected to the input terminal of the second input power V2 through a fifth resistor R5.
The drains of the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected in parallel and output to a load Vout, and the load end is connected in parallel with a second filter circuit. In this embodiment, the second filter circuit includes 4 polar capacitors E2, E3, E4, and E5 connected in parallel, the positive electrode of the limiting capacitor is connected to the load Vout, and the negative electrode is grounded.
In this embodiment, the load end is further connected in parallel with a third protection circuit, the third protection circuit is a TVS tube D5, the negative electrode of the TVS tube D5 is connected to the load Vout, and the positive electrode is grounded to perform overcurrent protection on the load.
The implementation principle of the embodiment is as follows: the voltage between the source electrode and the drain electrode of the MOS tube is monitored by the control unit, and the control unit controls the voltage output to the grid electrode of the MOS tube through the monitored source electrode-drain electrode voltage of the MOS tube, so that the control of the working state of the MOS tube is realized. When two paths of redundant power supplies are input, the output is the power supply with higher power supply voltage, and the other path is in a standby state; when the output power supply fails, the other power supply in the standby state works immediately.
The embodiment of this specific implementation mode is the preferred embodiment of the present invention, not limit according to this the utility model discloses a protection scope, so: all equivalent changes made according to the structure, shape and principle of the utility model are covered within the protection scope of the utility model.
Claims (9)
1. A power supply redundancy circuit comprises at least two paths of input power supplies, wherein each path of input power supply outputs to the same load, and the power supply redundancy circuit is characterized in that: each input power supply is connected with an MOS tube protection circuit, the MOS tube protection circuit comprises an NMOS tube, the source electrode of the NMOS tube is connected with the power input end, the drain electrode of the NMOS tube is connected with a load, and the grid electrode of the NMOS tube is connected with a control unit and used for controlling the on-off of the NMOS tube.
2. The power supply redundancy circuit of claim 1, wherein: the control unit adopts an LM5050MK-1 control chip, a pin 4 of the control chip is connected with a source electrode of an NMOS tube, a pin 5 is connected with a grid electrode of the NMOS tube, a pin 6 is connected with a drain electrode of the NMOS tube, and a pin 3 is grounded after being connected with a pin 2 in parallel.
3. The power supply redundancy circuit of claim 2, wherein: and a No. 3 pin and a No. 2 pin of the control chip are connected in parallel and then are connected with a first protection circuit, one end of the first protection circuit is connected with a connection point of the No. 3 pin and the No. 2 pin, and the other end of the first protection circuit is grounded.
4. The power supply redundancy circuit of claim 2, wherein: the pin 3 and the pin 2 of the control chip are connected in parallel and then are connected to an input power supply through a voltage stabilizing diode, the anode of the voltage stabilizing diode is connected with the connection point of the pin 3 and the pin 2, and the cathode of the voltage stabilizing diode is connected with the input power supply.
5. The power supply redundancy circuit of claim 2, wherein: and the 1 st pin of the control chip is connected with an input power supply through a current-limiting resistor.
6. The power supply redundancy circuit of claim 1, wherein: the input end of the input power supply is connected with a first filter circuit in parallel.
7. The power supply redundancy circuit of claim 1, wherein: the input end of the input power supply is connected with a second protection circuit in parallel, one end of the second protection circuit is connected with the input power supply, and the other end of the second protection circuit is grounded.
8. The power supply redundancy circuit of claim 1, wherein: and the drain stage of the NMOS tube is connected with a second filter circuit in parallel.
9. The power supply redundancy circuit of claim 1, wherein: and the drain of the NMOS tube is connected in parallel with a third protection circuit for protecting a load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021611017.8U CN212909338U (en) | 2020-08-05 | 2020-08-05 | Power supply redundancy circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021611017.8U CN212909338U (en) | 2020-08-05 | 2020-08-05 | Power supply redundancy circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212909338U true CN212909338U (en) | 2021-04-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021611017.8U Active CN212909338U (en) | 2020-08-05 | 2020-08-05 | Power supply redundancy circuit |
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| Country | Link |
|---|---|
| CN (1) | CN212909338U (en) |
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2020
- 2020-08-05 CN CN202021611017.8U patent/CN212909338U/en active Active
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