CN212907708U - Packaging structure of diode - Google Patents
Packaging structure of diode Download PDFInfo
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- CN212907708U CN212907708U CN202022561397.5U CN202022561397U CN212907708U CN 212907708 U CN212907708 U CN 212907708U CN 202022561397 U CN202022561397 U CN 202022561397U CN 212907708 U CN212907708 U CN 212907708U
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Abstract
A diode packaging structure comprises a diode chip to be packaged, wherein a first upper metal layer is arranged on a first surface of the diode chip, a first lower metal layer is arranged on a second surface of the diode chip, and the thicknesses of the first upper metal layer and the first lower metal layer are smaller than 1.5 mm; the surface of the first upper metal layer is provided with a second upper metal layer, and the surface of the first lower metal layer is provided with a second lower metal layer; the thickness of the second upper metal layer is larger than that of the first upper metal layer, and the thickness of the second lower metal layer is larger than that of the first lower metal layer. The design leads out a first metal sheet with proper thickness on the surface of the chip, and after the chip is encapsulated by insulating epoxy resin, a second metal sheet which is beneficial to heat dissipation is welded, so that the influence of metal warpage and stress generated by mutual dragging of metal around the metal on the chip in welding or other processing processes can be avoided, and the heat dissipation performance of the device is met.
Description
Technical Field
The utility model relates to a semiconductor package field, concretely relates to packaging structure of diode.
Background
Different doping processes are adopted, and a P-type semiconductor and an N-type semiconductor are manufactured on the same semiconductor (usually silicon or germanium) substrate through diffusion, and space charge regions called PN junctions are formed at the interfaces of the P-type semiconductor and the N-type semiconductor. PN junctions have unidirectional conductivity and are a property utilized by many devices in electronics, and commonly used semiconductor devices such as semiconductor diodes are based on PN junctions. In the preparation application process, in order to improve the life-span of semiconductor diode device, diode device's packaging structure should be able to have good radiating effect, usually after the chip preparation is accomplished, can adopt the great and thicker copper product of area to reach the heat dissipation purpose as the conducting material of chip electrode, and the chip is when accomplishing the welding of the thick big copper product, the material leftover bits that need process are more, not only lead to material cost to increase, often because warpage or shear muscle stress are too big in thick copper material packaging process moreover, the chip damages easily, make the device invalid.
Therefore, it is desirable to provide a diode package structure, which can reduce the damage of the chip caused by the processing stress during the packaging process and improve the heat dissipation capability of the product.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the main technical problem who solves provides a packaging structure of diode, makes it can reduce the produced stress in the packaging process and to the damage of chip, improves the heat dispersion of this device simultaneously.
According to a first aspect, an embodiment provides a diode package structure, including:
the diode chip comprises a first surface and a second surface opposite to the first surface, wherein a groove area is formed around the first surface or the second surface;
the first surface of the diode chip is provided with a first upper metal layer, the second surface of the diode chip is provided with a first lower metal layer, and the thicknesses of the first upper metal layer and the first lower metal layer are smaller than 1.5 mm;
an encapsulating layer is arranged around the diode chip, the first upper metal layer and the first lower metal layer, and the encapsulating layer is made of an insulating material;
the surface of the first upper metal layer is provided with a second upper metal layer, and the surface of the first lower metal layer is provided with a second lower metal layer; the thickness of the second upper metal layer is larger than that of the first upper metal layer, and the thickness of the second lower metal layer is larger than that of the first lower metal layer;
and electrode pins are respectively led out of the second upper metal layer and the second lower metal layer and are used for being connected with an external circuit.
In some embodiments, the area of the second upper metal layer is larger than the area of the first upper metal layer, and the area of the second lower metal layer is larger than the area of the first lower metal layer.
In some embodiments, the first upper metal layer and the first surface have a solder layer therebetween, and the first lower metal layer and the second surface have a solder layer therebetween, wherein the solder layer is a tin-lead alloy or a tin-lead-silver alloy.
In some embodiments, the first upper metal layer and the first lower metal layer are copper particles, silver-plated copper particles, molybdenum sheets, or valveable metal sheets.
In some embodiments, the area of the first upper metal layer is smaller than the area of the first lower metal layer; the area of the second upper metal layer is smaller than that of the second lower metal layer.
In some embodiments, the second upper metal layer and the second lower metal layer are less than 3mm thick.
In some embodiments, the encapsulating layer is an epoxy, silicone grease, or silicone rubber.
In some embodiments, the first upper metal layer and the first lower metal layer have a thickness of 0.2mm to 1.5 mm.
In some embodiments, the first upper metal layer and the first lower metal layer are square with sides of 6mm to 23 mm.
In some embodiments, the first surface and the second surface each have a trench region around the periphery.
According to the packaging structure of the diode in the embodiment, the first metal sheet with proper thickness is led out from the surface of the chip in the design, the first metal sheet is equivalent to a metal layer playing a transition role, the metal layer is subjected to small stress during manufacturing, so that the pulling stress of the chip can be reduced, after the chip is encapsulated by insulating epoxy resin, the second metal sheet which is beneficial to heat dissipation is welded, so that the influence of the warping of copper grains and the mutual pulling stress of copper materials on the chip during welding or other processing can be avoided, and the heat dissipation function of a device is realized.
Drawings
Fig. 1 is a schematic diagram of a diode chip according to an embodiment of the present invention;
fig. 2 is a top view of a diode chip according to an embodiment of the present invention;
fig. 3 is a schematic view of a diode package structure according to an embodiment of the present invention;
fig. 4 is a schematic view of a diode package structure according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Analysis shows that the larger the required force is in processing, the worse the uniformity of stress is, the larger the total deformation of copper materials cut by punching is, and the warping is easy to generate; and the connected metal can be mutually pulled during processing, thereby easily influencing the chip.
The embodiment of the utility model provides an in, be connected with the first metal level that thickness is less than 1.5mm earlier on the surface of chip, weld the second metal level on the first metal level again, the thickness of this second metal level can be greater than first metal level, the transition sheetmetal of suitable thickness is made to the heat conduction sheetmetal that this design will be drawn forth on the chip surface, after the chip carries out insulating epoxy encapsulation, weld last one again and do benefit to radiating second sheetmetal, the stress that produces when dragging mutually between metal warpage and its metal material on every side in can avoiding welding or other course of working like this causes the influence to the chip, can also realize the heat dissipation function of device simultaneously.
Referring to fig. 1 to 4, the present embodiment provides a diode package structure, including a diode chip 100 to be packaged, where the diode chip 100 includes a first surface 101 and a second surface 102 opposite to the first surface 101, and a trench region 110 is formed around the first surface 101 or the second surface 102.
Referring to fig. 1, in the present embodiment, the trench regions 110 are formed around the first surface 101 and the second surface 102, that is, a package of a diode with double mesas is formed; in some embodiments, the trench region 110 is only on one of the first surface 101 or the second surface 102, i.e., a package of a single mesa diode is formed, the package structure referring to fig. 4.
The first surface 101 of the diode chip 100 has a first upper metal layer 201 thereon, the second surface 102 has a first lower metal layer 202 thereon, and the thicknesses of the first upper metal layer 201 and the first lower metal layer 202 are less than 1.5 mm.
The diode chip 100 may be a TVS, a semiconductor discharge tube, or a general rectifying diode chip.
In this embodiment, the first upper metal layer 201 is soldered on the first surface 101, a solder layer is disposed between the first upper metal layer 201 and the first surface 101, the first lower metal layer 202 is soldered on the second surface 102, and a solder layer is disposed between the first lower metal layer 202 and the second surface 102.
The solder layer material in this embodiment may be a tin-lead alloy. In other embodiments, the material of the solder layer may also be tin-lead-silver alloy.
In some embodiments, the thicknesses of the first upper metal layer 201 and the first lower metal layer 202 are 0.2mm to 1.5mm, the thicknesses of the first metal layers (i.e., the first upper metal layer and the first lower metal layer) are too small, and when the thicknesses of the first metal layers are less than 0.2mm, the welding of the second metal layers (i.e., the second upper metal layer and the second lower metal layer) is not facilitated, so that the chip is prevented from being damaged by stress due to too large thicknesses of the second metal layers, and when the thicknesses of the first metal layers (i.e., the first upper metal layer and the first lower metal layer) are too large, the chip is easily damaged by stress when the thicknesses of the first metal layers are greater.
In this embodiment, the first upper metal layer 201 and the first lower metal layer 202 are square, the side length is 6mm to 23mm, and the first metal layer (i.e. the first upper metal layer and the first lower metal layer) is not too large, so as to avoid the problem that the area is too large and large stress is generated when the first metal layer contacts with a chip, and if the area is too small, the process difficulty is increased, which is not favorable for industrial processing.
An encapsulating layer 200 is disposed around the diode chip 100, the first upper metal layer 201, and the first lower metal layer 202, and the encapsulating layer 200 is an insulating material.
In this embodiment, the encapsulating layer 200 may be an epoxy resin, and is used for insulating and protecting the diode chip. In other embodiments, the encapsulating layer 200 may also be a silicone grease material, or a silicone rubber material.
The surface of the first upper metal layer 201 is provided with a second upper metal layer 301, and the surface of the first lower metal layer 202 is provided with a second lower metal layer 302; the thickness of the second upper metal layer is larger than that of the first upper metal layer, and the thickness of the second lower metal layer is larger than that of the first lower metal layer.
When the metal electrode is manufactured on the diode chip 100, a first metal layer (i.e., a first upper metal layer and a first lower metal layer) with a smaller thickness is manufactured at first, and researches show that when the metal layer with the thickness of less than 1.5mm is manufactured on the basis of the existing process, because metal particles are easier to process, such as copper particles, silver-plated copper particles, molybdenum sheets or foldable metal sheets and other materials are punched, the stress uniformity is better, and the deformation is smaller, so that a warping region can be prevented from being generated on the first metal layer, and therefore, the force of mutual pulling in the subsequent packaging and packaging processes is smaller, so that the stress uniformity when the first metal layer is in contact with the chip is better, and the possibility of chip damage is reduced; when the second metal layer (namely the second upper metal layer and the second lower metal layer) is welded on the first metal layer, the heat dissipation performance of the device can be further improved, and meanwhile, the warping area of the chip caused by metal contact is avoided, so that the influence of warping generated in the metal in welding or other processing processes and stress of mutual pulling of the metal around the warping area on the chip can be avoided, and the heat dissipation requirement is met.
In some embodiments, the first upper metal layer 201 and the first lower metal layer 202 are copper particles, silver-plated copper particles, molybdenum sheets, or valveable metal sheets.
In this embodiment, electrode pins are respectively led out from the second upper metal layer 301 and the second lower metal layer 302 for connecting with an external circuit.
In some embodiments, the area of the second upper metal layer 301 is larger than the area of the first upper metal layer 201, and the area of the second lower metal layer 302 is larger than the area of the first lower metal layer 301. When the area of the second metal layer is larger than that of the first metal layer, the heat dissipation performance of the diode chip is better facilitated, and meanwhile, the packaged device is easier to attach to a PCB (printed circuit board) to be connected with an external circuit.
In some embodiments, the area of the first upper metal layer 201 is smaller than the area of the first lower metal layer 202; the area of the second upper metal layer 301 is smaller than that of the second lower metal layer 302. Because the area of the upper metal layer is smaller than that of the lower metal layer on the same chip, if the electrode is led out from the side with small area to the side with large area, the electrode is more stable when being installed on an external circuit board.
In this embodiment, the thicknesses of the second upper metal layer 301 and the second lower metal layer 302 are less than 3mm, the larger the sum of the size and the thickness of the first metal layer and the second metal layer is, the more favorable the heat dissipation of the chip is, but the sum of the thicknesses is not too large, and when the thickness of the first metal layer is 1.5mm at most, the thickness of the second metal layer is not more than 3mm, so as to ensure the safety of the chip.
The diode packaging structure provided in the embodiment can reduce the loss of copper materials, simultaneously reduce the damage to the chip caused by the processing stress in the packaging process, and improve the heat dissipation capacity of the product.
It is right to have used specific individual example above the utility model discloses expound, only be used for helping to understand the utility model discloses, not be used for the restriction the utility model discloses. To the technical field of the utility model technical personnel, the foundation the utility model discloses an idea can also be made a plurality of simple deductions, warp or replacement.
Claims (10)
1. An encapsulation structure of a diode, comprising:
the diode chip comprises a first surface and a second surface opposite to the first surface, wherein a groove area is formed around the first surface or the second surface;
the first surface of the diode chip is provided with a first upper metal layer, the second surface of the diode chip is provided with a first lower metal layer, and the thicknesses of the first upper metal layer and the first lower metal layer are smaller than 1.5 mm;
an encapsulating layer is arranged around the diode chip, the first upper metal layer and the first lower metal layer, and the encapsulating layer is made of an insulating material;
the surface of the first upper metal layer is provided with a second upper metal layer, and the surface of the first lower metal layer is provided with a second lower metal layer; the thickness of the second upper metal layer is larger than that of the first upper metal layer, and the thickness of the second lower metal layer is larger than that of the first lower metal layer;
and electrode pins are respectively led out of the second upper metal layer and the second lower metal layer and are used for being connected with an external circuit.
2. The package structure of claim 1, wherein an area of the second upper metal layer is greater than an area of the first upper metal layer, and an area of the second lower metal layer is greater than an area of the first lower metal layer.
3. The package structure of claim 1, wherein the first upper metal layer and the first surface have a solder layer therebetween, and the first lower metal layer and the second surface have a solder layer therebetween, the solder layer being a tin-lead alloy or a tin-lead-silver alloy.
4. The package structure of claim 1, wherein the first upper metal layer and the first lower metal layer are copper particles, silver-plated copper particles, molybdenum sheets, or kovar sheets.
5. The package structure of claim 1, wherein an area of the first upper metal layer is smaller than an area of the first lower metal layer; the area of the second upper metal layer is smaller than that of the second lower metal layer.
6. The package structure of claim 1, wherein the thickness of the second upper metal layer and the second lower metal layer is less than 3 mm.
7. The package structure of claim 1, wherein the encapsulation layer is an epoxy, silicone grease, or silicone rubber.
8. The package structure of claim 1, wherein the first upper metal layer and the first lower metal layer have a thickness of 0.2mm to 1.5 mm.
9. The package structure of claim 8, wherein the first upper metal layer and the first lower metal layer are square with sides of 6mm to 23 mm.
10. The package structure of claim 9, wherein the first surface and the second surface each have a trench region around the periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022561397.5U CN212907708U (en) | 2020-11-09 | 2020-11-09 | Packaging structure of diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022561397.5U CN212907708U (en) | 2020-11-09 | 2020-11-09 | Packaging structure of diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212907708U true CN212907708U (en) | 2021-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202022561397.5U Active CN212907708U (en) | 2020-11-09 | 2020-11-09 | Packaging structure of diode |
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| CN (1) | CN212907708U (en) |
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- 2020-11-09 CN CN202022561397.5U patent/CN212907708U/en active Active
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