CN212873482U - Independently controllable computer motherboard - Google Patents
Independently controllable computer motherboard Download PDFInfo
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- CN212873482U CN212873482U CN202021396685.3U CN202021396685U CN212873482U CN 212873482 U CN212873482 U CN 212873482U CN 202021396685 U CN202021396685 U CN 202021396685U CN 212873482 U CN212873482 U CN 212873482U
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Abstract
The utility model discloses an autonomous controllable computer mainboard, which comprises a substrate, a substrate integrated processor, a COM-E board-to-board connector, a memory module, a storage module and a power module; the processor is an LS1026 or LS1046 processor; the LS1026 or LS1046 processor is respectively connected with the memory module and the storage module; the LS1026 or LS1046 processor is connected with the power supply module through a COM-E board-to-board connector; the interface function of the LS1026 or LS1046 processor is brought out through the COM-E board-to-board connector. The performance of the LS1026 or LS1046 processor is fully exerted, the method has the characteristics of automatic controllability, safety, reliability, high integration level and the like, the types and the number of interfaces are expanded, different application development requirements are met, and the method has good compatibility.
Description
Technical Field
The utility model relates to the field of electronic technology, especially, relate to an independently controllable computer motherboard.
Background
With the development of electronic technology, various embedded devices are increasing day by day, a traditional single chip microcomputer system cannot meet the requirements of a plurality of industries and applications, the existing embedded type combines computer software and hardware technology, communication technology and microelectronic technology, a user can directly embed a corresponding microprocessor into a specific application system according to specific application requirements, the microprocessor is applied to each industry, functions are complex, a plurality of practical application requirements have high real-time performance, equipment with an operating system is needed to meet the industrial applications, but the hardware system with the operating system is high in design difficulty, high in research and development threshold and long in research and development time, and the existing market requirements are difficult to meet. The mainboard in the existing market has different technical requirements, interface types, quantity and the like in an application field, so that the interface provided by the existing mainboard cannot meet the requirement of expansion, cannot adapt to the product requirements of more different functions, and has high development difficulty and poorer flexibility.
Disclosure of Invention
The utility model provides an independently controllable computer motherboard to solve one or more technical problem that exist among the prior art, provide a profitable selection or create the condition at least.
In a first aspect, an embodiment of the present invention provides an autonomously controllable computer motherboard, which includes a substrate, a substrate integrated processor, a COM-E board-to-board connector, a memory module, a storage module, and a power module; the storage module comprises a first storage module and a second storage module; the processor is an LS1026 or LS1046 processor; the COM-E board-to-board connector is provided with a first RGMII interface end, a second RGMII interface end, a plurality of paths of SGMII interface ends, a plurality of paths of USB interface ends, a first PCI-Ex1 interface end, a second PCI-Ex1 interface end, a plurality of paths of serial port ends, an SPI interface end, a plurality of paths of GPIO interface ends, an SATA interface end, an I2C interface end and a power supply interface end;
the DDR4 interface of the LS1026 or LS1046 processor is connected with the memory module;
the SDHC interface of the LS1026 or LS1046 processor is connected with the first storage module;
the QSPI _ A, QSPI _ B interface of the LS1026 or LS1046 processor is connected with the second storage module;
the LS1026 or LS1046 processor is connected with a COM-E board-to-board connector, and the LS1026 or LS1046 processor is connected with a power supply module through the power supply interface end; the interface function of the LS1026 or LS1046 processor is led out through a COM-E board-to-board connector;
the EC1/2 interface of the LS1026 or LS1046 processor is connected with the first RGMII interface end and the second RGMII interface end;
the SerDes1_ A/B/C/D interface and SerDes2_ B interface of the LS1026 or LS1046 processor are connected with the SGMII interface ends;
the USB interface of the LS1026 or LS1046 processor is connected with the plurality of USB interface ends;
the SerDes2_ A & C interface of the LS1026 or LS1046 processor is connected with a first PCI-Ex1 interface end and a second PCI-Ex1 interface end;
the DUART interface and the LPUART interface of the LS1026 or LS1046 processor are connected with the multi-path serial port end;
the SPI interface of the LS1026 or LS1046 processor is connected with the SPI interface end;
the GPIO interface of the LS1026 or LS1046 processor is connected with the multi-path GPIO interface end;
the SerDes2_ D interface of the LS1026 or LS1046 processor is connected with the SATA interface end;
the IIC interface of the LS1026 or LS1046 processor is connected with the I2C interface end.
Further, the memory module comprises 4 DDR4 memory particles.
Furthermore, the model numbers of the DDR4 memory particles are all MT40A1G8WE, and the total memory capacity of the memory module is 2GB or 4 GB.
Further, the serial ports comprise 3 LDPUART serial ports and 1 debugging serial port for RS232, an LPUART interface of the LS1026 or LS1046 processor is connected with the 3 LDPUART serial ports, and a DUART interface of the LS1026 or LS1046 processor is connected with the RS232 debugging serial port.
Further, the first memory module is an EMMC of 16 GB.
Further, the second storage module comprises a first SPINOR FLASH and a second SPINOR FLASH, the QSPI _ a interface of the LS1026 or LS1046 processor is connected with the first SPINOR FLASH, and the QSPI _ B interface of the LS1026 or LS1046 processor is connected with the second SPINOR FLASH.
Further, the capacity of the first SPINOR FLASH was 32MB, and the capacity of the second SPINOR FLASH was 32MB or 64 MB.
Further, the multiple USB interface terminals include 2 USB3.0 interface terminals and 1 USB2.0 terminal.
Further, USB3.0 is HOST mode, and USB2.0 is OTG or HOST mode.
Further, the power supply module comprises an AP3598AFNTR-G1 chip, and the LS1026 or LS1046 processor is connected with the AP3598AFNTR-G1 chip through the power supply interface terminal.
The utility model discloses following beneficial effect has at least: the performance of the LS1026 or LS1046 processor is fully exerted, the LS1026 or LS1046 processor, the COM-E board-to-board connector, the memory module, the storage module and the power module are integrated on the mainboard, the advantages of automatic controllability, safety, reliability, high integration level and the like are achieved, the functional interface of the LS1026 or LS1046 processor is led out through the COM-E board-to-board connector, the type and the number of the interface are expanded, different application development requirements are met, and good compatibility is achieved.
Drawings
The accompanying drawings are included to provide a further understanding of the technical solutions of the present invention, and are incorporated in and constitute a part of this specification, together with the embodiments of the present invention for explaining the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.
Fig. 1 is a logic plan view front of an autonomously controllable computer motherboard according to the present invention.
Fig. 2 is a logic plan view back of an autonomously controllable computer motherboard provided by the present invention.
Fig. 3 is a functional schematic diagram of an interface of an LS1026 or LS1046 processor provided by the present invention.
Description of reference numerals: the memory chip comprises a 1-LS1026 or LS1046 processor, a 2-first DDR4 memory particle, a 3-second DDR4 memory particle, a 4-EMMC, a 5-first SPINOR FLASH, a 6-second SPINOR FLASH, a 7-power management chip, an 8-COM-E board-to-board connector, a 9-third DDR4 memory particle and a 10-fourth DDR4 memory particle.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
It should be noted that although the functional modules are divided in the system diagram, in some cases, the functional modules may be divided differently from the modules in the system. The terms first, second and the like in the description and in the claims, and the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Fig. 1-2 provide a logical plan view of an autonomously controllable computer motherboard. The autonomously controllable computer motherboard comprises a baseboard, as shown in fig. 1, the front side of the baseboard comprises an LS1026 or LS1046 processor 1, a first DDR4 memory granule 2, a second DDR4 memory granule 3, an EMMC4, a first SPINOR FLASH5, a second SPINOR FLASH6 and a power management chip 7; as shown in fig. 2, the back side of the substrate includes a COM-E board-to-board connector 8, a third DDR4 memory particle 9 and a fourth DDR4 memory particle 10. FIG. 3 is a functional diagram of an interface of an LS1026 or LS1046 processor, and as shown in FIG. 3, the LS1026 or LS1046 processor has a DDR4 interface, an SDHC interface QSPI _ A interface, a QSPI _ B interface, an EC1/2 interface, a SerDes1_ A/B/C/D interface, a SerDes2_ B interface, a USB interface, a SerDes2_ A & C interface, a SerDes2_ D interface, a DUART interface, an LPUART interface, an IIC interface, a USB interface, an SPI interface and a GPIO interface. The LS1026 or LS1046 processor also includes a power interface (not shown in FIG. 3).
The device comprises a substrate integrated processor, a COM-E board-to-board connector 8, a memory module, a storage module and a power module; the storage module comprises a first storage module and a second storage module; the processor is an LS1026 or LS1046 processor 1; the COM-E board-to-board connector 8 is provided with a first RGMII interface end, a second RGMII interface end, a plurality of paths of SGMII interface ends, a plurality of paths of USB interface ends, a first PCI-Ex1 interface end, a second PCI-Ex1 interface end, a plurality of paths of serial ports, an SPI interface end, a plurality of paths of GPIO interface ends, an SATA interface end, an I2C interface end and a power supply interface end; the LS1026 processor is a dual-core processor, and the main frequency is 1.2-1.6 GHz; the LS1046 processor is a four-core processor with a main frequency of 1.2-1.6 GHz; the mainboard conforms to the COM-E2.0 specification, is compatible with the standard pin definition of COM Express Type10, and has the size of 55mm multiplied by 84 mm.
The DDR4 interface of the LS1026 or LS1046 processor 1 is connected with the memory module;
the SDHC interface of the LS1026 or LS1046 processor 1 is connected with the first storage module;
QSPI _ A interface and QSPI _ B interface of LS1026 or LS1046 processor 1 are connected with the second memory module;
the LS1026 or LS1046 processor 1 is connected with the COM-E board-to-board connector 8, and the LS1026 or LS1046 processor 1 is connected with the power supply module through the power supply interface end; the interface function of the LS1026 or LS1046 processor 1 is led out through a COM-E board-to-board connector;
the EC1/2 interface of the LS1026 or LS1046 processor 1 is connected with the first RGMII interface terminal and the second RGMII interface terminal;
the SerDes1_ A/B/C/D interface and the SerDes2_ B interface of the LS1026 or LS1046 processor 1 are connected with the SGMII interfaces;
the USB interface of the LS1026 or LS1046 processor 1 is connected with the plurality of USB interface terminals;
the SerDes2_ A & C interface of the LS1026 or LS1046 processor 1 is connected with a first PCI-Ex1 interface end and a second PCI-Ex1 interface end;
the DUART interface and the LPUART interface of the LS1026 or LS1046 processor 1 are connected with the multi-path serial port;
the SPI interface of the LS1026 or LS1046 processor 1 is connected with the SPI interface end;
the GPIO interface of the LS1026 or LS1046 processor 1 is connected with the multi-path GPIO interface end;
the SerDes2_ D interface of the LS1026 or LS1046 processor 1 is connected with the SATA interface end;
the IIC interface of LS1026 or LS1046 processor 1 interfaces with the I2C interface.
Specifically, the memory module comprises 4 pieces of onboard DDR4 memory particles, which are more reliable and stable than a memory slot, and the 4 pieces of onboard DDR4 memory particles are a first DDR4 memory particle 2, a second DDR4 memory particle 3, a third DDR4 memory particle 9 and a fourth DDR4 memory particle 10, respectively. The model number of DDR4 memory particles is MT40A1G8WE, and the total memory capacity of the memory module is 2GB or 4 GB.
The first memory module is a 16GB EMMC. The 16GB EMMC may be connected through the LS1026 or LS1046 processor's SDHC interface. The second storage module comprises a first SPINOR FLASH5 and a second SPINOR FLASH6, the QSPI _ A interface of the LS1026 or LS1046 processor is connected with the first SPINOR FLASH5, and the QSPI _ B interface of the LS1026 or LS1046 processor is connected with the second SPINOR FLASH 6. And the system also has a 1-way SATA interface and supports high-capacity SSD storage.
In an embodiment, the plurality of serial ports include 3 LDPUART serial ports and 1 RS232 debugging serial port, the LPUART interface of the LS1026 or LS1046 processor is connected with the 3 LDPUART serial ports, and the DUART interface of the LS1026 or LS1046 processor is connected with the RS232 debugging serial port.
In one embodiment, the multiple USB interface terminals include a 2-way USB3.0 interface terminal and a 1-way USB2.0 interface terminal. USB3.0 is HOST mode, USB2.0 is OTG or HOST mode.
In one embodiment, the power supply module comprises an AP3598AFNTR-G1 chip, and the LS1026 or LS1046 processor is connected with the AP3598AFNTR-G1 chip through the power supply interface terminal. The power module may provide a DC 12V voltage to the processor.
In one embodiment, the multiple SGMII interface terminals are 5 SGMII interface terminals, the multiple GPIO interface terminals are 8 GPIO interface terminals, and the 8 GPIOs can be programmed.
As shown in fig. 1-2, the LS1026 or LS1046 processor 1, the first DDR4 memory particle 2, the second DDR4 memory particle 3, the EMMC4, the first SPINOR FLASH5, the second SPINOR FLASH6 and the power management chip 7 are soldered on the front surface of the substrate, the LS1026 or LS1046 processor 1 is in the middle of the front surface of the substrate, the COM-E board-to-board connector 8, the third DDR4 memory particle 9 and the fourth DDR4 memory particle 10 are soldered on the back surface of the substrate, the COM-E board-to-board connector 8 is at the edge of the left side of the back surface of the substrate, so that the external expansion is facilitated, the layout of each module is reasonable, and the module is more convenient for different application developments.
On a carrier plate which accords with a PICMG COM Express specification and a COM Express Type10, 2 paths of RGMII and 5 paths of SGMII channels can be designed and led out to be connected with network equipment, 3 paths of LPUART serial ports are connected with serial port equipment, 1 path of SPI is connected with SPI equipment, 1 path of I2C is connected with I2C equipment, and 8 paths of GPIOs can be programmed and controlled.
The utility model discloses a mainboard adopts the design of full table subsides, has characteristics such as independently controllable, safe and reliable, integrated level height, and the function of LS1026 or LS1046 treater is drawn forth the board connector through COM-E board, has expanded the type and the quantity of interface, adapts to different application development demands, has good compatibility, but wide application in fields such as national defense, scientific research, medical treatment, communication.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are intended to be included within the scope of the present invention defined by the appended claims.
Claims (10)
1. An autonomous controllable computer mainboard is characterized by comprising a substrate, wherein the substrate integrates a processor, a COM-E board-to-board connector, a memory module, a storage module and a power module; the storage module comprises a first storage module and a second storage module; the processor is an LS1026 or LS1046 processor; the COM-E board-to-board connector is provided with a first RGMII interface end, a second RGMII interface end, a plurality of paths of SGMII interface ends, a plurality of paths of USB interface ends, a first PCI-Ex1 interface end, a second PCI-Ex1 interface end, a plurality of paths of serial port ends, an SPI interface end, a plurality of paths of GPIO interface ends, an SATA interface end, an I2C interface end and a power supply interface end;
the DDR4 interface of the LS1026 or LS1046 processor is connected with the memory module;
the SDHC interface of the LS1026 or LS1046 processor is connected with the first storage module;
the QSPI _ A, QSPI _ B interface of the LS1026 or LS1046 processor is connected with the second storage module;
the LS1026 or LS1046 processor is connected with a COM-E board-to-board connector, and the LS1026 or LS1046 processor is connected with a power supply module through the power supply interface end; the interface function of the LS1026 or LS1046 processor is led out through a COM-E board-to-board connector;
the EC1/2 interface of the LS1026 or LS1046 processor is connected with the first RGMII interface end and the second RGMII interface end;
the SerDes1_ A/B/C/D interface and SerDes2_ B interface of the LS1026 or LS1046 processor are connected with the SGMII interface ends;
the USB interface of the LS1026 or LS1046 processor is connected with the plurality of USB interface ends;
the SerDes2_ A & C interface of the LS1026 or LS1046 processor is connected with a first PCI-Ex1 interface end and a second PCI-Ex1 interface end;
the DUART interface and the LPUART interface of the LS1026 or LS1046 processor are connected with the multi-path serial port end;
the SPI interface of the LS1026 or LS1046 processor is connected with the SPI interface end;
the GPIO interface of the LS1026 or LS1046 processor is connected with the multi-path GPIO interface end;
the SerDes2_ D interface of the LS1026 or LS1046 processor is connected with the SATA interface end;
the IIC interface of the LS1026 or LS1046 processor is connected with the I2C interface end.
2. The motherboard of claim 1, wherein the memory module comprises 4 DDR4 memory die.
3. The motherboard of claim 2, wherein the DDR4 memory granules are all MT40A1G8WE, and the total memory capacity of the memory module is 2GB or 4 GB.
4. The mainboard of claim 1, wherein the plurality of serial ports comprise 3 LDPUART serial ports and 1 RS232 debugging serial port, the LPUART interface of the LS1026 or LS1046 processor is connected with the 3 LDPUART serial ports, and the DUART interface of the LS1026 or LS1046 processor is connected with the RS232 debugging serial port.
5. The motherboard of claim 1, wherein the first memory module is a 16GB EMMC.
6. The motherboard of claim 1, wherein the second storage module comprises a first SPINOR FLASH and a second SPINOR FLASH, wherein the QSPI _ a interface of the LS1026 or LS1046 processor is connected to the first SPINOR FLASH, and the QSPI _ B interface of the LS1026 or LS1046 processor is connected to the second SPINOR FLASH.
7. The motherboard of claim 1, wherein the first SPINOR FLASH has a capacity of 32MB and the second SPINOR FLASH has a capacity of 32MB or 64 MB.
8. The motherboard of claim 1, wherein the multi-way USB interface port comprises a 2-way USB3.0 interface port and a 1-way USB2.0 port.
9. The motherboard of claim 6 wherein USB3.0 is HOST mode and USB2.0 is OTG or HOST mode.
10. The motherboard of claim 1, wherein the power module comprises an AP3598AFNTR-G1 chip, and the LS1026 or LS1046 processor is connected to the AP3598AFNTR-G1 chip through the power interface terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021396685.3U CN212873482U (en) | 2020-07-15 | 2020-07-15 | Independently controllable computer motherboard |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021396685.3U CN212873482U (en) | 2020-07-15 | 2020-07-15 | Independently controllable computer motherboard |
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| Publication Number | Publication Date |
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| CN212873482U true CN212873482U (en) | 2021-04-02 |
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| CN202021396685.3U Active CN212873482U (en) | 2020-07-15 | 2020-07-15 | Independently controllable computer motherboard |
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