CN212850460U

CN212850460U - Novel frequency divider with enable control end

Info

Publication number: CN212850460U
Application number: CN201922187588.7U
Authority: CN
Inventors: 朱晓锐; 章国豪; 刘祖华
Original assignee: Guangzhou Suiyuan Microelectronics Technology Co ltd; Dongguan Sailwell Electronic Technology Co ltd
Current assignee: Guangzhou Suiyuan Microelectronics Technology Co ltd; Dongguan Sailwell Electronic Technology Co ltd
Priority date: 2019-12-09
Filing date: 2019-12-09
Publication date: 2021-03-30
Anticipated expiration: 2029-12-09

Abstract

A novel frequency divider with an enable control end consists of a clock circuit, a main loop and the enable control end, and whether the frequency divider works or not is realized by controlling the high ground level of the enable end. Optimize clock circuit module for add the clock signal at transmission gate both ends and match more, improved the highest operating frequency of the input signal that the circuit can handle, 1 the utility model provides a technical scheme that its technical problem adopted is: a novel enabling control circuit is designed by adopting a core international (SMIC) process and optimizing a clock module and a main loop module of the circuit. 2. The beneficial effects of the utility model are that, improved the highest operating frequency of the input signal that the circuit can be handled, optimized the phase noise performance of circuit, through using neotype enable control circuit for the circuit consumption is zero when the messenger turns off.

Description

Novel frequency divider with enable control end

Technical Field

The utility model belongs to the technical field of the radio frequency transceiver, specifically be a novel two frequency dividers of area enable control end.

Background

Because a frequency synthesizer is required in the transceiver to provide an up-conversion clock signal and a down-conversion clock signal, or a low-frequency clock signal is provided for a digital-to-analog converter and an analog-to-digital converter, the phase-locked loop frequency synthesizer has the characteristics of stability, low phase noise and the like and is widely adopted.

As shown in fig. 1, the whole rf transceiver system must provide the clock frequency of up-conversion and down-conversion by the frequency synthesizer, or provide a stable low-noise low-frequency signal to the digital-analog mixer and the analog-digital mixer, and the pll frequency synthesizer is the best choice, and the pll frequency synthesizer stabilizes the clock frequency by negative feedback, and can reduce the phase noise well.

In a multi-mode multi-band radio frequency transceiver, a phase-locked loop frequency synthesizer is used to provide a stable, low phase noise clock for the system as well as for the digital-to-analog converter and the analog-to-digital converter. The phase-locked loop frequency synthesizer module generally adopts a classical Fractional-N architecture with delta-sigma modulation, a frequency divider is added behind a voltage-controlled oscillator to divide the frequency of an output signal, and a low-frequency clock signal is transmitted to a digital-to-analog converter and an analog-to-digital converter.

The reference clock is phase compared with the frequency of the VCO after frequency division, which is implemented as a simple exclusive or gate. The result after the phase comparison is passed through a third order low pass passive filter as the control voltage for the VCO. The VCO generates an oscillation frequency required for output based on the control voltage. On the feedback path, after the output clock of the VCO passes through the frequency divider, one path is output to the phase comparator PD, and the other path is output to the Delta Sigma modulator as a control clock for frequency-divided signal output. The whole Delta-Sigma modulator is comprehensively realized by a digital circuit, so that the portability of the design is improved, and the complexity of the realization of the whole system is reduced. The clock divider (clock divider) divides the frequency of the signal output by the pll and outputs a low frequency clock signal to the adc and the dac.

Since the clock signal is not required to be provided to the digital-to-analog converter and the analog-to-digital converter all the time, the clock frequency division module must be controlled by an enable (enable) signal, and when the enable signal is at a high level, the clock frequency division module normally operates, and when the enable signal is at a low level, the clock frequency division module is turned off.

As shown in fig. 3, the proposed divide-by-two circuit with an enable terminal is provided, in which a two-input and gate is directly connected to an output terminal of the divide-by-two circuit, and then a final signal is output. The circuit does realize the function of enabling control, but when the circuit is turned off, the frequency divider is actually operated, only the output end is in a direct current low level, so that the power consumption is large when the circuit is turned off, and when the circuit is turned off, the phase noise of the signal is greatly reduced on a signal path.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

The utility model provides a not enough to prior art, the utility model provides a novel two frequency dividers of area enable control end crosses to improve the optimization to the circuit, has improved the highest operating frequency of the input signal that the circuit can handle, has optimized the phase noise performance of circuit to make the consumption of circuit be zero when the messenger enables the end and turn-offs.

(II) technical scheme

In order to achieve the above object, the utility model provides a following technical scheme: a novel frequency divider with an enable control end consists of a clock circuit, a main loop and the enable control end, and whether the frequency divider works or not is realized by controlling the high ground level of the enable end.

In a further improvement, the clock circuit module is optimized, so that clock signals added at two ends of the transmission gate are more matched, and the highest working frequency of input signals which can be processed by the circuit is improved.

Further improved, the main loop of the circuit is optimized, the number of stages of inverters in the loop is reduced, and the highest working frequency of input signals capable of being processed by the circuit is improved.

In a further improvement, a novel enable control circuit is adopted, so that the turn-off circuit does not appear on a transmission path of a signal, and the phase noise performance of the signal is not reduced.

In a further improvement, a novel enabling control circuit is adopted, and when the enabling end is zero, the power supply of the circuit is turned off, so that the power consumption of the circuit is zero when the circuit is turned off.

(III) advantageous effects

Compared with the prior art, the utility model provides a novel two frequency dividers of area messenger's control end possesses following beneficial effect:

1. the utility model provides a technical scheme that its technical problem adopted is: a novel enabling control circuit is designed by adopting a core international (SMIC) process and optimizing a clock module and a main loop module of the circuit.

2. The beneficial effects of the utility model are that, improved the highest operating frequency of the input signal that the circuit can be handled, optimized the phase noise performance of circuit, through using neotype enable control circuit for the circuit consumption is zero when the messenger turns off.

Drawings

The present invention will be further explained with reference to the drawings and examples.

Fig. 1 is a radio frequency transceiver system.

Fig. 2 is a phase-locked loop system architecture.

Fig. 3 is a proposed frequency divider with an enable control terminal.

Fig. 4 is a frequency divider with an enable control terminal proposed by this patent.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-4, the present invention provides a technical solution: a novel frequency divider with an enable control end consists of a clock circuit, a main loop and the enable control end, and whether the frequency divider works or not is realized by controlling the high ground level of the enable end.

The shorter the channel, the higher its cutoff frequency will be for different processes. In order to reach higher operating frequency, the utility model discloses a selected for use the international (SMIC)55nm technology of center, under 55nm, the cut-off frequency of MOS pipe can reach 500GHz, to the utility model discloses a, the cut-off frequency of this MOS is accomplished enough, consequently adopts this technology.

As shown in fig. 4 (the rearmost part of the document), it is a circuit structure diagram based on the existing two-frequency divider with an enable end. The power supply end of the circuit: avdd, ground: avss, input: clk, output: clkout, control: and (6) enable. The circuit is controlled by an enable end to realize the starting and the closing of the circuit.

We divide the whole circuit into 3 parts.

Part 1: the utility model discloses an utilize the transmission gate to constitute D flip-flop structure, because the transmission gate needs to control with two complete antiphase signals, and the signal end that needs to use the transmission gate among the frequency divider is clk, and the 1 st part is just used for realizing this kind of effect. We can see that clk is divided into two paths, one path is changed into ckb through a transmission gate and an inverter, the other path is changed into ck through two inverters, wherein the ckb is realized by adding one transmission gate and the ck respectively has the same delay relative to clk, and the purpose of this is to make the clock input to the loop (part 2) more matched, so that the circuit can process the signal with higher working frequency.

Section 2: this part is the main loop of the divide-by-two divider, which is used to implement the divide-by-two function of the input signal. The part is actually formed by two D latches, and the function of dividing the frequency of the input clock by two is realized by connecting the inverted signal of the output end of the second D latch to the input end of the first D latch. Compared with the existing circuit, the main loop reduces two inverters, reduces the delay of the main loop, so that the circuit speed is higher, and the circuit can process input signals with higher frequency.

Section 3: this part is the enable control part of the circuit. As shown, the input enable signal passes through an inverter to the gate of Pmos, which acts here as a switch and the control supply voltage cannot be supplied to the divider. When the enable signal is at high level, the grid end of the Pmos is at low level, the Pmos is conducted, the power supply voltage is transmitted to the circuit, and the circuit is started. When the enable signal is at low level, the gate terminal of the Pmos is at high level, the Pmos is turned off, the power supply voltage cannot be transmitted to the circuit, and the circuit is turned off. This enables the control circuit to be turned on and off. Thus, the signal is still on the main loop and does not pass through the control circuit part, and the phase noise performance is not weakened.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front end", "rear end", "both ends", "one end", "the other end" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element to which the reference is made must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides a novel two frequency dividers of area enable control end, it includes clock circuit, main loop, control end, control circuit, characterized by: the control end is provided with a high-ground level, the high-ground level is provided with a frequency divider, the clock circuit is connected with the main loop, the main loop is connected with the control circuit, and the control end is arranged on the control circuit;

the clock circuit is used for inputting a clock signal to the main loop;

the control circuit is used for inputting a power supply voltage to the main loop.

2. The novel frequency divider with enable control according to claim 1, wherein: and a clock circuit module is arranged on the frequency divider, and a transmission gate is arranged on the clock circuit module.

3. The novel frequency divider with enable control according to claim 2, wherein: the transmission gate is provided with a main loop, and the main loop is provided with a phase inverter.

4. The novel frequency divider with enable control according to claim 1, wherein: and a signal transmission path is arranged on the control circuit.

5. The novel frequency divider with enable control according to claim 1, wherein: the control circuit is provided with a power supply.