CN212811682U - Monitoring circuit and modem of airborne satellite communication data link transceiving module - Google Patents
Monitoring circuit and modem of airborne satellite communication data link transceiving module Download PDFInfo
- Publication number
- CN212811682U CN212811682U CN202022205003.2U CN202022205003U CN212811682U CN 212811682 U CN212811682 U CN 212811682U CN 202022205003 U CN202022205003 U CN 202022205003U CN 212811682 U CN212811682 U CN 212811682U
- Authority
- CN
- China
- Prior art keywords
- monitoring circuit
- port
- circuit
- airborne
- monitoring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a machine carries satellite communication data link transceiver module's monitoring circuit and has this transceiver module and monitoring circuit's machine and carries satellite communication modem to solve the problem that current equipment circuit structure is complicated, the function is redundant. The digital signal board is integrated with a signal processing unit which is an FPGA processor, the monitoring circuit comprises a data link monitoring circuit, an airborne servo monitoring circuit, an airborne BUC monitoring circuit and a flight control computer communication circuit, and the monitoring circuits respectively use the FPGA processor as a control core. The utility model overcomes among the prior art scheme defect such as function singleness, circuit structure are complicated, with too high costs.
Description
Technical Field
The utility model belongs to the technical field of satellite communication, a hardware circuit system who carries satellite communication is related to, concretely relates to airborne satellite communication data link transceiver module's monitoring circuit and have this monitoring circuit's airborne satellite communication modem.
Background
The satellite communication data link has the advantages of wide coverage range, large communication capacity, long transmission distance, strong anti-interference capability and the like. The importance of on-board monitoring as an on-board core module is becoming more and more obvious. With the development of unmanned aerial vehicles and satellite communication industries, the technology of over-the-horizon satellite communication data links is continuously mature, and the demand is continuously increased.
The forward spread spectrum signal received by the airborne data transceiving combination not only contains remote control data but also monitoring data, wherein the remote control data belongs to necessary information required by other subsystems of the aircraft platform, and the monitoring data belongs to control information of the transceiving combination, so that a monitoring module is required to distinguish in data flow.
However, the existing monitoring system of the satellite communication data link transceiver module usually needs to be equipped with a main control chip, a power supply, a storage module, an interface module and the like separately, which results in increased device volume and manufacturing cost. In addition, the monitoring system is connected with the plug-in device on one hand, and is also connected with the airborne data link module on the other hand, so that the complexity of the airborne system is increased and the working stability of the system is reduced on the one hand by the data transmission lines. Meanwhile, in order to meet EMC requirements of airborne equipment, expensive shielding transmission cables are generally required to be equipped, which also results in increased system manufacturing cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a machine carries satellite communication data link transceiver module's monitoring circuit and has this transceiver module and monitoring circuit's machine and carries satellite communication modem to solve the problem that current equipment circuit structure is complicated, the function is redundant.
According to the utility model discloses an aspect 1 provides a monitoring circuit for machine carries satellite communication data chain transceiver module, this machine carries satellite communication data chain transceiver module includes the digital signal board, and the integration has signal processing unit on this digital signal board, and this signal processing unit is the FPGA treater, monitoring circuit includes data chain monitoring circuit, machine carries servo monitoring circuit, machine carries BUC monitoring circuit and flight control computer communication circuit, above-mentioned each monitoring circuit respectively with the FPGA treater is control core.
In some embodiments, the data chain monitoring circuitry comprises: the processor comprises a GPIO port, a serial port baud rate setting port, a transmitter setting port, a receiver setting port and an onboard monitoring output port, and the GPIO port is connected with the video compression unit; the serial port baud rate setting port is connected with the interface component; the transmitter setting port is connected with a transmitter and comprises a transmitting power setting port and a transmitting frequency setting port; the receiver setting port is connected with the receiver and comprises a spread spectrum ratio setting port and a receiving frequency setting port; the airborne monitoring output port, the interface assembly and the video compression unit are respectively connected with a multiplexing circuit, and the multiplexing circuit is connected with a transmitter.
In some embodiments, the on-board servo monitoring circuitry comprises: the processor comprises a first RS422 interface, is connected with the onboard servo unit and is used for sending servo control data to the onboard servo unit and receiving servo telemetry return data from the onboard servo unit.
In some embodiments, the on-board BUC monitoring circuit comprises: the processor includes a second RS422 port connected to the onboard channel combination and the onboard antenna combination, respectively, for channel switching control and input attenuation settings.
In some embodiments, the flight control computer communication circuitry comprises: the processor performs bidirectional data transmission with the flight control computer through the LVDS interface.
According to the utility model discloses an aspect 2 still provides an airborne satellite communication modem, including airborne satellite communication data link transceiver module and according to any one of the aforesaid technical scheme monitoring circuit.
Compared with the prior art, owing to adopt above technical scheme, the utility model discloses following beneficial effect has:
the utility model discloses improve to airborne satellite communication data chain transceiver module circuit structure, with an FPGA of airborne satellite communication data chain transceiver module's signal processor sharing. Meanwhile, circuit modules such as an airborne satellite communication data link monitoring circuit, an airborne servo monitoring circuit, an airborne BUC monitoring circuit and a flight control computer communication circuit are respectively realized by utilizing rich ports of the FPGA, so that the circuit design and manufacturing cost is simplified to the greatest extent, and the defects of single function, complex circuit structure, overhigh cost and the like in the prior art are overcome.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention.
In the drawings:
fig. 1 is a schematic diagram of the overall circuit structure of the satellite communication data link transceiver module according to the present invention;
fig. 2 is a schematic diagram of the circuit structure of the digital signal board of the present invention;
fig. 3 is the utility model discloses an airborne satellite communication data link transceiver module monitoring circuit module schematic diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Referring to fig. 1, according to the embodiment of the present invention, the satellite communication data chain transceiver module includes a digital signal board 10 and an analog signal board 20, wherein the analog signal board 20 is used for performing interface adaptation on different Low Noise Block downconverters LNB (high frequency head) and an up-conversion power amplifier BUC, and providing a global clock source of the whole transceiver module. The digital signal board 10 is used to complete the functions of all the transceiving combinations, such as interface, monitoring, video coding, modulation and demodulation.
As shown in fig. 1, the analog signal board 20 is integrated with a crystal oscillator module, a first combiner, a second combiner, and a duplexer.
The crystal oscillator module is respectively connected with the first combiner and the second combiner to provide 10MHz clocks for the two combiners. The output end of the first combiner is connected with an up-conversion power amplifier BUC of the radio frequency part, the output end of the second combiner is connected with a duplexer, and the duplexer is connected with a low-noise down converter LNB of the radio frequency part.
The crystal oscillator module outputs a clock signal to the digital signal board 10 as a system operating clock of the clock chip of the digital signal board 10. The first combiner outputs a 10MHz reference clock and an intermediate frequency signal to the up-conversion power amplifier BUC, the second combiner outputs a 15V direct current voltage and a 10MHz reference clock to the duplexer, the duplexer outputs the 15V direct current voltage and the 10MHz reference clock to the low-noise down converter LNB, receives the intermediate frequency output signal of the low-noise down converter LNB and outputs the intermediate frequency output signal to the digital signal board 10.
With continued reference to fig. 1 in conjunction with fig. 2, the digital signal board 10 has integrated thereon a processor, a clock management unit, a video compression unit, an a/D conversion unit, a balun unit, an interface unit, and a power supply unit.
In some embodiments, the processor may employ an FPGA, such as a Kintex-7 family FPGA of Xilinx corporation, for example, the K7-325T family, which has rich processing resources and peripheral interfaces, so as to concentrate the processing work of the whole system into one processor, save the area of a hardware board, and reduce the power consumption.
When receiving signals, firstly receiving Ku waveband radio frequency signals through an antenna, amplifying and down-converting the Ku waveband radio frequency signals to an intermediate frequency L waveband through an LNB module, converting the L waveband signals into second differential signals through a second balun, inputting the second differential signals into an A/D conversion unit, inputting baseband digital signals into an FPGA, completing the steps of demodulation, decoding and the like in the FPGA, and finally realizing receiving.
When transmitting signals, the external interface unit inputs data to be transmitted into the FPGA, the steps of coding, framing, mapping, forming and the like are completed inside the FPGA, digital signals are input into the A/D conversion unit, digital-to-analog conversion and up-conversion to an L waveband are completed inside the A/D conversion unit, intermediate-frequency L waveband signals are input into the BUC unit and up-converted to a Ku waveband, and the signals are transmitted to the antenna to radiate out after being amplified.
As is known, according to the task requirements, a monitoring module of the satellite communication data link transceiver module analyzes the control command, and adjusts setting parameters of the video compression flow rate, the serial port baud rate, the intermediate frequency output power and frequency of the reverse link, the forward link receiving frequency, the airborne channel combination BUC switch, and the airborne antenna combination according to the command. Meanwhile, the parameters are transmitted back to the airborne flight control computer and the reverse link is transmitted back to the ground console.
According to the utility model discloses an embodiment, a monitoring circuit for satellite communication data link transceiver module includes data link monitoring circuit, machine carries servo monitoring circuit, machine carries BUC monitoring circuit and flies to control computer communication circuit, and above-mentioned each circuit respectively with the treater is the core.
Referring to fig. 3, the data link monitoring circuit includes: the processor comprises a GPIO port, a serial port baud rate setting port, a transmitter setting port, a receiver setting port and an onboard monitoring output port.
And the GPIO port is connected with the video compression unit. In the present invention, the video compression unit includes a first video compression circuit and a second video compression circuit, the first video compression circuit receives a video signal through an SDI interface (digital component serial interface), for example, and the second video compression circuit receives a PAL video signal, for example. And the GPIO port is respectively connected with the first video compression circuit and the second video compression circuit and is used for setting the compression ratio of the video compression circuit.
And the serial port baud rate setting port is connected with the interface component. The interface component comprises a serial port interface, a network port interface and the like, and is used for setting a serial port baud rate.
The transmitter setting port is connected with the transmitter and comprises a transmitting power setting port used for setting transmitting power of the transmitter and a transmitting frequency setting port used for setting transmitting frequency of the transmitter.
The receiver setting port is connected with the receiver and comprises a spread spectrum ratio setting port and a receiving frequency setting port, wherein the spread spectrum ratio setting port is used for setting a receiving spread spectrum ratio of the receiver, and the receiving frequency setting port is used for setting the receiving frequency of the receiver.
The airborne monitoring output port is connected with the input end of the multiplexing circuit and used for sending the state return data and the airborne satellite communication data link telemetry data to the reverse link transmission data multiplexing circuit, and the multiplexing circuit processes the data and the data output by the interface component, the first video compression circuit and the second video compression circuit and sends the processed data to the transmitter.
The airborne servo monitoring circuit comprises: the processor comprises a first RS422 interface, is connected with the onboard servo unit and is used for sending servo control data to the onboard servo unit and receiving servo telemetry return data from the onboard servo unit.
Airborne BUC monitoring circuit includes: the processor includes a second RS422 port connected to the onboard channel combination and the onboard antenna combination, respectively, for channel switching control and input attenuation settings.
Flight control computer communication circuit includes: the processor performs bidirectional data transmission with the flight control computer through the LVDS interface.
The processor is the processor which is used as a signal processing unit on the signal digital board 10, that is, the on-board monitoring circuit and the signal processing unit of the digital signal board 10 share one FPGA chip resource, so that an external power supply and a storage module are omitted, the multiplexing of the chip resource is realized, the circuit structure of the system is simplified, the hardware cost is saved, and the stability and the reliability of the system are improved.
The utility model discloses in, the configuration of RS422 interface parameter can be controlled to machine carries servo monitoring circuit, according to 115200 baud rate, realizes both-way communication. The monitoring circuit respectively verifies the servo remote control data and the return data, the remote control data passes the verification and is sent to the servo by using an RS422 interface; and the returned data passes the verification, the data is transmitted to a buffer area of a downlink transmitter, and the data is telemetered, packed and issued according to a satellite communication link.
The airborne BUC monitoring circuit can control the parameter configuration of the RS422 interface and realize bidirectional communication according to the 115200 baud rate. The monitoring circuit respectively verifies the BUC remote control data and the return data, the remote control data pass the verification, and the remote control data are sent to the BUC by using the RS422 interface. And the returned data passes the verification, the data is transmitted to a buffer area of a downlink transmitter, and the data is telemetered, packed and issued according to a satellite communication link.
The airborne data chain monitoring circuit is responsible for analyzing uplink remote control data and acquiring downlink remote measurement information of the satellite communication data chain. And analyzing the uplink remote control instruction, and controlling uplink and downlink intermediate frequency transmitting frequency points, intermediate frequency transmitting power, a coding mode, a spread spectrum ratio, a load rate, encryption and the like of the airborne satellite communication data chain. The method for acquiring the satellite communication data chain downlink telemetering information mainly comprises a modulation mode, a coding mode, a load rate, a spread spectrum ratio, an encryption mode, a frequency point, output power and the like.
Those skilled in the art will appreciate that the present invention is described with an emphasis on the circuit configuration of the satellite communication data link transceiver module and the monitoring circuit, rather than the signal processing algorithm, such as the signal processing software executed by the FPGA processor. Moreover, it is to be understood that, even if the present invention relates to a signal processing method executed by an FPGA processor, such as parameter setting of a data transmission interface, modulation and demodulation of signals, coding and decoding, encryption and decryption, data distribution multiplexing and monitoring, etc., the method adopts a conventional processing method known in the art, and the present invention does not relate to any improvement of the related method.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, it should be understood by those skilled in the art that: the invention can be modified or equivalent substituted for some technical features; without departing from the spirit of the present invention, it should be understood that the scope of the claims is intended to cover all such modifications and variations.
Claims (6)
1. A monitoring circuit is used for an airborne satellite communication data link transceiver module, the airborne satellite communication data link transceiver module comprises a digital signal board, a signal processing unit is integrated on the digital signal board, the signal processing unit is an FPGA processor, and the monitoring circuit is characterized by comprising a data link monitoring circuit, an airborne servo monitoring circuit, an airborne BUC monitoring circuit and a flight control computer communication circuit, and the FPGA processor is used as a control core of each monitoring circuit.
2. The monitoring circuit of claim 1, wherein the data link monitoring circuit comprises: the processor comprises a GPIO port, a serial port baud rate setting port, a transmitter setting port, a receiver setting port and an onboard monitoring output port, and the GPIO port is connected with the video compression unit; the serial port baud rate setting port is connected with the interface component; the transmitter setting port is connected with a transmitter and comprises a transmitting power setting port and a transmitting frequency setting port; the receiver setting port is connected with the receiver and comprises a spread spectrum ratio setting port and a receiving frequency setting port; the airborne monitoring output port, the interface assembly and the video compression unit are respectively connected with a multiplexing circuit, and the multiplexing circuit is connected with a transmitter.
3. The monitoring circuit of claim 1, wherein the on-board servo monitoring circuit comprises: the processor comprises a first RS422 interface, is connected with the onboard servo unit and is used for sending servo control data to the onboard servo unit and receiving servo telemetry return data from the onboard servo unit.
4. The monitoring circuit of claim 1, wherein the on-board BUC monitoring circuit comprises: the processor includes a second RS422 port connected to the onboard channel combination and the onboard antenna combination, respectively, for channel switching control and input attenuation settings.
5. The monitoring circuit of claim 1, wherein the flight control computer communication circuit comprises: the processor performs bidirectional data transmission with the flight control computer through the LVDS interface.
6. An airborne satellite communications modem comprising an airborne satellite communications data link transceiver module and its monitoring circuitry according to any of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022205003.2U CN212811682U (en) | 2020-09-30 | 2020-09-30 | Monitoring circuit and modem of airborne satellite communication data link transceiving module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022205003.2U CN212811682U (en) | 2020-09-30 | 2020-09-30 | Monitoring circuit and modem of airborne satellite communication data link transceiving module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212811682U true CN212811682U (en) | 2021-03-26 |
Family
ID=75090638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022205003.2U Active CN212811682U (en) | 2020-09-30 | 2020-09-30 | Monitoring circuit and modem of airborne satellite communication data link transceiving module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212811682U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113114334A (en) * | 2021-03-11 | 2021-07-13 | 中国电子科技集团公司第五十四研究所 | A variable frequency band 1 based on VPX architecture: 1 hot standby modulation and demodulation device |
| CN114095069A (en) * | 2021-10-29 | 2022-02-25 | 中国电子科技集团公司第五十四研究所 | Satellite-borne comprehensive payload device |
-
2020
- 2020-09-30 CN CN202022205003.2U patent/CN212811682U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113114334A (en) * | 2021-03-11 | 2021-07-13 | 中国电子科技集团公司第五十四研究所 | A variable frequency band 1 based on VPX architecture: 1 hot standby modulation and demodulation device |
| CN113114334B (en) * | 2021-03-11 | 2022-05-17 | 中国电子科技集团公司第五十四研究所 | A variable frequency band 1 based on VPX architecture: 1 hot standby modulation and demodulation device |
| CN114095069A (en) * | 2021-10-29 | 2022-02-25 | 中国电子科技集团公司第五十四研究所 | Satellite-borne comprehensive payload device |
| CN114095069B (en) * | 2021-10-29 | 2023-12-29 | 中国电子科技集团公司第五十四研究所 | Satellite-borne comprehensive effective load device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN212811682U (en) | Monitoring circuit and modem of airborne satellite communication data link transceiving module | |
| CN106571864B (en) | A kind of general multimodal information processor of aircraft based on software radio | |
| CN107332605B (en) | Measurement and control method based on Ka-S frequency band relay integrated measurement and control system | |
| CN109245833B (en) | Universal comprehensive radio frequency measurement and control system for spacecraft | |
| CN106559128A (en) | For the integrated communication device and method of microsatellite | |
| US10560132B2 (en) | Reconfigurable transmitter and receiver, and methods for reconfiguring | |
| CN106791704B (en) | A kind of multi-mode UAV TT & C communication system and method | |
| CN205665399U (en) | Low -power consumption big dipper communication navigation airborne terminal | |
| CN110611529A (en) | System for realizing integration of terahertz tracking and data relay communication | |
| CN205539477U (en) | Big dipper communication navigation integration airborne terminal | |
| CN112448728A (en) | IMA architecture-based airborne integrated radio communication navigation system and working method | |
| US20150245354A1 (en) | Method and device for sending/receiving electromagnetic signals received/sent on one or more first frequency bands | |
| CN115037347A (en) | Dual-band satellite communication simulation transponder | |
| CN114296371A (en) | Multi-mode measurement and control terminal supporting in-orbit reconstruction | |
| CN110149121B (en) | Adjustable ultra-wideband zero intermediate frequency transceiver radio frequency analog front end | |
| CN213484869U (en) | Satellite communication data link transceiver module | |
| CN113438013B (en) | Satellite data transmission and broadcast data distribution integrated device | |
| CN110365364B (en) | Radio frequency channel device and satellite transponder comprising same | |
| KR20190090144A (en) | A Communication Module for UAV Datalink Applications | |
| CN104682994A (en) | Radio frequency chip and system for wireless local area network and broadcast integrated transmission | |
| CN218071492U (en) | Multichannel frequency conversion divides combined circuit all-in-one | |
| CN115955269A (en) | Multi-track combination-based aircraft communication link wireless transmission system and method | |
| CN216490493U (en) | Satellite measurement and control satellite affair integrated system | |
| CN114422822B (en) | Unmanned aerial vehicle digital graph transmission control method supporting adaptive HDMI coding | |
| CN115441933A (en) | Software-defined satellite-borne universal communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |